Repository: open-sdr/openwifi
Branch: master
Commit: 8fd674f720f0
Files: 233
Total size: 1.9 MB
Directory structure:
gitextract_cw_8qgx2/
├── .github/
│ └── ISSUE_TEMPLATE/
│ └── issue-description.md
├── .gitmodules
├── CONTRIBUTING.md
├── LICENSE
├── LICENSES/
│ ├── AGPL-3.0-or-later.txt
│ ├── BSD-3-Clause.txt
│ ├── GPL-2.0-or-later.txt
│ └── ISC.txt
├── README.md
├── doc/
│ ├── README.md
│ ├── app_notes/
│ │ ├── 40mhz.png.license
│ │ ├── README.md
│ │ ├── ad-hoc-two-sdr.md
│ │ ├── ap-client-two-sdr.md
│ │ ├── csi-architecture.jpg.license
│ │ ├── csi-information-format.jpg.license
│ │ ├── csi-screen-shot.jpg.license
│ │ ├── csi.md
│ │ ├── csi_fuzzer.md
│ │ ├── driver_stat.md
│ │ ├── drv_fpga_dynamic_loading.md
│ │ ├── frequent_trick.md
│ │ ├── guard-interval.png.license
│ │ ├── hls.md
│ │ ├── ieee80211n.md
│ │ ├── inject_80211.md
│ │ ├── iq-architecture.jpg.license
│ │ ├── iq-capture-parameter.jpg.license
│ │ ├── iq-information-format.jpg.license
│ │ ├── iq-screen-shot.jpg.license
│ │ ├── iq.md
│ │ ├── iq_2ant-screen-shot.jpg.license
│ │ ├── iq_2ant-setup.png.license
│ │ ├── iq_2ant.md
│ │ ├── iq_ack_timing.md
│ │ ├── mimo.png.license
│ │ ├── mpdu-aggr.png.license
│ │ ├── packet-iq-self-loopback-test.md
│ │ ├── perf_counter.md
│ │ ├── radar-self-csi.md
│ │ └── subcarriers.png.license
│ ├── asic/
│ │ └── skywater-130-pdk-and-asic-considerations.md
│ ├── cite-openwifi-github-code.md
│ ├── cite-openwifi-vtc-paper.md
│ ├── img_build_instruction/
│ │ └── kuiper.md
│ ├── known_issue/
│ │ └── notter.md
│ ├── openwifi-detail.jpg.license
│ ├── publications.md
│ ├── rf-digital-if-chain-config.jpg.license
│ ├── rf-digital-if-chain-spectrum.jpg.license
│ └── videos.md
├── driver/
│ ├── Makefile
│ ├── hw_def.h
│ ├── make_all.sh
│ ├── openofdm_rx/
│ │ ├── Makefile
│ │ └── openofdm_rx.c
│ ├── openofdm_tx/
│ │ ├── Makefile
│ │ └── openofdm_tx.c
│ ├── rx_intf/
│ │ ├── Makefile
│ │ └── rx_intf.c
│ ├── sdr.c
│ ├── sdr.h
│ ├── sdrctl_intf.c
│ ├── side_ch/
│ │ ├── Makefile
│ │ ├── make_driver.sh
│ │ ├── side_ch.c
│ │ └── side_ch.h
│ ├── sysfs_intf.c
│ ├── tx_intf/
│ │ ├── Makefile
│ │ └── tx_intf.c
│ ├── xilinx_dma/
│ │ ├── README.md
│ │ ├── make_xilinx_dma.sh
│ │ └── xilinx_dma.c
│ └── xpu/
│ ├── Makefile
│ └── xpu.c
├── kernel_boot/
│ ├── 10-network-device.rules
│ ├── 70-persistent-net.rules
│ ├── ad9361.patch
│ ├── ad9361_conv.patch
│ ├── ad9361_private.patch
│ ├── axi_hdmi_crtc.patch
│ ├── boards/
│ │ ├── adrv9361z7035/
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ └── u-boot.elf
│ │ ├── adrv9361z7035_fmc/
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ └── u-boot.elf
│ │ ├── adrv9364z7020/
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ └── u-boot.elf
│ │ ├── antsdr/
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ ├── notes.md
│ │ │ └── u-boot.elf
│ │ ├── antsdr_e200/
│ │ │ ├── README.md
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ └── u-boot.elf
│ │ ├── e310v2/
│ │ │ ├── README.md
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ └── u-boot.elf
│ │ ├── neptunesdr/
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ └── u-boot.elf
│ │ ├── sdrpi/
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ ├── notes.md
│ │ │ └── u-boot.elf
│ │ ├── zc702_fmcs2/
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ └── u-boot.elf
│ │ ├── zc706_fmcs2/
│ │ │ ├── devicetree.dtb
│ │ │ ├── devicetree.dts
│ │ │ └── u-boot.elf
│ │ ├── zcu102_fmcs2/
│ │ │ ├── bl31.elf
│ │ │ ├── system.dtb
│ │ │ ├── system.dts
│ │ │ └── u-boot_xilinx_zynqmp_zcu102_revA.elf
│ │ └── zed_fmcs2/
│ │ ├── devicetree.dtb
│ │ ├── devicetree.dts
│ │ └── u-boot.elf
│ ├── build_boot_bin.sh
│ ├── build_zynqmp_boot_bin.sh
│ ├── kernel_config
│ ├── kernel_config_zynqmp
│ └── kernel_patch_readme.md
├── openwifi-arch.jpg.license
└── user_space/
├── agc_settings.sh
├── arbitrary_iq_gen/
│ ├── iq_single_carrier_1000000Hz_512.txt
│ └── single_carrier_gen.m
├── boot_bin_gen.sh
├── build_wpa_supplicant_wo11b.sh
├── cd_adi_iio_dir.sh
├── check_calib_inf.sh
├── csi_fuzzer.sh
├── csi_fuzzer_scan.sh
├── cw_disable.sh
├── cw_max_min_cfg.sh
├── dhcpd.conf
├── difs_disable.sh
├── driver_nl80211.patch
├── drv_and_fpga_package_gen.sh
├── eifs_by_last_rx_fail_disable.sh
├── eifs_by_last_tx_fail_disable.sh
├── eifs_disable.sh
├── fast_reg_log/
│ ├── fast_reg_log.c
│ └── fast_reg_log_analyzer.m
├── fosdem-11ag.sh
├── fosdem.sh
├── hostapd-openwifi-11ag.conf
├── hostapd-openwifi.conf
├── inject_80211/
│ ├── Makefile
│ ├── analyze_80211.c
│ ├── ieee80211_radiotap.h
│ ├── inject_80211.c
│ ├── inject_80211.h
│ ├── inject_80211.sh
│ ├── radiotap.c
│ ├── radiotap.h
│ ├── unaligned.h
│ └── uthash.h
├── link_perf_test.sh
├── load_fpga_img.sh
├── monitor_ch.sh
├── nav_disable.sh
├── nic_back_to_normal.sh
├── openwifi_ad9361_fir.ftr
├── openwifi_ad9361_fir_tx_0MHz.ftr
├── openwifi_ad9361_fir_tx_0MHz_11n.ftr
├── openwifi_ad9361_fir_tx_0MHz_11n_narrow1.ftr
├── populate_driver_userspace.sh
├── populate_kernel_image_module_reboot.sh
├── post_config.sh
├── prepare_kernel.sh
├── receiver_phase_offset_override.sh
├── rf_init.sh
├── rf_init_11n.sh
├── rssi_ad9361_show.sh
├── rssi_openwifi_show.sh
├── rx_gain_show.sh
├── rx_stat_show.sh
├── sdcard_boot_update.sh
├── sdr-ad-hoc-join.sh
├── sdr-ad-hoc-up.sh
├── sdrctl_src/
│ ├── Makefile
│ ├── cmd.c
│ ├── nl80211.h
│ ├── nl80211_testmode_def.h
│ ├── sdrctl.c
│ ├── sdrctl.h
│ ├── sections.c
│ └── version.sh
├── set_dbg_ch0.sh
├── set_dbg_ch1.sh
├── set_dbg_ch2.sh
├── set_lbt_th.sh
├── set_restrict_freq.sh
├── set_rx_gain_auto.sh
├── set_rx_gain_manual.sh
├── set_rx_monitor_all.sh
├── set_rx_target_sender_mac_addr.sh
├── set_tx_lo.sh
├── set_tx_port.sh
├── setup_once.sh
├── side_ch_ctl_src/
│ ├── iq_capture.py
│ ├── iq_capture_2ant.py
│ ├── iq_capture_freq_offset.py
│ ├── save_iq_to_txt_for_verilog_sim.m
│ ├── show_iq_snr.m
│ ├── side_ch_ctl.c
│ ├── side_info_display.py
│ ├── test_iq_2ant_file_display.m
│ ├── test_iq_file_ack_timing_display.m
│ ├── test_iq_file_display.m
│ └── test_side_info_file_display.m
├── slice_cfg.sh
├── stat_enable.sh
├── system_top.bif
├── transfer_driver_userspace_to_board.sh
├── transfer_kernel_image_module_to_board.sh
├── tx_intf_iq_data_to_sysfs.sh
├── tx_intf_iq_send.sh
├── tx_prio_queue_show.sh
├── tx_stat_show.sh
├── update_sdcard.sh
├── webserver/
│ ├── index.html
│ ├── openwifi-detail.jpg.license
│ └── openwifi-logo-small.jpg.license
├── wgd.sh
├── wpa-connect.conf
├── wpa-openwifi.conf
└── wpa-testap.conf
================================================
FILE CONTENTS
================================================
================================================
FILE: .github/ISSUE_TEMPLATE/issue-description.md
================================================
---
name: Issue description
about: Please report issue by this template
title: ''
labels: ''
assignees: ''
---
0. Could you send email to xianjun.jiao@ugent.be to introduce your self?
1. Our image is used directly or you build your own image?
2. What is your own modification?
3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision
4. Board/hardware type
5. WiFi channel number
6. Steps to reproduce the issue, and the related error message, screenshot, etc
7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"
8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods
9. Any other thing we need to know for helping you better?
================================================
FILE: .gitmodules
================================================
[submodule "adi-linux"]
path = adi-linux
url = https://github.com/analogdevicesinc/linux.git
[submodule "adi-linux-64"]
path = adi-linux-64
url = https://github.com/analogdevicesinc/linux.git
================================================
FILE: CONTRIBUTING.md
================================================
CLA([Individual](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/openwifi-Individual.pdf), [Entity](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/openwifi-Entity.pdf)) needs to be signed and sent to Filip.Louagie@UGent.be before you contributing.
CLA is generated by the [Project Harmony](http://www.harmonyagreements.org/index.html).
================================================
FILE: LICENSE
================================================
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License by making exceptions from one or more of its conditions.
Additional permissions that are applicable to the entire Program shall
be treated as though they were included in this License, to the extent
that they are valid under applicable law. If additional permissions
apply only to part of the Program, that part may be used separately
under those permissions, but the entire Program remains governed by
this License without regard to the additional permissions.
When you convey a copy of a covered work, you may at your option
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it. (Additional permissions may be written to require their own
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Notwithstanding any other provision of this License, for material you
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it) with contractual assumptions of liability to the recipient, for
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All other non-permissive additional terms are considered "further
restrictions" within the meaning of section 10. If the Program as you
received it, or any part of it, contains a notice stating that it is
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a further restriction but permits relicensing or conveying under this
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not survive such relicensing or conveying.
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where to find the applicable terms.
Additional terms, permissive or non-permissive, may be stated in the
form of a separately written license, or stated as exceptions;
the above requirements apply either way.
8. Termination.
You may not propagate or modify a covered work except as expressly
provided under this License. Any attempt otherwise to propagate or
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However, if you cease all violation of this License, then your
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holder fails to notify you of the violation by some reasonable means
prior to 60 days after the cessation.
Moreover, your license from a particular copyright holder is
reinstated permanently if the copyright holder notifies you of the
violation by some reasonable means, this is the first time you have
received notice of violation of this License (for any work) from that
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your receipt of the notice.
Termination of your rights under this section does not terminate the
licenses of parties who have received copies or rights from you under
this License. If your rights have been terminated and not permanently
reinstated, you do not qualify to receive new licenses for the same
material under section 10.
9. Acceptance Not Required for Having Copies.
You are not required to accept this License in order to receive or
run a copy of the Program. Ancillary propagation of a covered work
occurring solely as a consequence of using peer-to-peer transmission
to receive a copy likewise does not require acceptance. However,
nothing other than this License grants you permission to propagate or
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You may not impose any further restrictions on the exercise of the
rights granted or affirmed under this License. For example, you may
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rights granted under this License, and you may not initiate litigation
(including a cross-claim or counterclaim in a lawsuit) alleging that
any patent claim is infringed by making, using, selling, offering for
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work thus licensed is called the contributor's "contributor version".
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owned or controlled by the contributor, whether already acquired or
hereafter acquired, that would be infringed by some manner, permitted
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but do not include claims that would be infringed only as a
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Each contributor grants you a non-exclusive, worldwide, royalty-free
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In the following three paragraphs, a "patent license" is any express
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If you convey a covered work, knowingly relying on a patent license,
and the Corresponding Source of the work is not available for anyone
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available, or (2) arrange to deprive yourself of the benefit of the
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consistent with the requirements of this License, to extend the patent
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in a country, would infringe one or more identifiable patents in that
country that you have reason to believe are valid.
If, pursuant to or in connection with a single transaction or
arrangement, you convey, or propagate by procuring conveyance of, a
covered work, and grant a patent license to some of the parties
receiving the covered work authorizing them to use, propagate, modify
or convey a specific copy of the covered work, then the patent license
you grant is automatically extended to all recipients of the covered
work and works based on it.
A patent license is "discriminatory" if it does not include within
the scope of its coverage, prohibits the exercise of, or is
conditioned on the non-exercise of one or more of the rights that are
specifically granted under this License. You may not convey a covered
work if you are a party to an arrangement with a third party that is
in the business of distributing software, under which you make payment
to the third party based on the extent of your activity of conveying
the work, and under which the third party grants, to any of the
parties who would receive the covered work from you, a discriminatory
patent license (a) in connection with copies of the covered work
conveyed by you (or copies made from those copies), or (b) primarily
for and in connection with specific products or compilations that
contain the covered work, unless you entered into that arrangement,
or that patent license was granted, prior to 28 March 2007.
Nothing in this License shall be construed as excluding or limiting
any implied license or other defenses to infringement that may
otherwise be available to you under applicable patent law.
12. No Surrender of Others' Freedom.
If conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot convey a
covered work so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you may
not convey it at all. For example, if you agree to terms that obligate you
to collect a royalty for further conveying from those to whom you convey
the Program, the only way you could satisfy both those terms and this
License would be to refrain entirely from conveying the Program.
13. Remote Network Interaction; Use with the GNU General Public License.
Notwithstanding any other provision of this License, if you modify the
Program, your modified version must prominently offer all users
interacting with it remotely through a computer network (if your version
supports such interaction) an opportunity to receive the Corresponding
Source of your version by providing access to the Corresponding Source
from a network server at no charge, through some standard or customary
means of facilitating copying of software. This Corresponding Source
shall include the Corresponding Source for any work covered by version 3
of the GNU General Public License that is incorporated pursuant to the
following paragraph.
Notwithstanding any other provision of this License, you have
permission to link or combine any covered work with a work licensed
under version 3 of the GNU General Public License into a single
combined work, and to convey the resulting work. The terms of this
License will continue to apply to the part which is the covered work,
but the work with which it is combined will remain governed by version
3 of the GNU General Public License.
14. Revised Versions of this License.
The Free Software Foundation may publish revised and/or new versions of
the GNU Affero General Public License from time to time. Such new versions
will be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the
Program specifies that a certain numbered version of the GNU Affero General
Public License "or any later version" applies to it, you have the
option of following the terms and conditions either of that numbered
version or of any later version published by the Free Software
Foundation. If the Program does not specify a version number of the
GNU Affero General Public License, you may choose any version ever published
by the Free Software Foundation.
If the Program specifies that a proxy can decide which future
versions of the GNU Affero General Public License can be used, that proxy's
public statement of acceptance of a version permanently authorizes you
to choose that version for the Program.
Later license versions may give you additional or different
permissions. However, no additional obligations are imposed on any
author or copyright holder as a result of your choosing to follow a
later version.
15. Disclaimer of Warranty.
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
16. Limitation of Liability.
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
17. Interpretation of Sections 15 and 16.
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
Copyright (C)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Affero General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Affero General Public License for more details.
You should have received a copy of the GNU Affero General Public License
along with this program. If not, see .
Also add information on how to contact you by electronic and paper mail.
If your software can interact with users remotely through a computer
network, you should also make sure that it provides a way for users to
get its source. For example, if your program is a web application, its
interface could display a "Source" link that leads users to an archive
of the code. There are many ways you could offer source, and different
solutions will be better for different programs; see section 13 for the
specific requirements.
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU AGPL, see
.
================================================
FILE: LICENSES/AGPL-3.0-or-later.txt
================================================
GNU AFFERO GENERAL PUBLIC LICENSE
Version 3, 19 November 2007
Copyright (C) 2007 Free Software Foundation, Inc.
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The GNU Affero General Public License is a free, copyleft license for
software and other kinds of works, specifically designed to ensure
cooperation with the community in the case of network server software.
The licenses for most software and other practical works are designed
to take away your freedom to share and change the works. By contrast,
our General Public Licenses are intended to guarantee your freedom to
share and change all versions of a program--to make sure it remains free
software for all its users.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
them if you wish), that you receive source code or can get it if you
want it, that you can change the software or use pieces of it in new
free programs, and that you know you can do these things.
Developers that use our General Public Licenses protect your rights
with two steps: (1) assert copyright on the software, and (2) offer
you this License which gives you legal permission to copy, distribute
and/or modify the software.
A secondary benefit of defending all users' freedom is that
improvements made in alternate versions of the program, if they
receive widespread use, become available for other developers to
incorporate. Many developers of free software are heartened and
encouraged by the resulting cooperation. However, in the case of
software used on network servers, this result may fail to come about.
The GNU General Public License permits making a modified version and
letting the public access it on a server without ever releasing its
source code to the public.
The GNU Affero General Public License is designed specifically to
ensure that, in such cases, the modified source code becomes available
to the community. It requires the operator of a network server to
provide the source code of the modified version running there to the
users of that server. Therefore, public use of a modified version, on
a publicly accessible server, gives the public access to the source
code of the modified version.
An older license, called the Affero General Public License and
published by Affero, was designed to accomplish similar goals. This is
a different license, not a version of the Affero GPL, but Affero has
released a new version of the Affero GPL which permits relicensing under
this license.
The precise terms and conditions for copying, distribution and
modification follow.
TERMS AND CONDITIONS
0. Definitions.
"This License" refers to version 3 of the GNU Affero General Public License.
"Copyright" also means copyright-like laws that apply to other kinds of
works, such as semiconductor masks.
"The Program" refers to any copyrightable work licensed under this
License. Each licensee is addressed as "you". "Licensees" and
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To "modify" a work means to copy from or adapt all or part of the work
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earlier work or a work "based on" the earlier work.
A "covered work" means either the unmodified Program or a work based
on the Program.
To "propagate" a work means to do anything with it that, without
permission, would make you directly or secondarily liable for
infringement under applicable copyright law, except executing it on a
computer or modifying a private copy. Propagation includes copying,
distribution (with or without modification), making available to the
public, and in some countries other activities as well.
To "convey" a work means any kind of propagation that enables other
parties to make or receive copies. Mere interaction with a user through
a computer network, with no transfer of a copy, is not conveying.
An interactive user interface displays "Appropriate Legal Notices"
to the extent that it includes a convenient and prominently visible
feature that (1) displays an appropriate copyright notice, and (2)
tells the user that there is no warranty for the work (except to the
extent that warranties are provided), that licensees may convey the
work under this License, and how to view a copy of this License. If
the interface presents a list of user commands or options, such as a
menu, a prominent item in the list meets this criterion.
1. Source Code.
The "source code" for a work means the preferred form of the work
for making modifications to it. "Object code" means any non-source
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A "Standard Interface" means an interface that either is an official
standard defined by a recognized standards body, or, in the case of
interfaces specified for a particular programming language, one that
is widely used among developers working in that language.
The "System Libraries" of an executable work include anything, other
than the work as a whole, that (a) is included in the normal form of
packaging a Major Component, but which is not part of that Major
Component, and (b) serves only to enable use of the work with that
Major Component, or to implement a Standard Interface for which an
implementation is available to the public in source code form. A
"Major Component", in this context, means a major essential component
(kernel, window system, and so on) of the specific operating system
(if any) on which the executable work runs, or a compiler used to
produce the work, or an object code interpreter used to run it.
The "Corresponding Source" for a work in object code form means all
the source code needed to generate, install, and (for an executable
work) run the object code and to modify the work, including scripts to
control those activities. However, it does not include the work's
System Libraries, or general-purpose tools or generally available free
programs which are used unmodified in performing those activities but
which are not part of the work. For example, Corresponding Source
includes interface definition files associated with source files for
the work, and the source code for shared libraries and dynamically
linked subprograms that the work is specifically designed to require,
such as by intimate data communication or control flow between those
subprograms and other parts of the work.
The Corresponding Source need not include anything that users
can regenerate automatically from other parts of the Corresponding
Source.
The Corresponding Source for a work in source code form is that
same work.
2. Basic Permissions.
All rights granted under this License are granted for the term of
copyright on the Program, and are irrevocable provided the stated
conditions are met. This License explicitly affirms your unlimited
permission to run the unmodified Program. The output from running a
covered work is covered by this License only if the output, given its
content, constitutes a covered work. This License acknowledges your
rights of fair use or other equivalent, as provided by copyright law.
You may make, run and propagate covered works that you do not
convey, without conditions so long as your license otherwise remains
in force. You may convey covered works to others for the sole purpose
of having them make modifications exclusively for you, or provide you
with facilities for running those works, provided that you comply with
the terms of this License in conveying all material for which you do
not control copyright. Those thus making or running the covered works
for you must do so exclusively on your behalf, under your direction
and control, on terms that prohibit them from making any copies of
your copyrighted material outside their relationship with you.
Conveying under any other circumstances is permitted solely under
the conditions stated below. Sublicensing is not allowed; section 10
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3. Protecting Users' Legal Rights From Anti-Circumvention Law.
No covered work shall be deemed part of an effective technological
measure under any applicable law fulfilling obligations under article
11 of the WIPO copyright treaty adopted on 20 December 1996, or
similar laws prohibiting or restricting circumvention of such
measures.
When you convey a covered work, you waive any legal power to forbid
circumvention of technological measures to the extent such circumvention
is effected by exercising rights under this License with respect to
the covered work, and you disclaim any intention to limit operation or
modification of the work as a means of enforcing, against the work's
users, your or third parties' legal rights to forbid circumvention of
technological measures.
4. Conveying Verbatim Copies.
You may convey verbatim copies of the Program's source code as you
receive it, in any medium, provided that you conspicuously and
appropriately publish on each copy an appropriate copyright notice;
keep intact all notices stating that this License and any
non-permissive terms added in accord with section 7 apply to the code;
keep intact all notices of the absence of any warranty; and give all
recipients a copy of this License along with the Program.
You may charge any price or no price for each copy that you convey,
and you may offer support or warranty protection for a fee.
5. Conveying Modified Source Versions.
You may convey a work based on the Program, or the modifications to
produce it from the Program, in the form of source code under the
terms of section 4, provided that you also meet all of these conditions:
a) The work must carry prominent notices stating that you modified
it, and giving a relevant date.
b) The work must carry prominent notices stating that it is
released under this License and any conditions added under section
7. This requirement modifies the requirement in section 4 to
"keep intact all notices".
c) You must license the entire work, as a whole, under this
License to anyone who comes into possession of a copy. This
License will therefore apply, along with any applicable section 7
additional terms, to the whole of the work, and all its parts,
regardless of how they are packaged. This License gives no
permission to license the work in any other way, but it does not
invalidate such permission if you have separately received it.
d) If the work has interactive user interfaces, each must display
Appropriate Legal Notices; however, if the Program has interactive
interfaces that do not display Appropriate Legal Notices, your
work need not make them do so.
A compilation of a covered work with other separate and independent
works, which are not by their nature extensions of the covered work,
and which are not combined with it such as to form a larger program,
in or on a volume of a storage or distribution medium, is called an
"aggregate" if the compilation and its resulting copyright are not
used to limit the access or legal rights of the compilation's users
beyond what the individual works permit. Inclusion of a covered work
in an aggregate does not cause this License to apply to the other
parts of the aggregate.
6. Conveying Non-Source Forms.
You may convey a covered work in object code form under the terms
of sections 4 and 5, provided that you also convey the
machine-readable Corresponding Source under the terms of this License,
in one of these ways:
a) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by the
Corresponding Source fixed on a durable physical medium
customarily used for software interchange.
b) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by a
written offer, valid for at least three years and valid for as
long as you offer spare parts or customer support for that product
model, to give anyone who possesses the object code either (1) a
copy of the Corresponding Source for all the software in the
product that is covered by this License, on a durable physical
medium customarily used for software interchange, for a price no
more than your reasonable cost of physically performing this
conveying of source, or (2) access to copy the
Corresponding Source from a network server at no charge.
c) Convey individual copies of the object code with a copy of the
written offer to provide the Corresponding Source. This
alternative is allowed only occasionally and noncommercially, and
only if you received the object code with such an offer, in accord
with subsection 6b.
d) Convey the object code by offering access from a designated
place (gratis or for a charge), and offer equivalent access to the
Corresponding Source in the same way through the same place at no
further charge. You need not require recipients to copy the
Corresponding Source along with the object code. If the place to
copy the object code is a network server, the Corresponding Source
may be on a different server (operated by you or a third party)
that supports equivalent copying facilities, provided you maintain
clear directions next to the object code saying where to find the
Corresponding Source. Regardless of what server hosts the
Corresponding Source, you remain obligated to ensure that it is
available for as long as needed to satisfy these requirements.
e) Convey the object code using peer-to-peer transmission, provided
you inform other peers where the object code and Corresponding
Source of the work are being offered to the general public at no
charge under subsection 6d.
A separable portion of the object code, whose source code is excluded
from the Corresponding Source as a System Library, need not be
included in conveying the object code work.
A "User Product" is either (1) a "consumer product", which means any
tangible personal property which is normally used for personal, family,
or household purposes, or (2) anything designed or sold for incorporation
into a dwelling. In determining whether a product is a consumer product,
doubtful cases shall be resolved in favor of coverage. For a particular
product received by a particular user, "normally used" refers to a
typical or common use of that class of product, regardless of the status
of the particular user or of the way in which the particular user
actually uses, or expects or is expected to use, the product. A product
is a consumer product regardless of whether the product has substantial
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the only significant mode of use of the product.
"Installation Information" for a User Product means any methods,
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and execute modified versions of a covered work in that User Product from
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modification has been made.
If you convey an object code work under this section in, or with, or
specifically for use in, a User Product, and the conveying occurs as
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User Product is transferred to the recipient in perpetuity or for a
fixed term (regardless of how the transaction is characterized), the
Corresponding Source conveyed under this section must be accompanied
by the Installation Information. But this requirement does not apply
if neither you nor any third party retains the ability to install
modified object code on the User Product (for example, the work has
been installed in ROM).
The requirement to provide Installation Information does not include a
requirement to continue to provide support service, warranty, or updates
for a work that has been modified or installed by the recipient, or for
the User Product in which it has been modified or installed. Access to a
network may be denied when the modification itself materially and
adversely affects the operation of the network or violates the rules and
protocols for communication across the network.
Corresponding Source conveyed, and Installation Information provided,
in accord with this section must be in a format that is publicly
documented (and with an implementation available to the public in
source code form), and must require no special password or key for
unpacking, reading or copying.
7. Additional Terms.
"Additional permissions" are terms that supplement the terms of this
License by making exceptions from one or more of its conditions.
Additional permissions that are applicable to the entire Program shall
be treated as though they were included in this License, to the extent
that they are valid under applicable law. If additional permissions
apply only to part of the Program, that part may be used separately
under those permissions, but the entire Program remains governed by
this License without regard to the additional permissions.
When you convey a copy of a covered work, you may at your option
remove any additional permissions from that copy, or from any part of
it. (Additional permissions may be written to require their own
removal in certain cases when you modify the work.) You may place
additional permissions on material, added by you to a covered work,
for which you have or can give appropriate copyright permission.
Notwithstanding any other provision of this License, for material you
add to a covered work, you may (if authorized by the copyright holders of
that material) supplement the terms of this License with terms:
a) Disclaiming warranty or limiting liability differently from the
terms of sections 15 and 16 of this License; or
b) Requiring preservation of specified reasonable legal notices or
author attributions in that material or in the Appropriate Legal
Notices displayed by works containing it; or
c) Prohibiting misrepresentation of the origin of that material, or
requiring that modified versions of such material be marked in
reasonable ways as different from the original version; or
d) Limiting the use for publicity purposes of names of licensors or
authors of the material; or
e) Declining to grant rights under trademark law for use of some
trade names, trademarks, or service marks; or
f) Requiring indemnification of licensors and authors of that
material by anyone who conveys the material (or modified versions of
it) with contractual assumptions of liability to the recipient, for
any liability that these contractual assumptions directly impose on
those licensors and authors.
All other non-permissive additional terms are considered "further
restrictions" within the meaning of section 10. If the Program as you
received it, or any part of it, contains a notice stating that it is
governed by this License along with a term that is a further
restriction, you may remove that term. If a license document contains
a further restriction but permits relicensing or conveying under this
License, you may add to a covered work material governed by the terms
of that license document, provided that the further restriction does
not survive such relicensing or conveying.
If you add terms to a covered work in accord with this section, you
must place, in the relevant source files, a statement of the
additional terms that apply to those files, or a notice indicating
where to find the applicable terms.
Additional terms, permissive or non-permissive, may be stated in the
form of a separately written license, or stated as exceptions;
the above requirements apply either way.
8. Termination.
You may not propagate or modify a covered work except as expressly
provided under this License. Any attempt otherwise to propagate or
modify it is void, and will automatically terminate your rights under
this License (including any patent licenses granted under the third
paragraph of section 11).
However, if you cease all violation of this License, then your
license from a particular copyright holder is reinstated (a)
provisionally, unless and until the copyright holder explicitly and
finally terminates your license, and (b) permanently, if the copyright
holder fails to notify you of the violation by some reasonable means
prior to 60 days after the cessation.
Moreover, your license from a particular copyright holder is
reinstated permanently if the copyright holder notifies you of the
violation by some reasonable means, this is the first time you have
received notice of violation of this License (for any work) from that
copyright holder, and you cure the violation prior to 30 days after
your receipt of the notice.
Termination of your rights under this section does not terminate the
licenses of parties who have received copies or rights from you under
this License. If your rights have been terminated and not permanently
reinstated, you do not qualify to receive new licenses for the same
material under section 10.
9. Acceptance Not Required for Having Copies.
You are not required to accept this License in order to receive or
run a copy of the Program. Ancillary propagation of a covered work
occurring solely as a consequence of using peer-to-peer transmission
to receive a copy likewise does not require acceptance. However,
nothing other than this License grants you permission to propagate or
modify any covered work. These actions infringe copyright if you do
not accept this License. Therefore, by modifying or propagating a
covered work, you indicate your acceptance of this License to do so.
10. Automatic Licensing of Downstream Recipients.
Each time you convey a covered work, the recipient automatically
receives a license from the original licensors, to run, modify and
propagate that work, subject to this License. You are not responsible
for enforcing compliance by third parties with this License.
An "entity transaction" is a transaction transferring control of an
organization, or substantially all assets of one, or subdividing an
organization, or merging organizations. If propagation of a covered
work results from an entity transaction, each party to that
transaction who receives a copy of the work also receives whatever
licenses to the work the party's predecessor in interest had or could
give under the previous paragraph, plus a right to possession of the
Corresponding Source of the work from the predecessor in interest, if
the predecessor has it or can get it with reasonable efforts.
You may not impose any further restrictions on the exercise of the
rights granted or affirmed under this License. For example, you may
not impose a license fee, royalty, or other charge for exercise of
rights granted under this License, and you may not initiate litigation
(including a cross-claim or counterclaim in a lawsuit) alleging that
any patent claim is infringed by making, using, selling, offering for
sale, or importing the Program or any portion of it.
11. Patents.
A "contributor" is a copyright holder who authorizes use under this
License of the Program or a work on which the Program is based. The
work thus licensed is called the contributor's "contributor version".
A contributor's "essential patent claims" are all patent claims
owned or controlled by the contributor, whether already acquired or
hereafter acquired, that would be infringed by some manner, permitted
by this License, of making, using, or selling its contributor version,
but do not include claims that would be infringed only as a
consequence of further modification of the contributor version. For
purposes of this definition, "control" includes the right to grant
patent sublicenses in a manner consistent with the requirements of
this License.
Each contributor grants you a non-exclusive, worldwide, royalty-free
patent license under the contributor's essential patent claims, to
make, use, sell, offer for sale, import and otherwise run, modify and
propagate the contents of its contributor version.
In the following three paragraphs, a "patent license" is any express
agreement or commitment, however denominated, not to enforce a patent
(such as an express permission to practice a patent or covenant not to
sue for patent infringement). To "grant" such a patent license to a
party means to make such an agreement or commitment not to enforce a
patent against the party.
If you convey a covered work, knowingly relying on a patent license,
and the Corresponding Source of the work is not available for anyone
to copy, free of charge and under the terms of this License, through a
publicly available network server or other readily accessible means,
then you must either (1) cause the Corresponding Source to be so
available, or (2) arrange to deprive yourself of the benefit of the
patent license for this particular work, or (3) arrange, in a manner
consistent with the requirements of this License, to extend the patent
license to downstream recipients. "Knowingly relying" means you have
actual knowledge that, but for the patent license, your conveying the
covered work in a country, or your recipient's use of the covered work
in a country, would infringe one or more identifiable patents in that
country that you have reason to believe are valid.
If, pursuant to or in connection with a single transaction or
arrangement, you convey, or propagate by procuring conveyance of, a
covered work, and grant a patent license to some of the parties
receiving the covered work authorizing them to use, propagate, modify
or convey a specific copy of the covered work, then the patent license
you grant is automatically extended to all recipients of the covered
work and works based on it.
A patent license is "discriminatory" if it does not include within
the scope of its coverage, prohibits the exercise of, or is
conditioned on the non-exercise of one or more of the rights that are
specifically granted under this License. You may not convey a covered
work if you are a party to an arrangement with a third party that is
in the business of distributing software, under which you make payment
to the third party based on the extent of your activity of conveying
the work, and under which the third party grants, to any of the
parties who would receive the covered work from you, a discriminatory
patent license (a) in connection with copies of the covered work
conveyed by you (or copies made from those copies), or (b) primarily
for and in connection with specific products or compilations that
contain the covered work, unless you entered into that arrangement,
or that patent license was granted, prior to 28 March 2007.
Nothing in this License shall be construed as excluding or limiting
any implied license or other defenses to infringement that may
otherwise be available to you under applicable patent law.
12. No Surrender of Others' Freedom.
If conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot convey a
covered work so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you may
not convey it at all. For example, if you agree to terms that obligate you
to collect a royalty for further conveying from those to whom you convey
the Program, the only way you could satisfy both those terms and this
License would be to refrain entirely from conveying the Program.
13. Remote Network Interaction; Use with the GNU General Public License.
Notwithstanding any other provision of this License, if you modify the
Program, your modified version must prominently offer all users
interacting with it remotely through a computer network (if your version
supports such interaction) an opportunity to receive the Corresponding
Source of your version by providing access to the Corresponding Source
from a network server at no charge, through some standard or customary
means of facilitating copying of software. This Corresponding Source
shall include the Corresponding Source for any work covered by version 3
of the GNU General Public License that is incorporated pursuant to the
following paragraph.
Notwithstanding any other provision of this License, you have
permission to link or combine any covered work with a work licensed
under version 3 of the GNU General Public License into a single
combined work, and to convey the resulting work. The terms of this
License will continue to apply to the part which is the covered work,
but the work with which it is combined will remain governed by version
3 of the GNU General Public License.
14. Revised Versions of this License.
The Free Software Foundation may publish revised and/or new versions of
the GNU Affero General Public License from time to time. Such new versions
will be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the
Program specifies that a certain numbered version of the GNU Affero General
Public License "or any later version" applies to it, you have the
option of following the terms and conditions either of that numbered
version or of any later version published by the Free Software
Foundation. If the Program does not specify a version number of the
GNU Affero General Public License, you may choose any version ever published
by the Free Software Foundation.
If the Program specifies that a proxy can decide which future
versions of the GNU Affero General Public License can be used, that proxy's
public statement of acceptance of a version permanently authorizes you
to choose that version for the Program.
Later license versions may give you additional or different
permissions. However, no additional obligations are imposed on any
author or copyright holder as a result of your choosing to follow a
later version.
15. Disclaimer of Warranty.
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
16. Limitation of Liability.
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
17. Interpretation of Sections 15 and 16.
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
Copyright (C)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Affero General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Affero General Public License for more details.
You should have received a copy of the GNU Affero General Public License
along with this program. If not, see .
Also add information on how to contact you by electronic and paper mail.
If your software can interact with users remotely through a computer
network, you should also make sure that it provides a way for users to
get its source. For example, if your program is a web application, its
interface could display a "Source" link that leads users to an archive
of the code. There are many ways you could offer source, and different
solutions will be better for different programs; see section 13 for the
specific requirements.
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU AGPL, see
.
================================================
FILE: LICENSES/BSD-3-Clause.txt
================================================
Modified BSD license (no advertisement clause):
Copyright (c) 2002-2017, Jouni Malinen and contributors
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name(s) of the above-listed copyright holder(s) nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
================================================
FILE: LICENSES/GPL-2.0-or-later.txt
================================================
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too.
When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things.
To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it.
For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights.
We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software.
Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations.
Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and modification follow.
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program.
You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License.
c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program.
In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License.
3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.)
The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable.
If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance.
5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it.
6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License.
7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program.
If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances.
It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice.
This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns.
Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation.
10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found.
Copyright (C)
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker.
, 1 April 1989 Ty Coon, President of Vice
This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License.
Standard License Header
Copyright (C)
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
================================================
FILE: LICENSES/ISC.txt
================================================
Copyright
Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
================================================
FILE: README.md
================================================
# openwifi
**openwifi:** Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio).
- We remain committed to open source, which is our foundation. To access advanced features and dedicated support, consider a **SUBSCRIPTION**. More info on https://openwifi.tech
[[Download img and Quick start](#Download-img-and-Quick-start)] [[known issue](doc/known_issue/notter.md)] [[**Tips for Windows users**](https://github.com/open-sdr/openwifi/discussions/341)]
This repository includes Linux driver and software. **openwifi-hw** repository has the FPGA design. It is **YOUR RESPONSIBILITY** to follow your **LOCAL SPECTRUM REGULATION** or use **CABLE** to avoid potential interference over the air.
[[Project document](doc/README.md)]
[[Application notes](doc/app_notes/README.md)]
[[Videos](doc/videos.md)]
[[Publications and How to Cite](doc/publications.md)]
[[maillist](https://lists.ugent.be/wws/subscribe/openwifi)]
Openwifi code has dual licenses. [AGPLv3](https://github.com/open-sdr/openwifi/blob/master/LICENSE) is the opensource license. For non-opensource and advanced feature license, please fill a contact form on https://openwifi.tech. Openwifi project also leverages some 3rd party modules. It is user's duty to check and follow licenses of those modules according to the purpose/usage. You can find [an example explanation from Analog Devices](https://github.com/analogdevicesinc/hdl/blob/master/LICENSE) for this compound license conditions. [[How to contribute]](https://github.com/open-sdr/openwifi/blob/master/CONTRIBUTING.md).
**Features:**
- 802.11a/g/n [[IEEE 802.11n (Wi-Fi 4)](doc/app_notes/ieee80211n.md)]
- 20MHz bandwidth; [70 MHz to 6 GHz frequency range](doc/README.md#let-openwifi-work-at-arbitrary-frequency)
- Mode tested: [Ad-hoc](doc/app_notes/ad-hoc-two-sdr.md); [Station; AP](doc/app_notes/ap-client-two-sdr.md), Monitor
- [DCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)](doc/app_notes/frequent_trick.md)
- [802.11 packet injection and fuzzing](doc/app_notes/inject_80211.md)
- [CSI](doc/app_notes/csi.md): Channel State Information, freq offset, equalizer to computer
- [CSI fuzzer](doc/app_notes/csi_fuzzer.md): Create artificial channel response in WiFi transmitter
- [CSI radar](doc/app_notes/radar-self-csi.md): Moving detection. Joint radar and communication
- [[IQ capture](doc/app_notes/iq.md)]: real-time AGC, RSSI, IQ sample to computer. [[Dual antenna version](doc/app_notes/iq_2ant.md)]
- [Configurable channel access priority parameters](doc/app_notes/frequent_trick.md):
- CCA threshold, receiver sensitivity, etc
- duration of RTS/CTS, CTS-to-self
- SIFS/DIFS/xIFS/slot-time/CW/etc
- [Time slicing based on MAC address (time gated/scheduled FPGA queues)](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html#sdr-tx-time-slicing)
- Easy to change bandwidth and [frequency](doc/README.md#let-openwifi-work-at-arbitrary-frequency):
- 2MHz for 802.11ah in sub-GHz
- 10MHz for 802.11p/vehicle in 5.9GHz
- **802.11ax** and more advanced features, check: https://openwifi.tech
**Performance (best case: aggregation/AMPDU on):**
- iperf: TCP 40~50Mbps; UDP 50Mbps
- EVM -38dB; MCS0 sensitivity -92dBm; MCS7 -73dBm. (FMCOMMS2 2.4GHz; cable and OTA test)
**Supported SDR platforms:**
board_name|Description|Vivado license
----------|-----------|--------------
zc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Need
zed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|**NO** need
adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|**NO** need
adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Need
zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|**NO** need
antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|**NO** need
e310v2|[MicroPhase](https://github.com/MicroPhase/) new antsdr [Notes](kernel_boot/boards/e310v2/README.md)|**NO** need
antsdr_e200|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO (smaller/cheaper) [Notes](kernel_boot/boards/antsdr_e200/README.md)|**NO** need
sdrpi|[HexSDR](https://github.com/HexSDR/) SDR in Raspberry Pi size [Notes](kernel_boot/boards/sdrpi/notes.md)|**NO** need
zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Need
neptunesdr|Low cost Zynq 7020 + AD9361 board (Unofficial!)|**NO** need
LibreSDR|[Low cost Zynq 7020 + AD9361 board (Unofficial!)](https://github.com/pavelyazev/openwifi-libresdr)|**NO** need
- Check [Porting guide](#Porting-guide) for your new board if it isn't in the list.
- board_name is used to identify FPGA design in openwifi-hw/boards/ and FPGA image in openwifi-hw-img/boards
- Don't have any boards? Or you like JTAG boot instead of SD card? Check our test bed [w-iLab.t](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html) tutorial.
[[Download img and Quick start](#Download-img-and-Quick-start)]
[[Basic operations](#Basic-operations)]
[[Update FPGA](#Update-FPGA)]
[[Update Driver](#Update-Driver)]
[[Update sdrctl](#Update-sdrctl)]
[[Update Misc Helpers](#Update-Misc-Helpers)]
[[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)]
[[Special note for 11b](#Special-note-for-11b)]
[[Porting guide](#Porting-guide)]
[[Project document](doc/README.md)]
[[Application notes](doc/app_notes/README.md)]
## Download img and Quick start
- Download [openwifi img](https://users.ugent.be/~xjiao/openwifi-1.5.0-shahecheng.img.xz), unzip and burn it into a SD card (>=16GB). After this operation, the SD card should have two partitions: BOOT and rootfs. To flash the SD card, SD card tool software (such as Startup Disk Creator in Ubuntu) or dd command can be used:
```
sudo dd bs=512 count=31116288 if=openwifi-xyz.img of=/dev/your_sdcard_dev
(To have correct count value, better to check the .img file actual situation by "fdisk -l img_filename")
```
- Config the **correct files in the BOOT partition** according to the **board you have** by operation on your computer:
- Copy files in **BOOT/openwifi/board_name** to the base directory of BOOT partition.
- Delete the **rootfs/root/kernel_modules** directory (if exist).
- Delete the **rootfs/etc/network/interfaces.new** directory (if exist).
- Insert the SD card to the board. Configure the board in SD booting mode. Connect antennas. Power on.
- Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with password **openwifi**.
```
ssh root@192.168.10.122
```
- If not successful, check [known issue](doc/known_issue/notter.md)
- Then, run openwifi AP and the on board webserver
```
raspi-config --expand-rootfs (Only needed when your SD card > 16GB. Run and reboot)
./openwifi/setup_once.sh (Reboot the board. Only need to run once for new board)
cd openwifi
./wgd.sh
./fosdem.sh
(Use "./wgd.sh 1" to enable experimental AMPDU aggregation on top of 11n)
(Use "./fosdem-11ag.sh" to force 11a/g mode)
```
**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!
- After you see the "openwifi" SSID on your device (Phone/Laptop/etc), connect it (If not get 192.168.13.* IP automatically, check [known issue](doc/known_issue/notter.md)). Browser to 192.168.13.1 on your device, you should see the webpage hosted by the webserver on board.
- Note 1: If your device doesn't support 5GHz (ch44), please change the **hostapd-openwifi.conf** on board and re-run fosdem.sh.
- Note 2: After ~2 hours, the Viterbi decoder will halt (Xilinx Evaluation License). Just reload FPGA ([method](doc/app_notes/drv_fpga_dynamic_loading.md)) or simply power cycle the board if it happens. (If output of "./sdrctl dev sdr0 get reg rx 20" is always the same, it means the decoder halts)
- To give the Wi-Fi client internet access, configure routing/NAT **on the PC**:
```
sudo sysctl -w net.ipv4.ip_forward=1
sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE
sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX
```
**ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet).
If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC.
- To monitor **real-time CSI (Chip State Information)**, such as timestamp, frequency offset, channel state, equalizer, please refer to [[CSI notes](doc/app_notes/csi.md)].
## Basic operations
The board actually is an Linux/Ubuntu computer which is running **hostapd** to offer Wi-Fi AP functionality over the Wi-Fi Network Interface (NIC). The NIC is implemented by openwifi-hw FPGA design. We use the term **"On board"** to indicate that the commands should be executed after ssh login to the board. **"On PC"** means the commands should run on PC.
- Bring up the openwifi NIC sdr0:
```
cd ~/openwifi && ./wgd.sh
(Use "./wgd.sh 1" to enable experimental AMPDU aggregation)
```
- Use openwifi as client to connect other AP (Change wpa-connect.conf on board firstly):
```
route del default gw 192.168.10.1
wpa_supplicant -i sdr0 -c wpa-connect.conf &
dhclient sdr0
```
- Use openwifi in ad-hoc mode: Please check **sdr-ad-hoc-up.sh**, **sdr-ad-hoc-join.sh** and [this app note](./doc/app_notes/ad-hoc-two-sdr.md).
- Use openwifi in monitor mode: Please check **monitor_ch.sh** and [this app note](./doc/app_notes/inject_80211.md).
- The Linux native Wi-Fi tools/Apps (iwconfig/ifconfig/iwlist/iw/hostapd/wpa_supplicant/etc) can run over openwifi NIC in the same way as commercial Wi-Fi chip.
- **sdrctl** is a dedicated tool to access openwifi driver/FPGA, please check [project document](./doc/README.md) for more information.
## Update FPGA
Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to always copy the latest files in the [user_space](./user_space) directory on to the board. Then update the FPGA&Driver according to the Quick start of [this app note](doc/app_notes/radar-self-csi.md#quick-start). Following instructions are doing the same thing with extra info for environment setup.
(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for better understanding of updating FPGA and driver files without rebooting/power-cycle)
- Install Vivado 2021.1. Make sure install Vitis as well. You should have this directory: your_Xilinx_install_directory/Vitis (NOT Vitis_HLS!)
- If the Vitis is not installed, you can add it by running "Xilinx Design Tools --> Add Design Tools for Devices 2021.1" from Xilinx program group/menu in your OS start menu.
- Setup environment variables (use absolute path):
```
export XILINX_DIR=your_Xilinx_install_directory
(Example: export XILINX_DIR=/opt/Xilinx. The Xilinx directory should include sth like: Downloads, Vitis, etc.)
export OPENWIFI_HW_IMG_DIR=your_openwifi-hw-img_directory
(The directory where you get the open-sdr/openwifi-hw-img repo via git clone)
export BOARD_NAME=your_board_name
```
- Pick the FPGA bitstream from openwifi-hw-img, generate system_top.bit.bin and transfer it on board via ssh channel:
```
cd openwifi/user_space; ./boot_bin_gen.sh $XILINX_DIR $BOARD_NAME $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top.xsa
scp ./system_top.bit.bin root@192.168.10.122:openwifi/
```
- Now the system_top.bit.bin is onboard in /root/openwifi/ directory. When wgd.sh runs onboard from that directory, it will discover the FPGA img file system_top.bit.bin and load it before loading driver .ko files.
## Update Driver
Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to always copy the latest files in the [user_space](./user_space) directory on to the board. Then update the FPGA&Driver according to the Quick start of [this app note](doc/app_notes/radar-self-csi.md#quick-start). Following instructions are doing the same thing with extra info for environment setup.
(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for better understanding of updating FPGA and driver files without rebooting/power-cycle)
- Prepare Analog Devices Linux kernel source code (only need to run once):
```
sudo apt install flex bison libssl-dev device-tree-compiler u-boot-tools -y
cd openwifi/user_space; ./prepare_kernel.sh $XILINX_DIR ARCH_BIT
(For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
```
- Compile the latest openwifi driver
```
cd openwifi/driver; ./make_all.sh $XILINX_DIR ARCH_BIT
(For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
(More arguments (max 5) beyond above two will be converted to "#define argument" in pre_def.h for conditional compiling)
```
- Copy the driver files to the board via ssh channel
```
cd openwifi/driver; scp `find ./ -name \*.ko` root@192.168.10.122:openwifi/
```
Now you can use **wgd.sh** on board to load the new openwifi driver. **wgd.sh** also tries to reload FPGA img if system_top.bit.bin presents in the same directory.
Find more information in [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md).
**Note**: If you have symbol or version error while loadng the driver, it could be because the kernel in the SD card image is too old. In this case, you need put the linux kernel image generated by prepare_kernel.sh (check [[Update Driver](#Update-Driver)]) to the BOOT partition of SD card. The kernel image file name: adi-linux/arch/arm/boot/uImage (32bit); adi-linux-64/arch/arm64/boot/Image (64bit).
## Update sdrctl
- Copy the sdrctl source files to the board via ssh channel
```
cd openwifi/user_space/sdrctl_src; scp `find ./ -name \*` root@192.168.10.122:openwifi/sdrctl_src/
```
- Compile the sdrctl **on board**:
```
cd ~/openwifi/sdrctl_src/ && make clean && make && cp sdrctl ../ && cd ..
```
## Update Misc Helpers
- Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for more convenient way of updating FPGA and driver files without rebooting/power-cycle.
- Update new kernel, modules and devicetree to the board
- Prepare in the host PC (run scripts in the user_space directory)
- `prepare_kernel.sh`
- `boot_bin_gen.sh`
- `transfer_kernel_image_module_to_board.sh`
- Run on board (in the /root/ directory)
- `populate_kernel_image_module_reboot.sh`
If kernel version is changed, you should run this script again after rebooting. Because the first time run it with old kernel will not setup correct liked directory name for the new kernel version.
- Suggest also update the Linux rootfs (https://wiki.analog.com/resources/tools-software/linux-software/kuiper-linux/update)
- `git clone https://github.com/analogdevicesinc/linux_image_ADI-scripts.git` on board
- `apt update`
- `adi_update_tools.sh`
- Update new drivers .ko files to the board
- Prepare in the host PC
- `make_all.sh` (in the driver directory)
- `transfer_driver_userspace_to_board.sh`
- Run on board (in the /root/ directory)
- `populate_driver_userspace.sh`
- FPGA and driver on board update scripts
- Setup [ftp server](https://ubuntu.com/server/docs/service-ftp) on PC, allow anonymous and change ftp root directory to the openwifi directory.
- On board:
```
./sdcard_boot_update.sh $BOARD_NAME
(Above command downloads uImage, BOOT.BIN and devicetree.dtb, then copy them into boot partition. Remember to power cycle)
./wgd.sh remote
(Above command downloads driver files, and brings up sdr0)
```
- Access the board disk/rootfs like a disk:
- On PC: "File manager --> Connect to Server...", input: sftp://root@192.168.10.122/root
- Input password "openwifi"
## Build openwifi Linux image from scratch
- For the ADI Kuiper image, please check [kuiper.md](./doc/img_build_instruction/kuiper.md)
## Special note for 11b
Openwifi only applies OFDM as its modulation scheme and as a result, it is not backward compatible with 802.11b clients or modes of operation. This is usually the case during beacon transmission, connection establishment, and robust communication.
As a solution to this problem, openwifi can be fully controlled only if communicating with APs/clients instantiated using hostapd/wpa_supplicant userspace programs respectively.
For hostapd program, 802.11b rates can be suppressed using configuration commands (i.e. supported_rates, basic_rates) and an example configuration file is provided (i.e. hostapd-openwifi.conf). One small caveat to this one comes from fullMAC Wi-Fi cards as they must implement the *NL80211_TXRATE_LEGACY* NetLink handler at the device driver level.
On the other hand, the wpa_supplicant program on the client side (commercial Wi-Fi dongle/board) cannot suppress 802.11b rates out of the box in 2.4GHz band, so there will be an issue when connecting openwifi (OFDM only). A patched wpa_supplicant should be used at the client side.
```
sudo apt-get install libssl1.0-dev
cd openwifi/user_space; ./build_wpa_supplicant_wo11b.sh
```
## Porting guide
This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 2021_r1 of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl).
- Open the fmcomms2 + zc706 reference design at hdl/projects/fmcomms2/zc706 (Please read Analog Devices help)
- Open the openwifi design zc706_fmcs2 at openwifi-hw/boards/zc706_fmcs2 (Please read openwifi-hw repository)
- "Open Block Design", you will see the differences between openwifi and the reference design. Both in "diagram" and in "Address Editor".
- The address/interrupts of FPGA blocks hooked to the ARM bus should be put/aligned to the devicetree file openwifi/kernel_boot/boards/zc706_fmcs2/devicetree.dts. Linux will parse the devicetree.dtb when booting to know information of attached device (FPGA blocks in our case).
- We use dtc command to get devicetree.dts converted from devicetree.dtb in [Analog Devices Linux image](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images), then do modification according to what we have added/modified to the reference design.
- Please learn the script in [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to understand how we generate devicetree.dtb, BOOT.BIN, Linux kernel and put them together to build the full SD card image.
## License
This project is available as open source under the terms of the AGPL 3.0 Or later. However, some elements are being licensed under GPL 2-0 or later and BSD 3 license . For accurate information, please check individual files.
## Funding
This project received funding through [ORCA project](https://www.orca-project.eu/). ORCA project is funded by the EU's Horizon2020 programme under agreement number 732174.
This project received funding through [NGI Zero Core](https://nlnet.nl/core/), a fund established by [NLnet](https://nlnet.nl/) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu/) program. Learn more at the NLnet project pages: [802.11n feature of openwifi](https://nlnet.nl/project/OpenWifi-80211n/), [openwifi: 802.11a/g/n maturity](https://nlnet.nl/project/OpenWifi-maturity/), [Extensive openwifi support for OpenWRT](https://nlnet.nl/project/OpenWifi-OpenWRT/)
================================================
FILE: doc/README.md
================================================
# Openwifi document
Above figure shows software and hardware/FPGA modules that compose the openwifi design. The module name is equal/similar to the source code file name. Driver module source codes are in openwifi/driver/. FPGA module source codes are in openwifi-hw repository. The user space tool sdrctl source code are in openwifi/user_space/sdrctl_src/. [Sysfs](https://man7.org/linux/man-pages/man5/sysfs.5.html) is another channel that is offered to do userspace-driver communication by mapping driver variables to virtual files. Check [this app note](app_notes/driver_stat.md#Sysfs-explanation) for further explanation.
- [Driver and software overall principle](#Driver-and-software-overall-principle)
- [sdrctl command](#sdrctl-command)
- [Rx packet flow and filtering config](#Rx-packet-flow-and-filtering-config)
- [Tx packet flow and config](#Tx-packet-flow-and-config)
- [Understand the timestamp of WiFi packet](#Understand-the-timestamp-of-WiFi-packet)
- [Regulation and channel config](#Regulation-and-channel-config)
- [Analog and digital frequency design](#Analog-and-digital-frequency-design)
- [Debug methods](#Debug-methods)
- [Test mode driver](#Test-mode-driver)
- [Application notes](app_notes/README.md)
## Driver and software overall principle
[Linux mac80211 subsystem](https://www.kernel.org/doc/html/v4.16/driver-api/80211/mac80211.html), as a part of [Linux wireless](https://wireless.wiki.kernel.org/en/developers/documentation/mac80211), defines a set of APIs ([ieee80211_ops](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#c.ieee80211_ops)) to rule the Wi-Fi chip driver behavior. SoftMAC Wi-Fi chip driver implements (subset of) those APIs. That is why Linux can support so many Wi-Fi chips of different chip vendors. Different mode (AP/Client/ad-hoc/mesh) might need different set of APIs
openwifi driver (sdr.c) implements following APIs of ieee80211_ops:
- **tx**. It is called when upper layer has a packet to send
- **start**. It is called when NIC up. (ifconfig sdr0 up)
- **stop**. It is called when NIC down. (ifconfig sdr0 down)
- **add_interface**. It is called when NIC is created
- **remove_interface**. It is called when NIC is deleted
- **config**. It is called when upper layer wants to change channel/frequency (like the scan operation)
- **set_antenna**. Set/select the tx/rx antenna
- **get_antenna**. Read the current tx/rx antenna idx/combination
- **bss_info_changed**. It is called when upper layer believe some BSS parameters need to be changed (BSSID, TX power, beacon interval, etc)
- **conf_tx**. It is called when upper layer needs to config/change some tx parameters (AIFS, CW_MIN, CW_MAX, TXOP, etc)
- **prepare_multicast**. It is called when upper layer needs to prepare multicast, currently only a empty function hook is present.
- **configure_filter**. It is called when upper layer wants to config/change the [frame filtering](#Rx-packet-flow-and-filtering-config) rule in FPGA.
- **rfkill_poll**. It is called when upper layer wants to know the RF status (ON/OFF).
- **get_tsf**. It is called when upper layer wants to get 64bit FPGA timer value (TSF - Timing synchronization function)
- **set_tsf**. It is called when upper layer wants to set 64bit FPGA timer value
- **reset_tsf**. It is called when upper layer wants to reset 64bit FPGA timer value
- **set_rts_threshold**. It is called when upper layer wants to change the threshold (packet length) for turning on RTS mechanism
- **ampdu_action**. AMPDU (Aggregated Mac PDU) related operations
- **testmode_cmd**. It is called when upper layer has test command for us. [sdrctl command](#sdrctl-command) message is handled by this function.
Above APIs are called by upper layer (Linux mac80211 subsystem). When they are called, the driver (sdr.c) will do necessary job via openwifi FPGA implementation. If necessary, the driver will call other component drivers, like tx_intf_api/rx_intf_api/openofdm_tx_api/openofdm_rx_api/xpu_api, for help.
After receiving a packet from the air, FPGA will raise interrupt (if the frame filtering rule allows) to Linux, then the function openwifi_rx_interrupt() of openwifi driver (sdr.c) will be triggered. In that function, ieee80211_rx_irqsafe() API is used to give the packet and related information (timestamp, rssi, etc) to upper layer.
The packet sending is initiated by upper layer towards openwifi driver. After the packet is sent by the driver over FPGA to the air, the upper layer will expect a sending report from the driver. Each time FPGA sends a packet, an interrupt will be raised to Linux and trigger openwifi_tx_interrupt(). This function will report the sending result (failed? succeeded? number of retransmissions, etc.) to upper layer via ieee80211_tx_status_irqsafe() API.
## sdrctl command
Besides the Linux native Wi-Fi control programs, such as ifconfig/iw/iwconfig/iwlist/wpa_supplicant/hostapd/etc, openwifi offers a user space tool sdrctl to access openwifi specific functionalities, such as time sharing of the interface between two network slices, arbitrary Tx/Rx frequency, Tx attenuation, etc. you may find more details of the slicing mechanism [here](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html#sdr-tx-time-slicing).
sdrctl is implemented as nl80211 testmode command and communicates with openwifi driver (function openwifi_testmode_cmd() in sdrctl_intf.c) via Linux nl80211--cfg80211--mac80211 path
### Get and set a parameter
```
sdrctl dev sdr0 get para_name
sdrctl dev sdr0 set para_name value
```
para_name|meaning|comment
---------|-------|----
slice_idx|the slice that will be set/get|0 to 3. After finishing all slice config, **set slice_idx to 4** to synchronize all slices. Otherwise the start/end of different slices have different actual time
addr|target MAC address of tx slice_idx|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
slice_total|tx slice_idx cycle length in us|for length 50ms, you set 49999
slice_start|tx slice_idx cycle start time in us|for start at 10ms, you set 10000
slice_end| tx slice_idx cycle end time in us|for end at 40ms, you set 39999
tsf| sets TSF value| it requires two values "high_TSF low_TSF". Decimal
### Get and set a register of a module
```
sdrctl dev sdr0 get reg module_name reg_idx
sdrctl dev sdr0 set reg module_name reg_idx reg_value
```
module_name **drv_rx**/**drv_tx**/**drv_xpu**/**rf** refers to the corresponding driver functionality. Related registers are defined in sdr.h. Search drv_rx_reg_val/drv_tx_reg_val/drv_xpu_reg_val/rf_reg_val to see their functionalities.
module_name **rx_intf**/**tx_intf**/**rx**/**tx**/**xpu** FPGA modules (rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu). Related register addresses are defined in hw_def.h and mapped to slv_regX in .v file (X is the register index). Check rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu.c and .v files to see their functionalities.
module name **rf** refers to RF (ad9xxx front-end). The agent register rf_reg_val is defined in sdr.h.
Please be aware that some registers are set by driver in real-time (instructed by Linux mac80211), so be careful when set them manually.
module_name: **drv_rx** (for full list, search drv_rx_reg_val in sdr.c)
reg_idx|meaning|comment
-------|-------|----
0|receiver action threshold|receiver will not react (short preamble search and further) if the signal strength is less than this threshold. N means -NdBm
4|rx antenna selection|0:rx1, 1:rx2
7|dmesg print control|please check Debug methods section in this page
(In the **comment** column, you may get a list of **decimalvalue(0xhexvalue):explanation** for a register, only use the **decimalvalue** in the sdrctl command)
module_name: **drv_tx** (for full list, search drv_tx_reg_val in sdr.c)
reg_idx|meaning|comment
-------|-------|----
0|override Linux rate control of non-ht TX unicast data packet|0:auto by Linux, 4:6M, 5:9M, 6:12M, 7:18M, 8:24M, 9:36M, 10:48M, 11:54M
1|override Linux rate control of ht TX unicast data packet|0:auto by Linux, 4:6.5M, 5:13M, 6:19.5M,7:26M, 8:39M, 9:52M, 10:58.5M, 11:65M (add 16 to these values for short GI rate)
2|override Linux rate control of vht (11ac)|not implemented yet
3|override Linux rate control of he (11ax)|not implemented yet
4|tx antenna selection|0:tx1, 1:tx2
7|dmesg print control|please check Debug methods section in this page
module_name: **drv_xpu** (for full list, search drv_xpu_reg_val in sdr.c)
reg_idx|meaning|comment
-------|-------|----
0|LBT/CCA threshold|0: automatic threshold by ad9361_rf_set_channel(). others -- N means -NdBm fixed threshold
7|git revision when build the driver|return the git revision in hex format
module_name: **rf**
reg_idx|meaning|comment
-------|-------|----
0|TX attenuation in dB\*1000|example: set to 3000 for 3dB attenuation
1|TX frequency in MHz|example: set to 5000 for 5GHz -- override Linux channenl tuning/control
5|RX frequency in MHz|example: set to 4000 for 4GHz -- override Linux channenl tuning/control
module_name: **rx_intf** (for full list, check rx_intf.c and **slv_reg** in rx_intf.v)
reg_idx|meaning|comment
-------|-------|----
0|reset|each bit is connected to rx_intf.v internal sub-module. 1 -- reset; 0 -- normal
1|trigger for ILA debug|bit4 and bit0. Please check slv_reg1 in rx_intf.v
2|enable/disable rx interrupt|256(0x100):disable, 0:enable
3|get loopback I/Q from tx_intf|256(0x100):from tx_intf, 0:from ad9361 ADC
4|baseband clock and IQ fifo in/out control|no use anymore -- for old bb rf independent mode
5|control/config dma to cpu|check rx_intf.v slv_reg5
6|abnormal packet length threshold|bit31-16 to store the threshold. if the packet length is not in the range of 14 to threshold, terminate the dma to cpu
7|source selection of rx dma to cpu|check rx_intf.v slv_reg7
8|reserved|reserved
9|number of dma symbol to cpu|only valid in manual mode (slv_reg5[5]==1). normally the dma is set automatically by the received packet length
10|rx adc fifo reading control|check rx_intf.v slv_reg10
11|rx digital I/Q gain|number of bit shift to left. default 4 in rx_intf.c: rx_intf_api->RX_INTF_REG_BB_GAIN_write(4)
12|timeout/reset control of dma to cpu|check rx_intf.v slv_reg12
13|delay from RX DMA complete to RX packet interrupt to cpu|unit 0.1us
16|rx antenna selection|0:ant0, 1:ant1. default 0
module_name: **tx_intf** (for full list, check tx_intf.c and **slv_reg** in tx_intf.v)
reg_idx|meaning|comment
-------|-------|----
0|reset|each bit is connected to tx_intf.v internal sub-module. 1 -- reset; 0 -- normal
1|DUC config or tx arbitrary IQ write port|DUC is removed already. Now it is used to write arbitrary IQ to tx_intf for test purpose
2|phy tx auto start config|check tx_intf.v slv_reg2
4|CTS to Self config|auto set by cts_reg in openwifi_tx of sdr.c. bit31: enable/disable, bit30: rate selection: 1: use traffic rate, 0: manual rate in bit7-4, bit23-8: duration field
5|csi fuzzer config|check CSI fuzzer app note
6|CTS to Self sending delay (for SIFS)|unit 0.1us. bit13-0 for 2.4GHz, bit29-16 for 5GHz
7|tx arbitrary IQ config|check tx_intf.v slv_reg7
8|tx config per packet|automatically set per packet in openwifi_tx() via tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config)
9|reserved|reserved
10|dac input and dma control|check tx_intf.v slv_reg10
11|threshold for FPGA fifo almost full|driver(sdr.c) read 1bit flag in slv_reg21 (4bit in total for 4 queue) to know the FPGA fifo/queue is almost full.
12|threshold to pause openofdm_tx|unit: number of sample. back pressure flow control for I/Q generation speed of openofdm_tx
13|tx I/Q digital gain before dac|find the optimal value (and test record) in tx_intf.c: tx_intf_api->TX_INTF_REG_BB_GAIN_write
14|tx interrupt config|196612(0x30004):disable, 4:enable. check tx_intv.v slv_reg14
15|ampdu action config|set automatically in driver (sdr.c) by openwifi_ampdu_action()
16|tx antenna selection and cdd control|bit1: 0 or 1 to select ant0 or 1. bit4: 1 to enable simple cdd (two antennas have 1 sample tx delay)
17|phy config per packet|aggregation/rate/GI/ht/non-ht/etc. automatically set by driver tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_write(phy_hdr_config)
21|queue almost full flag|4bit for 4 queue. criteria is the threshold in slv_reg11. check by tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read() in sdr.c
22|tx status0 per pkt sent|cw,num_slot_random,linux_prio,tx_queue_idx,bd_wr_idx,num_retrans -- per pkt info read by tx interrupt after the pkt sent
23|tx status1 per pkt sent|blk_ack_resp_ssn, pkt_cnt -- per pkt info read by tx interrupt after the pkt sent
24|tx status2 per pkt sent|blk_ack_bitmap_low -- per pkt info read by tx interrupt after the pkt sent
25|tx status3 per pkt sent|blk_ack_bitmap_high -- per pkt info read by tx interrupt after the pkt sent
26|FPGA tx queue runtime length|bit6-0: queue0; bit14-8: queue1; bit22-16: queue2; bit30-24: queue3
module_name: **rx** (for full list, check openofdm_rx.c and **slv_reg** in openofdm_rx.v)
reg_idx|meaning|comment
-------|-------|----
0|reset|each bit is connected to openofdm_rx.v internal sub-module. 1 -- reset; 0 -- normal
1|misc settings|bit0: 1--force smoothing; 0--auto by ht header. bit4: 1--disable all smoothing; 0--let bit0 decide. bit8: 0--high sensitivity sync short; 1--less fake sync short. bit12: 0--watchdog runs regardless power trigger; 1--runs only when power trigger. bit13: 0--watchdog runs regardless state; 1--runs only when state <= S_DECODE_SIGNAL. bit16: 0--enable watchdog eq monitor; 1--disable eq monitor
2|power trigger and dc detection threshold|bit10-0: signal level below this threshold won't trigger demodulation. the unit is rssi_half_db, check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm. bit23-16: threshold to prevent dc (or low frequency interference) triggered demodulation
3|minimum plateau used for short preamble detection|initialized by openofdm_rx.c: openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write
4|soft decoding flag and abnormal packet length threshold|bit0 for soft decoding: 0--hard; 1--soft. bit31-16: if the packet length is longer this threshold, terminate demodulation. bit15-12: minimum packet length threshold to terminate demodulation
5|fft_win_shift and small eq monitor threshold|bit3-0: fft window shift (default 4). bit9-4: threshold of how many very small eq out is counted to decide whether reset receiver
17|selector for watchdog event counter|0--phase_offset(sync_short) too big. 1--too many eq out small values. 2--dc is detected (threshold slv_reg2[23:16]). 3--packet too short. 4--packet too long.
18|sync_short phase_offset (frequency offset) threshold|watchdog will reset receiver if phase_offset is above the threshold
19|sync_short phase_offset override|bit31: 1--enable override; 0--disable. bit15-0: value to be set (SIGNED value!)
20|history of PHY rx state|read only. If the last digit readback is always 3, it means the Viterbi decoder stops working
21|read back Fc_in_MHz and sync_short phase_offset|bit31-16: Fc_in_MHz. bit15-0: phase_offset
30|read back watchdog event counter(selected by reg 17)|write to this register, the event counter (selected by reg 17) will be cleared
31|git revision when build the receiver|returned register value means git revision in hex format
module_name: **tx** (for full list, check openofdm_tx.c and **slv_reg** in openofdm_tx.v)
reg_idx|meaning|comment
-------|-------|----
0|reset|each bit is connected to openofdm_tx.v internal sub-module. 1 -- reset; 0 -- normal
1|pilot scrambler initial state|lowest 7 bits are used. 127(0x7F) by default in openofdm_tx.c
2|data scrambler initial state|lowest 7 bits are used. 127(0x7F) by default in openofdm_tx.c
20|reserved|reserved
module_name: **xpu** (for full list, check xpu.c and **slv_reg** in xpu.v)
reg_idx|meaning|comment
-------|-------|----
0|reset|each bit is connected to xpu.v internal sub-module. 1 -- reset; 0 -- normal
1|rx packet and I/Q config when tx|bit0 0: auto control (auto self-rx-IQ-mute when tx), 1:manual control by bit31 (1 self-IQ-mute; 0 unmute). bit2 0: rx packet filtering is configured by Linux, 1: no rx packet filtering, send all to Linux
2|TSF timer low 32bit write|only write this register won't trigger the TSF timer reload. should use together with register for high 31bit
3|TSF timer high 31bit write|falling edge of register MSB will trigger the TSF timer reload, which means write '1' then '0' to bit31 (bit30-0 for TSF)
4|band, channel and ERP short slot setting|for CSMA engine config. set automatically by Linux. manual set could be overrided unless you change sdr.c. Channel means frequency in MHz
5|DIFS and backoff advance (us), abnormal pkt length threshold|advance (us) for tx preparation before the end of DIFS/backoff. bit7-0:DIFS advance, bit15-8: backoff advance. bit31-16: if the packet length is not in the range of 14 to this threshold, terminate pkt filtering procedure
6|multi purpose CSMA settings|bit7-0: forced channel idle (us) after decoding done to avoid false alarm caused by strong "AGC tail" signal. bit31: NAV disable, bit30: DIFS disable, bit29: EIFS disable, bit28: dynamic CW disable (when disable, CW is taken from bit19-16). (value 1 -- forced disable; 0 -- normal/enable)
7|RSSI and ad9361 gpio/gain delay setting (sync with IQ rssi)|bit26-16: offset for rssi report to Linux; bit6-0 delay (number of sample) of ad9361 gpio/gain to sync with IQ sample rssi/amplitude
8|RSSI threshold for CCA (channel idle/busy)|set by ad9361_rf_set_channel automatically. the unit is rssi_half_db, check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm
9|some low MAC time setting|bit31 0:auto, 1:manual. When manual, bit6-0: PHY rx delay, bit13-7: SIFS, bit18-14: slot time, bit23-19: ofdm symbol time, bit30-24: preamble+SIG time. unit us. check xpu.v (search slv_reg9)
10|BB RF delay setting|unit 0.1us. bit7-0: BB RF delay, bit14-8: RF end extended time on top of the delay. bit22-16: delay between bb tx start to RF tx on (lo or port control via spi). bit30-24: delay between bb tx end to RF tx off. check xpu.v (search slv_reg10)
11|ACK control and max num retransmission|bit4: 0:normal ACK tx/reply, 1:disable auto ACK tx/reply in FPGA. bit5: 0:normal ACK rx from peer, 1:not expecting ACK rx from peer. bit3-0: if bit3==0, the number of retransmission is decided by Linux. if bit3==1, the max num retransmission is taken from bit2-0
12|AMPDU control|bit0: indicate low MAC start to receive AMPDU. bit4-1: tid. bit31: tid enable (by default, tid is not enabled and we decode AMPDU of all tid)
13|spi controller config|1: disable spi control and Tx RF is always on; 0: enable spi control and Tx RF only on (lo/port) when pkt sending
16|setting when wait for ACK in 2.4GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet
17|setting when wait for ACK in 5GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet
18|setting for sending ACK|unit 0.1us. bit14-0: ACK sending delay in 2.4GHz, bit30-16: ACK sending delay in 5GHz
19|CW min and max setting for 4 FPGA queues|bit3-0: CW min for queue 0, bit7-4: CW max for queue 0, bit11-8: CW min for queue 1, bit15-12: CW max for queue 1, bit19-16: CW min for queue 2, bit23-20: CW max for queue 2, bit27-24: CW min for queue 3, bit31-28: CW max for queue 3. automatically decided by Linux via openwifi_conf_tx of sdr.c
20|slice/queue-tx-gate total cycle length|bit21-20: queue selection. bit19-0: total cycle length in us
21|slice/queue-tx-gate start time in the cycle|bit21-20: queue selection. bit19-0: start time in us
22|slice/queue-tx-gate end time in the cycle|bit21-20: queue selection. bit19-0: end time in us
26|CTS to RTS setting|bit15-0: extra duration, bit20-16: rate/MCS, bit31: 0:enable CTStoRTS 1:disable CTStoRTS
27|FPGA packet filter config|bit13-0 passing/filter config. bit24-16 dropping config. check openwifi_configure_filter in sdr.c. also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)
28|BSSID address low 32bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_LOW_write in openwifi_bss_info_changed of sdr.c
29|BSSID address high 16bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_HIGH_write in openwifi_bss_info_changed of sdr.c
30|MAC address low 32bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c
31|MAC address high 16bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c
57|rssi_half_db read back together with channel idle and other CSMA states|Check slv_reg57 in xpu.v. Use rssi_openwifi_show.sh and rssi_ad9361_show.sh together for RSSI checking.
58|TSF runtime value low 32bit|read only
59|TSF runtime value high 32bit|read only
62|addr2 of rx packet read back|bit31-0 are from bit47-16 of addr2 field in the received packet
63|git revision when build the FPGA|returned register value means git revision in hex format
## Rx packet flow and filtering config
After FPGA receives a packet, no matter the FCS/CRC is correct or not it will raise interrupt to Linux if the frame filtering rule allows (See also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)). openwifi_rx_interrupt() function in sdr.c serves the interrupt and gives the necessary information to upper layer (Linux mac80211 subsystem) via ieee80211_rx_irqsafe.
- frame filtering
The FPGA frame filtering configuration is done by function openwifi_configure_filter() in sdr.c. The filter_flag together with **HIGH_PRIORITY_DISCARD_FLAG** finally go to pkt_filter_ctl.v of xpu module in FPGA, and control how FPGA does frame filtering. Openwifi has the capability to capture all received packets even if the CRC is wrong. You just need to set the NIC to monitor mode by iwconfig command (check monitor_ch.sh in user_space directory). In monitor mode, all received packets (including control packet, like ACK) will be given to Linux mac80211.
- main rx interrupt operations in openwifi_rx_interrupt()
- get raw content from DMA buffer. When Linux receives interrupt from FPGA rx_intf module, the content has been ready in Linux DMA buffer
- parse extra information inserted by FPGA in the DMA buffer
- TSF timer value
- raw RSSI value that will be converted to actual RSSI in dBm by different correction in different bands/channels
- packet length and MCS
- FCS is valid or not
- send packet pointer (skb) and necessary extra information to upper layer via ieee80211_rx_irqsafe()
## Tx packet flow and config
Linux mac80211 subsystem calls openwifi_tx() to initiate a packet sending.
- main operations in openwifi_tx()
- get necessary information from the packet header (struct ieee80211_hdr) for future FPGA configuration
- packet length and MCS
- unicast or broadcast? does it need ACK? how many retransmissions at most are allowed to be tried by FPGA in case ACK is not received in time?
- which driver-ring/queue (time slice) in FPGA the packet should go?
- should RTS-CTS be used? (Send RTS and wait for CTS before actually send the data packet)
- should CTS-to-self be used? (Send CTS-to-self packet before sending the data packet. You can force this on by force_use_cts_protect = true;)
- should a sequence number be inserted to the packet at the driver/chip level?
- maintain sequence number (ring->bd_wr_idx) for internal use (cross check between FPGA, openwifi_tx and openwifi_tx_interrupt)
- config FPGA register according to the above information to help FPGA do correct actions (generate PHY header, etc) according to the packet specific requirement.
- fire DMA transmission from Linux to one of FPGA tx queues. The packet may not be sent immediately if there are still some packets in FPGA tx queue (FPGA does the queue packet transmission according to channel and low MAC CSMA state)
Each time when FPGA sends a packet, an interrupt will be raised to Linux reporting the packet sending result. This interrupt handler is openwifi_tx_interrupt().
- main operations in openwifi_tx_interrupt()
- get necessary information/status of the packet just sent by FPGA
- packet length and sequence number to capture abnormal situation (cross checking between FPGA, openwifi_tx and openwifi_tx_interrupt)
- packet sending result: packet is sent successfully (FPGA receives ACK for this packet) or not. How many retransmissions have been done (in case FPGA doesn't receive ACK in time, FPGA will do retransmission according to CSMA/CA low MAC state)
- send above information to upper layer (Linux mac80211 subsystem) via ieee80211_tx_status_irqsafe()
## Understand the timestamp of WiFi packet
The TSF timestamp shown in the usual wireshark snapshot is reported by openwifi Linux driver towards Linux mac80211 framework.
This TSF timestamp is attached to the DMA of the received packet in FPGA by reading the TSF timier (defined by 802.11 standard and implemented in FPGA) value while PHY header is received: [FPGA code snip](https://github.com/open-sdr/openwifi-hw/blob/14b1e840591f470ee945844cd3bb51a95d7da09f/ip/rx_intf/src/rx_intf_pl_to_m_axis.v#L201).
Then openwifi driver report this timestamp value (together with the corresponding packet) to Linux via:
https://github.com/open-sdr/openwifi/blob/0ce2e6b86ade2f6164a373b2e98d075eb7eecd9e/driver/sdr.c#L530
To match the openwifi side channel collected data (CSI, IQ sample, etc.) to the TSF timestamp of the packet, please check: https://github.com/open-sdr/openwifi/discussions/344
## Regulation and channel config
SDR is a powerful tool for research. It is the user's responsibility to align with local spectrum regulation when doing OTA (Over The Air) test, or do the test via cable (conducted test), or in a chamber to avoid any potential interference.
This section explains how openwifi config the frequency/channel range and change it driven by Linux. The frequency overriding method is also offered by openwifi to allow the system working in any frequency in 70MHz-6GHz.
### Frequency range
When openwifi driver is loaded, openwifi_dev_probe() will be executed. Following two lines configure the frequency range:
```
dev->wiphy->regulatory_flags = xxx
wiphy_apply_custom_regulatory(dev->wiphy, &sdr_regd);
```
sdr_regd is the predefined variable in sdr.h. You can search the definition/meaning of its type: struct ieee80211_regdomain.
### Supported channel
The supported channel list is defined in openwifi_2GHz_channels and openwifi_5GHz_channels in sdr.h. If you change the number of supported channels, make sure you also change the frequency range in sdr_regd accordingly and also array size of the following two fields in the struct openwifi_priv:
```
struct ieee80211_channel channels_2GHz[14];
struct ieee80211_channel channels_5GHz[53];
```
Finally, the supported channel list is transferred to Linux mac80211 when openwifi driver is loaded by following two lines in openwifi_dev_probe():
```
dev->wiphy->bands[NL80211_BAND_2GHZ] = &(priv->band_2GHz);
dev->wiphy->bands[NL80211_BAND_5GHZ] = &(priv->band_5GHz);
```
### Real-time channel setting and restrict the channel
Linux mac80211 (struct ieee80211_ops openwifi_ops in sdr.c) uses the "config" API to configure channel frequency and some other parameters in real-time (such as during scanning or channel setting by iwconfig). It is hooked to openwifi_config() in sdr.c, and supports only frequency setting currently. The real execution of frequency setting falls to ad9361_rf_set_channel() via the "set_chan" field of struct openwifi_rf_ops ad9361_rf_ops in sdr.c. Besides tuning RF front-end (AD9361), the ad9361_rf_set_channel() also handles AD9361 calibration (if the tuning step size >= 100MHz), RSSI compensation for different frequencies and FPGA configurations (SIFS, etc) for different bands.
If you don't want openwifi node to change the channel anymore (even the Linux asks to do so), use the script user_space/set_restrict_freq.sh to limit the frequency.
```
./set_restrict_freq abcd
```
Above will limit the frequency to abcdMHz. For instance, after you setup the working system in channel 44 and you don't want the node to tune to other channel (occasionally driven by Linux scanning for example), input 5220 as argument to the script.
```
./set_restrict_freq 0
```
Above will remove the limitation. Linux driven channel tuning will be recovered.
### Let openwifi work at arbitrary frequency
Before setting a non-standard frequency to the system, a normal working system should be setup in normal/legal WiFi frequency, which should be as close as possible to the target non-standard frequency. Then use **set_restrict_freq.sh** (see above) to force upper layer to stay at that normal WiFi frequency (no scanning anymore). After this, you can set actual RF frequency to any frequency in 70MHz-6GHz (without notifying upper layer).
```
./sdrctl dev sdr0 set reg rf 1 3500
```
Above will set the Tx frequency to 3.5GHz.
```
./sdrctl dev sdr0 set reg rf 5 3500
```
Above will set the Rx frequency to 3.5GHz.
## Analog and digital frequency design
Openwifi has adopted a new RF/baseband frequency and sampling design instead of the original "offset tuning" to achieve better EVM, spectrum mask conformance, sensitivity and RSSI measurement accuracy. The AD9361 is set to FDD working mode with the same Tx and Rx frequency. Realtime AD9361 Tx chain control is done via FPGA SPI interface (openwifi-hw/ip/xpu/src/spi.v) to achieve self-interference free (when Rx) and fast Tx/Rx turn around time (0.6us). The AD9361 Tx lo (local oscillator) or RF switch is turned on before the Tx packet and turned off after the Tx packet. so that there isn't any Tx lo noise leakage during Rx period. The IQ sampling rate between AD9361 and FPGA is 40Msps. It is converted to 20Msps via decimation/interpolation inside FPGA to WiFi baseband transceiver.
Following figure shows the detailed configuration point in AD9361, driver (.c file) and related FPGA modules (.v file).
The openwifi FPGA baseband clock is driven by AD9361 clock, so there won't be any clock drifting/slight-mismatching between RF and baseband as shown in the following picture.
## Debug methods
### dmesg
To debug/see the basic driver behaviour via printk in the sdr.c, you could turn on **dmesg** message printing by
```
./sdrctl dev sdr0 set reg drv_tx 7 X
./sdrctl dev sdr0 set reg drv_rx 7 X
The bit in value X controls what type of information will be printed to the dmesg (0--no print; 1--print).
bit0: error message
bit1: regular message for unicast packet (openwifi_tx/openwifi_tx_interrupt/openwifi_rx_interrupt)
bit2: regular message for broadcast packet
bit3: regular queue stop/wake-up message due to too much traffic
For example, regular message for unicast packet and error message
./sdrctl dev sdr0 set reg drv_tx 7 3
./sdrctl dev sdr0 set reg drv_rx 7 3
For example, error message only:
./sdrctl dev sdr0 set reg drv_tx 7 1
./sdrctl dev sdr0 set reg drv_rx 7 1
```
and use **dmesg** command in Linux to see those messages. Regular printing includes tx/rx packet information when a packet is sent or received. Error printing has WARNING information if something abnormal happens. You can search "printk" in sdr.c to see all the printing points.
### tx printing example
```
sdr,sdr openwifi_tx: 70B RC0 10M FC0040 DI0000 ADDRffffffffffff/6655443322aa/ffffffffffff flag4001201e QoS00 SC20_1 retr1 ack0 prio0 q0 wr19 rd18
```
- printing from sdr driver, openwifi_tx function
- 70B: packet size (length field in SIGNAL)
- RC0: rate of the packet. enum mac80211_rate_control_flags in Linux kernel mac80211.h
- 10M: rate 1Mbps. This 802.11b rate will be converted to 6Mbps, because openwifi supports only OFDM rate.
- FC0040: Frame Control field. Example: FC0208 means type data, subtype data, to DS 0, from DS 1 (a packet from AP to client)
- DI0000: Duration/ID field
- ADDR: address fields addr1/2/3. Target MAC address ffffffffffff (broadcast), source MAC address 6655443322aa (openwifi)
- flag4001201e: flags field from Linux mac80211 struct ieee80211_tx_info (first fragment? need ACK? need sequence number insertion? etc.)
- QoS00: QoS control byte related to the packet (from Linux mac80211)
- SC20_1: sequence number 20 is set to the header of the packet. 1 means that it is set by driver (under request of Linux mac80211)
- retr1: retr1 means no retransmission is needed. retr6 means the maximum number of transmissions for this packet is 6 (set by Linux mac80211)
- ack0: ack0 means the packet doesn't need ACK; ack1 means the packet needs ACK. (set by Linux mac80211)
- prio0: priority queue 0 for this packet (0:VO voice, 1:VI video, 2:BE best effort and 3:BK background). check prio in openwifi_tx() of sdr.c (set by Linux mac80211)
- q0: the packet goes to FPGA queue 0. (You can change the mapping between Linux priority and FPGA queue in sdr.c)
- wr19 rd18: the write/read index of buffer (shared buffer between the active openwifi_tx and background openwifi_tx_interrupt/FPGA)
### tx interrupt printing example
```
sdr,sdr openwifi_tx_interrupt: tx_result [nof_retx 1 pass 1] SC20 prio0 q0 wr20 rd19 num_slot0 cw0 hwq len00000000 no_room_flag0
```
- printing from sdr driver, openwifi_tx_interrupt function
- tx_result [nof_retx 1 pass 1]: nof_retx 1 means the total number of transmission is 1. pass 1 indicates ACK is received. (0 means not)
- SC20: sequence number 20
- prio, q, wr, rd: these fields can be interpreted the same way as the print in openwifi_tx function
- num_slot: tells how many slots the CSMA/CA state machine waited until the packet is sent in the last tx attempt
- cw: the exponent of the Contention Window for this packet. 6 means the CW size 64. If the contention phase is never entered, CW is 0
- hwq len: the current FPGA queue length (number of pkt left in the queue).8bit per queue. see tx_intf register 26 in the register table section.
- no_room_flag: the DMA room of FPGA queue is almost run out. 1bit per queue. see tx_intf register 21 in the register table section.
### rx printing example
```
sdr,sdr openwifi_rx: 270B ht0aggr0/0 sgi0 240M FC0080 DI0000 ADDRffffffffffff/00c88b113f5f/00c88b113f5f SC2133 fcs1 buf_idx10 -78dBm
```
- printing from sdr driver, openwifi_rx_interrupt function
- 270B: packet size (length field in SIGNAL)
- ht0: ht0 means 11a/g (legacy); ht1 means 11n (ht)
- aggr0/0: the 1st digit means the packet is from a AMPDU packet (1) or not (0). the 2nd digit means the packet is the last packet of a AMPDU packet (1) or not (0)
- sgi0: 0 means normal GI (Guard Interval); 1 means short GI
- 240M: rate 24Mbps
- FC0080: Frame Control field. Example: FC0108 means type data, subtype data, to DS 1, from DS 0 (a packet client to openwifi AP)
- DI0000: Duration/ID field
- ADDR: address fields addr1/2/3. Target MAC address ffffffffffff (broadcast), source MAC address 00c88b113f5f
- SC2133: sequence number 2133 from the header of the packet
- fcs1: FCS/CRC is OK. (fcs0 means bad CRC)
- buf_idx10: the rx packet is from DMA buffer with index 10
- -78dBm: signal strength of this received packet (after calibration)
### Native Linux tools
For analysis/debug, many native Linux tools you still could rely on. Such as tcpdump, tshark, etc.
### Debug FPGA
For FPGA itself, FPGA developer could use Xilinx ILA tools to analyze FPGA signals (https://github.com/open-sdr/openwifi-hw/issues/39). Spying on those state machines in xpu/tx_intf/rx_intf would be very helpful for understanding/debugging Wi-Fi low level functionalities.
## Test mode driver
While loading the openwifi driver by "insmod sdr.ko", a test_mode argument can be specified (You can also specify the test_mode value to wgd.sh or fosdem.sh). It will enable some experimental feataures (such as AMPDU aggregation):
```
insmod sdr.ko test_mode=value
```
It is implemented by the global static variable test_mode in sdr.c.
Supported test_mode value definitions:
- bit0: AMPDU/aggregation is ON (1) or OFF (0 -- default OFF)
================================================
FILE: doc/app_notes/40mhz.png.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/README.md
================================================
Application notes collect many small topics about using openwifi in different scenarios/modes.
- [Use openwifi on the w-iLab.t testbed remotely](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html)
- [Communication between two SDR boards under AP and client mode](ap-client-two-sdr.md)
- [Communication between two SDR boards under ad-hoc mode](ad-hoc-two-sdr.md)
- [From CSI (Channel State Information) to CSI (Chip State Information)](csi.md)
- [WiFi CSI radar via self CSI capturing](radar-self-csi.md)
- [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md)
- [ACK timing verification by IQ capture](iq_ack_timing.md)
- [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md)
- [WiFi packet, CSI and IQ sample self loopback test (over-the-air and FPGA internal)](packet-iq-self-loopback-test.md)
- [IEEE 802.11n (Wi-Fi 4)](ieee80211n.md)
- [802.11 packet injection and fuzzing](inject_80211.md)
- [CSI fuzzer](csi_fuzzer.md)
- [Access counter/statistics in FPGA](perf_counter.md)
- [Access counter/statistics in driver](driver_stat.md)
- [Frequent/usual trick on controlling Gain/Att/Frequency/CCA/LBT/CSMA/CW/Sensitivity/etc](frequent_trick.md)
- [Driver and FPGA dynamic reloading](drv_fpga_dynamic_loading.md)
- [owfuzz: a WiFi protocol fuzzing tool using openwifi.](https://github.com/alipay/WiFi-Protocol-Fuzzing-Tool) [[**Vulnerabilities**]](https://github.com/alipay/Owfuzz#discovered-vulnerabilities)
- [Build FPGA with High-Level Synthesis modules](hls.md)
================================================
FILE: doc/app_notes/ad-hoc-two-sdr.md
================================================
**NOTE** the terminal session mentioned in the following text can also be setup via USB-UART instead of Ethernet.
**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!
- Power on two SDR boards. Call one board "adhoc1" and the other "adhoc2". On each board, the TX and RX antenna should vertical/orthogonal to each other as much as possible to gain a good TX/RX isolation.
- Connect a computer to the adhoc1 via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
ssh root@192.168.10.122
(password: openwifi)
service network-manager stop
cd openwifi
./wgd.sh
(Wait for the script completed)
ifconfig sdr0 up
./sdr-ad-hoc-up.sh sdr0 44 192.168.13.1
(Above command setup ad-hoc network at channel 44 with static IP assigned to sdr0 NIC)
iwconfig sdr0
```
- You should see output like:
```
sdr0 IEEE 802.11 ESSID:"sdr-ad-hoc"
Mode:Ad-Hoc Frequency:5.22 GHz Cell: 92:CA:14:27:1E:B0
Tx-Power=20 dBm
Retry short limit:7 RTS thr:off Fragment thr:off
Encryption key:off
Power Management:off
```
If you see "Cell: Not-Associated", please wait and run "iwconfig sdr0" again until a randomly generated Cell ID appears.
- Connect another computer to the adhoc2 via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
ssh root@192.168.10.122
(password: openwifi)
service network-manager stop
cd openwifi
./wgd.sh
ifconfig sdr0 up
./sdr-ad-hoc-up.sh sdr0 44 192.168.13.2
iwconfig sdr0
```
- You should see output like:
```
sdr0 IEEE 802.11 ESSID:"sdr-ad-hoc"
Mode:Ad-Hoc Frequency:5.22 GHz Cell: 92:CA:14:27:1E:B0
Tx-Power=20 dBm
Retry short limit:7 RTS thr:off Fragment thr:off
Encryption key:off
Power Management:off
```
The "Cell: 92:CA:14:27:1E:B0" should be the same as adhoc1, because the later joined node should discover the Cell ID of the existing network and join/get it automatically. If not, please adjust the antenna/distance and re-run the commands.
Now the communication link should be already setup between the two ad-hoc nodes, and you can ping each other.
================================================
FILE: doc/app_notes/ap-client-two-sdr.md
================================================
**NOTE** the terminal session mentioned in the following text can also be setup via USB-UART instead of Ethernet.
**NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!
- Power on two SDR boards. Call one board "AP board" and the other "client board". On each board, the TX and RX antenna should vertical/orthogonal to each other as much as possible to gain a good TX/RX isolation.
- Connect a computer to the AP board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
ssh root@192.168.10.122
(password: openwifi)
cd openwifi
./fosdem.sh
(It will create a WiFi AP by hostapd program with config file: hostapd-openwifi.conf)
(Wait for the script completed)
cat /proc/interrupts
(Execute the "cat ..." command for several times)
(You should see the number of "sdr,tx_itrpt1" grows, because it sends the "openwifi" beacon periodically)
```
- Connect another computer to the client board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
ssh root@192.168.10.122
(password: openwifi)
service network-manager stop
cd openwifi
./wgd.sh
(Wait for the script completed)
ifconfig sdr0 up
iwlist sdr0 scan
(The "openwifi" AP should be listed in the scanning results)
wpa_supplicant -i sdr0 -c wpa-openwifi.conf
("iwconfig sdr0 essid openwifi" could also work. Less info compared to wpa_supplicant)
```
If wpa-openwifi.conf is not on board, please create it with [this content](../../user_space/wpa-openwifi.conf).
- Now the client is trying to associate with the AP. You should see like:
```
root@analog:~/openwifi# wpa_supplicant -i sdr0 -c wpa-openwifi.conf
Successfully initialized wpa_supplicant
sdr0: CTRL-EVENT-SCAN-STARTED
sdr0: SME: Trying to authenticate with 66:55:44:33:22:8c (SSID='openwifi' freq=5220 MHz)
sdr0: Trying to associate with 66:55:44:33:22:8c (SSID='openwifi' freq=5220 MHz)
sdr0: Associated with 66:55:44:33:22:8c
sdr0: CTRL-EVENT-CONNECTED - Connection to 66:55:44:33:22:8c completed [id=0 id_str=]
```
The AP board terminal should print like:
```
...
sdr0: STA 66:55:44:33:22:4c IEEE 802.11: authenticated
sdr0: STA 66:55:44:33:22:4c IEEE 802.11: associated (aid 1)
sdr0: AP-STA-CONNECTED 66:55:44:33:22:4c
sdr0: STA 66:55:44:33:22:4c RADIUS: starting accounting session 613E16DE-00000000
```
If not, please adjust antenna/distance and re-run the commands on the client side.
- After association is done, in another terminal of client (**DO NOT** terminate wpa_supplicant in the original client terminal!):
```
dhclient sdr0
(Wait for it completed)
ifconfig sdr0
(Now you should see the IP address like 192.168.13.x allocated by AP)
ping 192.168.13.1
(Ping the AP)
```
Now the communication link should be already setup between the AP and the client.
================================================
FILE: doc/app_notes/csi-architecture.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/csi-information-format.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/csi-screen-shot.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/csi.md
================================================
We extend the **CSI** (Channel State Information) to **CSI** (Chip State Information)!
(This app note shows general CSI collection. To use self-Tx CSI in full duplex mode as **RADAR**, please refer to [WiFi CSI radar via self CSI capturing](radar-self-csi.md))
## Quick start
- Power on the SDR board.
- Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
ssh root@192.168.10.122
(password: openwifi)
cd openwifi
./wgd.sh
(Wait for the script completed)
./monitor_ch.sh sdr0 11
(Monitor on channel 11. You can change 11 to other channel that is busy)
insmod side_ch.ko
./side_ch_ctl g
```
You should see on board outputs like:
```
loop 64 side info count 61
loop 128 side info count 99
...
```
If the second number (61, 99, ...) is not zero and keeps increasing, that means the CSI (Chip State Information) is going to the computer smoothly.
- On your computer (NOT in ssh!), run:
```
cd openwifi/user_space/side_ch_ctl_src
python3 side_info_display.py
```
You might need to install beforehand: "sudo apt install python3-numpy python3-matplotlib python3-tk". Now you should see 3 figures showing run-time **frequency offset**, **channel state/response** and **constellation form equalizer**. Meanwhile the python script prints the **timestamp**.
While running, all information is also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do analysis on the Chip State Information offline.
## Understand the CSI feature
The CSI information is extracted via the openwifi **side channel** infrastructure. This figure explains the related modules (also related source code file name) and how the information goes from the SDR board to the computer.
The CSI information format is shown in this figure.
For each element, the actual size is 64bit.
- timestamp: 64bit TSF timer value, which is the same timestamp value shown by other sniffer software, like tcpdump, wireshark or openwifi printing in dmesg.
- freq_offset: Only the 1st 16bit is used.
- csi (channel state/response) and equalizer: Only the first two 16bit are used for I/Q of channel response and equalizer output. The remaining two 16bit are reserved for future multi-antenna cases.
The python and Matlab scripts are recommended for you to understand the CSI packet format precisely.
## Config the capture condition and interval
The quick start guide will monitor all CSI information of all packets decoded by the WiFi ofdm receiver. To monitor only specific packets that match the specific conditions: FC (Frame Control), addr1 (target MAC address), addr2 (source MAC address), configuration command should be issued before executing "**side_ch_ctl g**". The configuration command is realized by feeding a different parameter to "**side_ch_ctl**".
A quick example: Capture only CSI of those packets from the device with MAC address 56:5b:01:ec:e2:8f
```
./side_ch_ctl wh1h4001
./side_ch_ctl wh7h01ece28f
(01ece28f are the last 32 bits of MAC address 56:5b:01:ec:e2:8f)
./side_ch_ctl g
```
The parameter string format is explained in detail:
```
whXhY
```
The X is the register index, and the Y is the value in hex format. The remaining "w", "h" and "h" should be kept untouched.
- To turn on conditional capture, X should be 1. For Y: bit11~bit0 should be 001(hex), bit12: on/off of FC match, bit13: on/off of addr1 match, bit14 : on/off of addr2 match. Examples:
```
Turn on FC only match:
./side_ch_ctl wh1h1001
(1001 is the value in hex format)
Turn on addr2 (source address) only match:
./side_ch_ctl wh1h4001
Turn on both FC and addr1 (target address) match:
./side_ch_ctl wh1h3001
Turn off conditional capture (all packets will be captured):
./side_ch_ctl wh1h0001
```
- To specify the condition matching target (when that type of match is turned on by above command):
```
Specify the FC matching target:
./side_ch_ctl wh5hY
(Y is the FC value in hex format)
Specify the addr1 (target address) matching target:
./side_ch_ctl wh6hY
Specify the addr2 (source address) matching target:
./side_ch_ctl wh7hY
(Y is the MAC address in hex format. Only the last 32 bits are needed. Example: for 56:5b:01:ec:e2:8f, 01ece28f should be input.)
```
The command "**side_ch_ctl g**" will perform CSI capture every 100ms until you press ctrl+C. To use a different capture interval:
```
side_ch_ctl gN
```
The interval will become N*1ms
## Config the num_eq
The num_eq (number of equalizer output) is configurable in case you don't need so many equalizer information. The valid value is 0~8. You should align the num_eq value at the side_ch.ko, side_info_display.py and test_side_info_file_display.m.
- When insert the kernel module, use:
```
insmod side_ch.ko num_eq_init=3
```
You can replace 3 by number 0~8. (8 is the default value. You don't need to specify it like in the Quick start section)
- When launch the python script, use:
```
side_info_display.py 3
```
- When use the Matlab script, please change the num_eq variable in the script to 3 (3 is just an example).
## Compile the side channel driver and user space program
- side_ch.ko
```
$OPENWIFI_DIR/driver/side_ch/make_driver.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT
(For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
```
- side_ch_ctl (take user_space/side_ch_ctl_src/side_ch_ctl.c and compile it on board!)
```
gcc -o side_ch_ctl side_ch_ctl.c
```
## Run the CSI together with modes other than monitor
The openwifi CSI feature could run with not only monitor mode but also other modes, such as AP-Client or ad-hoc mode. After the communication functionality is fully up in those modes, you can start CSI feature from "**insmod side_ch.ko**" and "**./side_ch_ctl g**" on board as described in the previous sections to extract CSI to your computer.
## Map the CSI information to the WiFi packet
Please check this discussion: https://github.com/open-sdr/openwifi/discussions/344
If you want to relate the CSI information to the WiFi packet, you need to capture WiFi packets (tcpdump/wireshark/etc) while capturing CSI. Then you can match the timestamp (TSF timer value) between WiFi packet and CSI information, because this is the unique same identity of a Wifi packet and related CSI information.
Please learn the python and Matlab script to extract CSI information per packet according to your requirement.
================================================
FILE: doc/app_notes/csi_fuzzer.md
================================================
- [ACM WiSec 2021. Openwifi CSI fuzzer for authorized sensing and covert channels](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)
- [Privacy Protection in WiFi Sensing via CSI Fuzzing](https://ieeexplore.ieee.org/abstract/document/10818006)
CSI (Channel State Information) of WiFi systems is available in some WiFi chips and can be used for sensing the environment (keystrokes, people, object) passively and secretly.
## Concept
How could a CSI fuzzer stop unauthorized sensing?
CSI fuzzer implementation principle.
## Demo instructions
Thanks to the full-duplex capability and CSI extraction feature of openwifi, you can monitor the artificial channel response via [side channel](./csi.md) by Tx-Rx over the air coupling without affecting the normal operation/traffic of openwifi. Before fuzzing the CSI, please follow [WiFi CSI radar via self CSI capturing](radar-self-csi.md) app note to setup normal self CSI monitoring.
Then, start another ssh session to the openwifi board:
```
ssh root@192.168.10.122
(password: openwifi)
cd openwifi
./csi_fuzzer_scan.sh 1
(CSI fuzzer applies possible artificial CSI by scanning all values)
(csi_fuzzer.sh is called. Please read both scripts to understand these commands)
```
Now you should see that CSI keeps changing like in this [video](https://youtu.be/aOPYwT77Qdw).
# Further explanation on parameters
CSI fuzzer in openwifi system architecture and related commands.
# Example fuzzed CSI
CSI self-monitoring before fuzzing.
CSI self-monitoring after fuzzing command: `./csi_fuzzer.sh 1 45 0 13`
`csi_fuzzer_scan.sh` can scan the c1 and c2 in different styles/modes by calling `csi_fuzzer.sh`.
================================================
FILE: doc/app_notes/driver_stat.md
================================================
Comprehensive statistics are offered at the driver level via the [Linux sysfs](https://en.wikipedia.org/wiki/Sysfs#:~:text=sysfs%20is%20a%20pseudo%20file,user%20space%20through%20virtual%20files.).
[[Quick start](#Quick-start)]
[[Sysfs explanation](#Sysfs-explanation)]
[[Statistics variable file meaning](#Statistics-variable-file-meaning)]
All operations should be done on board in openwifi directory, not in host PC.
## Quick start
Enable the driver level statistics (after openwifi up and running)
```
./stat_enable.sh
```
Show the statistics
```
./tx_stat_show.sh
./tx_prio_queue_show.sh
./rx_stat_show.sh
./rx_gain_show.sh
```
Clear the stattistics
```
./tx_stat_show.sh clear
./tx_prio_queue_show.sh clear
./rx_stat_show.sh clear
```
Let rx_stat_show.sh calculate PER (Packet Error Rate) by giving the number of packet sent at the peer (30000 packets for example):
```
./rx_stat_show.sh 30000
```
To only show the statistics for the link with a specific peer node
```
./set_rx_target_sender_mac_addr.sh c83caf93
(If the peer node MAC address is 00:80:c8:3c:af:93)
```
To show the statistics of all (not filtered by the peer node MAC address)
```
./set_rx_target_sender_mac_addr.sh 0
```
To show the peer node MAC address for statistics
```
./set_rx_target_sender_mac_addr.sh
```
To see the statistics of ACK packet, run this before above scripts
```
./set_rx_monitor_all.sh
```
Disable the statistics of ACK packet, run this before above scripts
```
./set_rx_monitor_all.sh 0
```
Disable the driver level statistics (after openwifi up and running)
```
./stat_enable.sh 0
```
## Sysfs explanation
For user, as you can check in those scripts above, the sysfs is a set of files that can be operated in the command line for communicating with kernel module. You can find these files on zcu102 board at
```
/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr
```
On othe boards at
```
/sys/devices/soc0/fpga-axi@0/fpga-axi@0:sdr
```
## Statistics variable file meaning
These statistics names are the same as the file names (in those scripts) and variable names in the sdr.c. Do search these names in sdr.c to understand exact meaning of these statistics.
- tx_stat_show.sh
name|meaning
------------|----------------------
tx_data_pkt_need_ack_num_total | number of tx data packet reported in openwifi_tx_interrupt() (both fail and succeed)
tx_data_pkt_need_ack_num_total_fail| number of tx data packet reported in openwifi_tx_interrupt() (fail -- no ACK received)
tx_data_pkt_need_ack_num_retx | number of tx data packet reported in openwifi_tx_interrupt() at different number of retransmission (both fail and succeed)
tx_data_pkt_need_ack_num_retx_fail | number of tx data packet reported in openwifi_tx_interrupt() at different number of retransmission (fail -- no ACK received)
tx_data_pkt_mcs_realtime | MCS (10*Mbps) of tx data packet reported in openwifi_tx_interrupt() (both fail and succeed)
tx_data_pkt_fail_mcs_realtime | MCS (10*Mbps) of tx data packet reported in openwifi_tx_interrupt() (fail -- no ACK received)
tx_mgmt_pkt_need_ack_num_total | number of tx management packet reported in openwifi_tx_interrupt() (both fail and succeed)
tx_mgmt_pkt_need_ack_num_total_fail| number of tx management packet reported in openwifi_tx_interrupt() (fail -- no ACK received)
tx_mgmt_pkt_need_ack_num_retx | number of tx management packet reported in openwifi_tx_interrupt() at different number of retransmission (both fail and succeed)
tx_mgmt_pkt_need_ack_num_retx_fail | number of tx management packet reported in openwifi_tx_interrupt() at different number of retransmission (fail -- no ACK received)
tx_mgmt_pkt_mcs_realtime | MCS (10*Mbps) of tx management packet reported in openwifi_tx_interrupt() (both fail and succeed)
tx_mgmt_pkt_fail_mcs_realtime | MCS (10*Mbps) of tx management packet reported in openwifi_tx_interrupt() (fail -- no ACK received)
- tx_prio_queue_show.sh
tx_prio_queue_show.sh will show 4 rows. Each row is corresponding one Linux-prio and one FPGA queue. Each row has 12 elements. Elements' name will not be displayed in the command line.
Element name|meaning
------------|----------------------
tx_prio_num | number of tx packet from Linux prio N to openwifi_tx()
tx_prio_interrupt_num | number of tx packet from Linux prio N recorded in openwifi_tx_interrupt()
tx_prio_stop0_fake_num | number of Linux prio N stopped attempt in the 1st place of openwfii_tx(), fake alarm
tx_prio_stop0_real_num | number of Linux prio N stopped attempt in the 1st place of openwfii_tx(), real stop
tx_prio_stop1_num | number of Linux prio N stopped in the 2nd place of openwfii_tx()
tx_prio_wakeup_num | number of Linux prio N waked up in openwifi_tx_interrupt()
tx_queue_num | number of tx packet for FPGA queue N to openwifi_tx()
tx_queue_interrupt_num | number of tx packet for FPGA queue N recorded in openwifi_tx_interrupt()
tx_queue_stop0_fake_num| number of FPGA queue N stopped attempt in the 1st place of openwfii_tx(), fake alarm
tx_queue_stop0_real_num| number of FPGA queue N stopped attempt in the 1st place of openwfii_tx(), real stop
tx_queue_stop1_num | number of FPGA queue N stopped in the 2nd place of openwfii_tx()
tx_queue_wakeup_num | number of FPGA queue N waked up in openwifi_tx_interrupt()
- rx_stat_show.sh
name|meaning
------------|----------------------
rx_data_pkt_num_total | number of rx data packet with both FCS ok and failed
rx_data_pkt_num_fail | number of rx data packet with FCS failed
rx_mgmt_pkt_num_total | number of rx management packet with both FCS ok and failed
rx_mgmt_pkt_num_fail | number of rx management packet with FCS failed
rx_ack_pkt_num_total | number of rx ACK packet with both FCS ok and failed
rx_ack_pkt_num_fail | number of rx ACK packet with FCS failed
rx_data_pkt_mcs_realtime | MCS (10*Mbps) of rx data packet with both FCS ok and failed
rx_data_pkt_fail_mcs_realtime | MCS (10*Mbps) of rx data packet with FCS failed
rx_mgmt_pkt_mcs_realtime | MCS (10*Mbps) of rx management packet with both FCS ok and failed
rx_mgmt_pkt_fail_mcs_realtime | MCS (10*Mbps) of rx management packet with FCS failed
rx_ack_pkt_mcs_realtime | MCS (10*Mbps) of rx ACK packet with both FCS ok and failed
rx_data_ok_agc_gain_value_realtime | agc gain value of rx data packet with FCS ok
rx_data_fail_agc_gain_value_realtime| agc gain value of rx data packet with FCS failed
rx_mgmt_ok_agc_gain_value_realtime | agc gain value of rx management packet with FCS ok
rx_mgmt_fail_agc_gain_value_realtime| agc gain value of rx management packet with FCS failed
rx_ack_ok_agc_gain_value_realtime | agc gain value of rx ACK packet with FCS ok
- rx_gain_show.sh
name|meaning
------------|----------------------
rx_data_ok_agc_gain_value_realtime | agc gain value of rx data packet with FCS ok
rx_data_fail_agc_gain_value_realtime| agc gain value of rx data packet with FCS failed
rx_mgmt_ok_agc_gain_value_realtime | agc gain value of rx management packet with FCS ok
rx_mgmt_fail_agc_gain_value_realtime| agc gain value of rx management packet with FCS failed
rx_ack_ok_agc_gain_value_realtime | agc gain value of rx ACK packet with FCS ok
Note: gain value here is always 14 dB higher than set_rx_gain_auto.sh/set_rx_gain_manual.sh at 5220MHz. 5dB higher at 2.4GHz.
================================================
FILE: doc/app_notes/drv_fpga_dynamic_loading.md
================================================
The **wgd.sh** (running on board) supports reloading driver and/or FPGA image dynamically without rebooting/power-cycle. It can work in a
flexible way.
The purpose of this feature is to help you easily reload driver and FPGA built from your branch/version/variant/modification, and switch/run different driver and FPGA of different branch/version/variant/modification without rebooting. To enjoy this feature, always ensure your onboard openwifi/files are the latest files in [user_space](../../user_space)).
- [[Reload driver only](#Reload-driver-only)]
- [[Reload driver and FPGA](#Reload-driver-and-FPGA)]
- [[Reload driver and FPGA in target directory](#Reload-driver-and-FPGA-in-target-directory)]
- [[Reload driver and FPGA from a single package file](#Reload-driver-and-FPGA-from-a-single-package-file)] -- **RECOMMENDED!**
- [[Suggested practice to generate driver FPGA variants](#Suggested-practice-to-generate-driver-FPGA-variants)]
- [[Detailed full usage info](#Detailed-full-usage-info)]
Note: Make sure you have compiled driver before. Check [Update Driver](../../README.md#update-driver).
## Reload driver only
This is the original way. To let **wgd.sh** only loads the driver without touching FPGA, please ensure FPGA image file **system_top.bit.bin** is **NOT**
present in the directory. If wgd.sh can not find the FPGA image, it will skip reloading it.
## Reload driver and FPGA
- Generate the reloadable FPGA file **system_top.bit.bin**. In the Linux host computer:
```
cd openwifi/user_space
./drv_and_fpga_package_gen.sh $OPENWIFI_HW_IMG_DIR $XILINX_DIR $BOARD_NAME
```
Then **system_top.bit.bin** will be generated in openwifi/user_space.
- Put **system_top.bit.bin** on board in the same directory as wgd.sh and other driver files (.ko)
- Run **wgd.sh** on board as usual
## Reload driver and FPGA in target directory
Put **system_top.bit.bin** on board together with other driver files (.ko) in a directory ($TARGET_DIR), then run on board:
```
./wgd.sh $TARGET_DIR
```
In this way, different versions/variants of driver/FPGA can be put in different directories. Then **wgd.sh** can be used to switch
between them without rebooting/power-cycle.
## Reload driver and FPGA from a single package file
The openwifi/user_space/**drv_and_fpga_package_gen.sh** also generates a single package file **drv_and_fpga.tar.gz**, which includes driver files (.ko),
FPGA image and many other source files with rich infos that are related.
You can switch to your own branch/version/variant, build the single package file via **drv_and_fpga_package_gen.sh**, rename it with a more meaningful name (such as add version or variant info as postfix), put the renamed **drv_and_fpga_MEANINGFUL_POSTFIX.tar.gz** on board in the same directory as **wgd.sh**, and let **wgd.sh** load it:
```
./wgd.sh ./drv_and_fpga_MEANINGFUL_POSTFIX.tar.gz
```
In this way, different version/variants of driver/FPGA can be switched by **wgd.sh** without rebooting/power-cycle.
## Suggested practice to generate driver FPGA variants
There are several ways to generate variants of the single driver-FPGA package file. For example:
- Switch/create another branch for openwifi and openwifi-hw, work/modify there, then generate the single package file via **drv_and_fpga_package_gen.sh**. This package is the branch specific, so renaming the package name to a more meaningful one would be good practice.
- In the same branch, set different arguments (finally macro definitions in .h and .v files) via conditional compiling to enable/disable different driver and FPGA code blocks/functionalities, then generate the single package file via **drv_and_fpga_package_gen.sh**. Rename the package to remind you which conditions are ON/OFF.
- Check "Conditional compile by verilog macro" in openwifi-hw README for FPGA design
- Input more arguments (max 5) to driver building script "make_all.sh $XILINX_DIR ARCH_BIT". Those arguments will be converted to "#define argument" in pre_def.h for driver conditional compiling. **Attention:** **drv_and_fpga_package_gen.sh** currently only call **make_all.sh** without extra arguments. If you have conditional compiling arguments, do not forget to put them into **drv_and_fpga_package_gen.sh** as extra arguments of **make_all.sh**.
## Detailed full usage info
Run the "./wgd.sh -h" on board or open wgd.sh to see full usage info:
```
usage:
Script for load (or download+load) different driver and FPGA img without rebooting
no argument: Load .ko driver files and FPGA img (if system_top.bit.bin exist) in current dir with test_mode=0.
1st argument: If it is a NUMBER, it will be assigned to test_mode. Then load everything from current dir.
1st argument: If it is a string called "remote", it will download driver/FPGA and load everything.
- 2nd argument (if exist) is the target directory name for downloading and reloading
- 3rd argument (if exist) is the value for test_mode
1st argument: neither NUMBER nor "remote" nor a .tar.gz file, it is regarded as a directory and load everything from it.
- 2nd argument (if exist) is the value for test_mode
1st argument: a .tar.gz file, it will be unpacked then load from that unpacked directory
- 2nd argument (if exist) is the value for test_mode
```
================================================
FILE: doc/app_notes/frequent_trick.md
================================================
Some usual/frequent control trick over the openwifi FPGA. You need to do these controls on board in the openwifi directory.
[[CCA LBT threshold and disable](#CCA-LBT-threshold-and-disable)]
[[Retransmission and ACK control](#Retransmission-and-ACK-control)]
[[NAV DIFS EIFS CW disable and enable](#NAV-DIFS-EIFS-CW-disable-and-enable)]
[[CW max and min config](#CW-max-and-min-config)]
[[Rx gain config](#Rx-gain-config)]
[[Tx power config](#Tx-power-config)]
[[Tx Lo and port config](#Tx-Lo-and-port-config)]
[[Antenna selection](#Antenna-selection)]
[[Restrict the frequency](#Restrict-the-frequency)]
[[Receiver sensitivity control](#Receiver-sensitivity-control)]
[[Tx rate config](#Tx-rate-config)]
[[Arbitrary Tx IQ sample](#Arbitrary-Tx-IQ-sample)]
## CCA LBT threshold and disable
In normal operation, different threshold is set to FPGA according to the different calibration of different frequency/channel by driver automatically. Show the current LBT threshold in FPGA:
```
./set_lbt_th.sh
dmesg
```
It shows: "sdr,sdr FPGA LBT threshold 166(-62dBm). The last_auto_fpga_lbt_th 166(-62dBm). rssi corr 145". Check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm.
Override a new threshold -NNdBm to FPGA, for example -70dBm:
```
./set_lbt_th.sh 70
dmesg
```
Above will disable the automatic CCA threshold setting from the openwifi driver.
Recover the driver automatic control on the threshold:
```
./set_lbt_th.sh 0
dmesg
```
Disable the CCA by setting a very strong level as threshold, for example -1dBm:
```
./set_lbt_th.sh 1
dmesg
```
After above command, the CCA engine will always believe the channel is idle, because the rx signal strength not likely could exceed -1dBm.
## Retransmission and ACK control
The best way of override the maximum number of re-transmission for a Tx packet is doing it in the driver openwifi_tx() function.
```
retry_limit_hw_value = ( retry_limit_raw==0?0:((retry_limit_raw - 1)&0xF) );
```
Override retry_limit_hw_value to 0 to disable re-transmission. Override it to 1 means that let FPGA do maximum 1 time re-transmission.
The FPGA also has a register to override the re-transmission and ACK behavior. Check the current register value.
```
./sdrctl dev sdr0 get reg xpu 11
```
When operate this register, make sure you only change the relevant bits and leave other bits untouched, because other bits have other purposes. Also check the xpu register 11 in the [project document](../README.md)
To override the maximum number of re-transmission, set bit3 to 1, and set the value (0 ~ 7) to bit2 ~ 0. Example, override the maximum number of re-transmission to 1
```
./sdrctl dev sdr0 set reg xpu 11 9
```
9 in binary form is 01001.
To disable the ACK TX after receiving a packet, set bit4 to 1:
```
./sdrctl dev sdr0 set reg xpu 11 16
```
If we want to preserve the above re-transmission overriding setting while disable ACK Tx:
```
./sdrctl dev sdr0 set reg xpu 11 25
```
25 in binary form is 11001. the 1001 of bit3 to 1 is untouched.
Disabling ACK TX might be useful for monitor mode and packet injection.
To disable the ACK RX after sending a packet, set bit5 to 1:
```
./sdrctl dev sdr0 set reg xpu 11 32
```
To disable both ACK Tx and Rx:
```
./sdrctl dev sdr0 set reg xpu 11 48
```
## NAV DIFS EIFS CW disable and enable
To check the current NAV/DIFS/EIFS/CW disable status, just run
```
./nav_disable.sh
./difs_disable.sh
./eifs_disable.sh
./cw_disable.sh
```
If NAV is disabled, the openwifi will always assume the NAV (Network Allocation Vector) is already counting down to 0. If DIFS/EIFS is disabled, when the CSMA engine needs to wait for DIFS/EIFS, it won't wait anymore. If CW is disabled, the contention window is fixed to 0, and there won't be any number of slots for random backoff procedure. To disable them, just input 1 as the script argument.
```
./nav_disable.sh 1
./difs_disable.sh 1
./eifs_disable.sh 1
./cw_disable.sh 1
```
To enable them, just input 0 as the script argument.
```
./nav_disable.sh 0
./difs_disable.sh 0
./eifs_disable.sh 0
./cw_disable.sh 0
```
## CW max and min config
When the openwifi NIC bring up (as AP/Client/ad-hoc/etc), Linux will configure the CW (Contention Window) max and min value for FPGA queue 3 ~ 0 via openwifi_conf_tx() in the openwifi driver. You can check the current CW configuration in FPGA (set by Linux).
```
./cw_max_min_cfg.sh
```
It will show sth like
```
FPGA cw max min for q3 to q0: 1023 15; 63 15; 15 7; 7 3
FPGA cw max min for q3 to q0: a4644332
```
The CW max and min for q3 ~ 0 are a4, 64, 43, 32 (in hex). Example explanation for q3: in hex the configuration is a4, which means 10 and 4 in the logarithmic domain, (2^10)-1=1023 and (2^4)-1=15 in the linear domain.
To override the CW max and min for queue 3 ~ 0, for example 2047 31; 63 31; 15 7; 7 3, just map it to a hex string b5654332 for queue 3 ~ 0 and give it as the script argument:
```
./cw_max_min_cfg.sh b5654332
```
It will show sth like
```
FPGA cw max min for q3 to q0: 2047 31; 63 31; 15 7; 7 3
FPGA cw max min for q3 to q0: b5654332
SYSFS cw max min for q3 to q0: 2047 31; 63 31; 15 7; 7 3
SYSFS cw max min for q3 to q0: b5654332
```
To give the control back to Linux
```
./cw_max_min_cfg.sh 0
```
Be careful that above command won't bring the Linux CW max min setting back to FPGA automatically, because Linux normally only call the setting function openwifi_conf_tx() for 1 time when the NIC is started. So either you write down the Linux setting by checking it at the beginning, and set it back via cw_max_min_cfg.sh before giving it argument 0, or re-load the NIC/driver to trigger the Linux setting action for the NIC.
## Rx gain config
In normal operation, you don't need to do Rx gain control manually, because it is controled by the AD9361 AGC function. For optimization/experiment purpose, you might want to use the manual rx gain control, you can run
```
./set_rx_gain_manual.sh 30
```
Above command will turn the automatic gain control mode to manual gain control mode, and set 30dB to the Rx gain module.
Bring it back to the automatic gain control mode
```
./set_rx_gain_auto.sh
```
To find out a good reference about a manual Rx gain setting for the current link/peer, you can set it to automatic mode and then run
```
./stat_enable.sh
```
once and then
```
./rx_gain_show.sh
```
for multiple times to check the actual AGC gain vlaue for received packet as explained in this [Access counter/statistics in driver](driver_stat.md). Then you can set the AGC gain value as argument to the **set_rx_gain_manual.sh** with the corret **offset**! For example, if **rx_gain_show.sh** reports a AGC gain value 34 for many successfully received data packets, and you want to use it as a manual gain setting, you need to set
```
./set_rx_gain_manual.sh 20
```
if the current working channel is 5220MHz (34 - 14dB offset = 20). You need to set
```
./set_rx_gain_manual.sh 29
```
if the current working channel is in 2.4GHz (34 - 5dB offset = 29).
## Tx power config
```
./sdrctl dev sdr0 set reg rf 0 20000
```
Above command will set Tx power attenuation to 20dB (20*1000). By default it is 0dB.
If you want an initial attenuation 20dB while loading and bringing up the openwifi NIC, please use the **init_tx_att** argument for the sdr.ko.
```
insmod sdr.ko init_tx_att=20000
```
You can change above driver loading action at the end of **wgd.sh**.
The initial Tx attenuation might be useful when you connect two SDR boards directly by cable. Even though, you shouldn't not connect them during the setup phase (bring up the AP or client), because the initialization/tuning of AD9361 might generate big Tx power and kill the other AD9361's Rx. Only connect two SDR boards by cable after both sides have been setup and the attenuation setting takes effect.
To increase the Tx power, you can consider add external PA like [this](https://github.com/open-sdr/openwifi/issues/53#issuecomment-767621478). Or increase the value of register 13 of tx_intf (check [README](../README.md)).
Read the register value:
```
./sdrctl dev sdr0 get reg tx_intf 13
```
Set the register value to N (a number larger than the value read back above):
```
./sdrctl dev sdr0 set reg tx_intf 13 N
```
Bigger value in that register could hurt the Tx EVM and long packet signal. You need to fine tune it for your case.
## Tx Lo and port config
In normal operation, the Tx Lo and RF port are controled by FPGA automatically during signal Tx. To check the current Tx Lo and RF port switch status
```
./set_tx_port.sh
./set_tx_lo.sh
```
Give argument **1** to above scripts to turn them **ON**, **0** for **OFF**.
To turn off automatic Tx Lo control from FPGA and leave Tx Lo always ON:
```
./sdrctl dev sdr0 set reg xpu 13 1
```
## Antenna selection
By default, the 1st Tx and Rx antennas are used (tx0 and rx0). You can change the tx antenna to tx1 by
```
./sdrctl dev sdr0 set reg drv_tx 4 1
```
Change the tx antenna back to tx0 by
```
./sdrctl dev sdr0 set reg drv_tx 4 0
```
Change the rx antenna to rx1 and rx0 by
```
./sdrctl dev sdr0 set reg drv_rx 4 1
./sdrctl dev sdr0 set reg drv_rx 4 0
```
## Restrict the frequency
Since the AD9361 frequency tuning could generate big unwanted Tx noise, and it could damage the other AD9361 Rx during the test via cable, a restricted frequency can be set to avoid the possible frequency tuning (such as the background scan of Wifi). For example, you want the AD9361 works only in 5220Mhz:
```
./set_restrict_freq.sh 5220
```
Above command will fix the AD9361 in 5220MHz and let driver ignore frequency tuning request other than 5220MHz. The restriction can be removed by:
```
./set_restrict_freq.sh 0
```
To let openwifi work at arbitrary frequency, please check [Let openwifi work at arbitrary frequency](../README.md#let-openwifi-work-at-arbitrary-frequency)
## Receiver sensitivity control
Sometimes too good sensitivity could be a bad thing. WiFi receiver could be "attracted" by many weak signal/packet in the background, and has less "attention" to its real communication target (client/AP). Openwifi has offered a way to make the receiver less sensitive by setting a threshold. When the received signal is lower than this threshold, the receiver will not try to search the WiFi short preamble, i.e. ignore it. For example, if you want to set -70dBm as the threshold, use:
```
./sdrctl dev sdr0 set reg drv_rx 0 70
```
## Tx rate config
By default, the Linux rate adaptation algorithm **minstrel_ht** set the packet rate/MCS automatically via openwifi_tx() function.
```
rate_hw_value = ieee80211_get_tx_rate(dev, info)->hw_value;
```
To override the Linux automatic control for non-ht packet
```
./sdrctl dev sdr0 set reg drv_tx 0 N
```
Value N: 0 for Linux auto control; 4 ~ 11 for 6M, 9M, 12M, 18M, 24M, 36M, 48M, 54M.
To override the Linux automatic control for ht packet
```
./sdrctl dev sdr0 set reg drv_tx 1 N
```
Value N: 0 for Linux auto control; 4 ~ 11 for 6.5M, 13M, 19.5M, 26M, 39M, 52M, 58.5M, 65M. By default, the normal GI is used. To use the short GI, you need to add 16 to the target value N.
## Arbitrary Tx IQ sample
Arbitrary IQ sample can be written to tx_intf and sent for test purposes. Currently maximum 512 samples, which is decided by the FIFO size in tx_iq_intf.v.
To verify this feature, firstly bring up the sdr0 NIC and put it into non-Tx mode, such as monitor mode. Then setup IQ capture in loopback mode, for example FPGA internal. (Check IQ capture App note for more details)
```
insmod side_ch.ko iq_len_init=8187
# Make sure to set the Tx local oscillator always on (as XPU is not aware of the transmission)
./sdrctl dev sdr0 set reg xpu 13 1
# Set 100 to register 11. It means the pre trigger length is 100, so we mainly capture IQ after trigger condition is met
./side_ch_ctl wh11d100
# Set 3 to register 8 -- set trigger condition to tx_intf_iq0_non_zero in tx_intf
./side_ch_ctl wh8d3
# Set the loopback mode to FPGA internal
./side_ch_ctl wh5h4
./side_ch_ctl g0
```
Run `python3 iq_capture.py 8187` on the host PC to wait for IQ capture by FPGA. After FPGA hits the IQ capture trigger condition, this host PC Python script will display and save the captured IQ.
Open another ssh session to the board. Make sure you have an arbitrary_iq_gen directory, tx_intf_iq_data_to_sysfs.sh and tx_intf_iq_send.sh (from user_space directory in the host PC) on board. Then run:
```
# Send the example IQ data to driver sysfs, and read back for check
./tx_intf_iq_data_to_sysfs.sh
# Write the IQ data from driver to FPGA, and send once
./tx_intf_iq_send.sh
```
Above scripts will send one time IQ. So you should see the captured IQ plot pop up. You can further check/process iq.txt in Matlab by `test_iq_file_display.m`.
The related tx_intf registers and tx_iq_intf ports
tx_intf register|tx_iq_intf port|explanation
----------------|---------------|-----------
slv_reg7 bit0 |tx_arbitrary_iq_mode| 0:Normal operation; 1:Arbitrary IQ mode
slv_reg7 bit1 |tx_arbitrary_iq_tx_trigger| jumping from 0 to 1 will trigger one time Tx of IQ in the tx_iq_intf FIFO
slv_reg1 bit31~0|tx_arbitrary_iq_in|The driver writes IQ (32bit=I+Q) via this port one by one into the FIFO
The script `tx_intf_iq_send.sh` will trigger driver operations via `tx_intf_iq_ctl_store` function in `sysfs_intf.c`:
- Switch to arbitrary IQ mode via slv_reg7 bit0
- Write IQ data one by one to the tx_intf FIFO via slv_reg1
- Trigger one time Tx of IQ data via slv_reg7 bit1
================================================
FILE: doc/app_notes/guard-interval.png.license
================================================
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/hls.md
================================================
FCCM2023 Poster: [Thijs Havinga, et al. Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thijs-FCCM2023-poster.jpg)
[Longer/detailed info about the poster](https://arxiv.org/abs/2305.13351)
In order to speed up or ease FPGA development, it is possible to use High-Level Synthesis (HLS) for creating core baseband processing modules of openwifi. We have already programmed the receiver modules channel estimation and equalization in C++ and converted to Verilog using Vitis HLS. In order to use openwifi with these HLS modules, follow the [build instructions](#build-instructions).
In order to modify these modules within Vitis HLS, follow [the instructions below](#modify-the-code-using-vitis-hls).
## Build instructions
Follow the [Build FPGA](https://github.com/open-sdr/openwifi-hw#build-fpga) instructions till before generating ip_repo. In order to switch to the HLS-version of openofdm_rx, use the following commands:
```
cd ip/openofdm_rx
git checkout dot11zynq_hls
```
Now continue with the instructions. Before generating the bitstream, update the openofdm_rx IP by making sure it is selected under "IP Status" and click "Upgrade Selected". Afterwards, continue with the instructions to generate the bitstream.
## Modify the code using Vitis HLS
When in the `openwifi-hw` folder, make sure to run:
```
./get_ip_openofdm_rx.sh
cd ip/openofdm_rx
git checkout dot11zynq_hls
```
Then start Vitis HLS and create a new project. Import either all source files (except those ending on '_test.cpp') in the [ch_gain_cal](https://github.com/open-sdr/openofdm/tree/dot11zynq_hls/hls/ch_gain_cal) or [equalizer](https://github.com/open-sdr/openofdm/tree/dot11zynq_hls/hls/equalizer) folder to modify the channel estimation or equalizer module, respectively. Choose either 'equalizer' or 'ch_gain_cal' as top-level module. Next, select `equalizer_test.cpp` or `ch_gain_cal_test.cpp` as testbench file. In 'Part selection', select the right part corresponding to your board.
After modifying the code and making sure C simulation and cosimulation is running fine, select 'Export RTL', which will generate a ZIP file with a folder `hdl/verilog` containing the generated Verilog files. Replace the current folder `openwifi-hw/ip/openofdm_rx/hls/equalizer/hdl/verilog/` (or `.../ch_gain_cal/hdl/verilog`) with this folder and change the `openofdm_rx.tcl` file to include the newly generated Verilog files. See [here](https://github.com/open-sdr/openofdm/blob/dot11zynq_hls/openofdm_rx.tcl#L268) for an example. If you modified the top-level function arguments, you will need to interface them accordingly in [dot11.v](https://github.com/open-sdr/openofdm/blob/dot11zynq_hls/verilog/dot11.v).
Now follow the [Build FPGA](https://github.com/open-sdr/openwifi-hw#build-fpga) instructions, starting at the step "Generate ip_repo for the top level FPGA project". It will then use the modified .tcl file to include the correct files for your modified HLS module and build the FPGA using it.
A similar approach can be followed to create other HLS modules, where you would need to execute these steps in the folder of the IP to be modified and integrate the modules in the corresponding top-level Verilog file.
================================================
FILE: doc/app_notes/ieee80211n.md
================================================
## IEEE 802.11n (Wi-Fi 4)
The 4th generation of Wi-Fi (i.e. 802.11n-2009) is a generation leap over its predecessor Wi-Fi 3 (i.e. 802.11g-2003). It was coined as high throughput (HT) since it improves both the physical layer and the MAC layer.
### PHY layer improvements
At the physical layer, 5 major improvements were amended on top of Wi-Fi 3 and this has increased the throughput from 54Mbps to 600Mbps.
#### More subcarriers
Wi-Fi 3 utilizes 48 OFDM data subcarriers and Wi-Fi 4 increased this number to 52, thereby increasing the throughput to 52/48 * 54Mbps = 58.5Mbps.
#### Forward error correction
The most efficient coding rate used in Wi-Fi 3 was 3/4 but Wi-Fi increased this value to 5/6 by squeezing more bits. This has increased the throughput to (5/6)/(3/4) * 58.5Mbps = 65Mbps.
#### Guard interval
As a measure to combat inter-symbol interference (ISA), Wi-Fi 3 utilizes 800nsec of guard interval between consecutive OFDM symbols. Wi-Fi 4 shortens this value to 400nsec, and this has increased the throughput to 4usec/3.6usec * 65Mbps = 72.2Mbps.
#### MIMO
Wi-Fi 4 was the first to introduce MIMO and standardized 4x4 spatial streams. This has quadrupled the throughput to 4*72.2Mbps = 288.9Mbps.
#### 40MHz bandwidth
The last thing Wi-Fi 4 introduced to the physical layer is a 40MHz bandwidth utilizing 108 OFDM data subcarriers. This has increased the throughput to 108/52 * 288.8Mbps = 600 Mbps.
### MAC layer improvements
On top of the PHY layer improvements, Wi-Fi 4 also introduced frame aggregation at the MAC layer to ease the medium access contention. Two types of frame aggregation are used in Wi-Fi 4; A-MPDU and A-MSDU. While A-MSDU is efficient in medium occupation, a single packet error will make the whole frame unusable and require complete retransmission. However, A-MPDU aggregates multiple MPDUs by adding headers to each packet and a single packet error only requires single packet retransmission. As such, A-MPDU gained traction.
## Supported openwifi 802.11n amendments
- 52 subcarriers
- 5/6 code rates
- 400nsec short guard interval.
Current theoretical throughput = 72.2Mbps.
## To be supported openwifi 802.11n amendments
- Frame aggregation
## Not supported openwifi 802.11n amendments
- MIMO
- 40MHz bandwidth
================================================
FILE: doc/app_notes/inject_80211.md
================================================
## 802.11 packet injection and fuzzing
The Linux wireless networking stack (i.e. driver, mac80211, cfg80211, net_dev, user app) is a robust implementation supporting a plethora of wireless devices. As robust as it is, it also has a drawback when it comes to single-layer testing and manual/total control mode (fuzzing).
Ping and Iperf are well established performance measurement tools. However, using such tools to measure 802.11 PHY performance can be misleading, simply because they touch multiple layers in the network stack.
Luckily, the mac80211 Linux subsystem provides packet injection functionality when the NIC is in the monitor mode and it allows us to have finer control for physical layer testing and/or fuzzing.
Besides the traditional fuzzing tool (like scapy), we have adapted a [packetspammer](https://github.com/gnychis/packetspammer) application, which is originally written by Andy Green and maintained by George Nychis , to show how to inject packets and control the FPGA behavior.
### Build inject_80211 on board
Userspace program to inject 802.11 packets through mac80211 supported (softmac) wireless devices.
Login/ssh to the board and setup internet connection according to the Quick Start. Then
```
cd openwifi/inject_80211
make
```
### Customize the packet content
To customize the packet, following piece of the inject_80211.c needs to be changed:
```
/* IEEE80211 header */
static u8 ieee_hdr_data[] =
{
0x08, 0x02, 0x00, 0x00,
0x66, 0x55, 0x44, 0x33, 0x22, 0x11,
0x66, 0x55, 0x44, 0x33, 0x22, 0x22,
0x66, 0x55, 0x44, 0x33, 0x22, 0x33,
0x10, 0x86,
};
static u8 ieee_hdr_mgmt[] =
{
0x00, 0x00, 0x00, 0x00,
0x66, 0x55, 0x44, 0x33, 0x22, 0x11,
0x66, 0x55, 0x44, 0x33, 0x22, 0x22,
0x66, 0x55, 0x44, 0x33, 0x22, 0x33,
0x10, 0x86,
};
static u8 ieee_hdr_ack_cts[] =
{
0xd4, 0x00, 0x00, 0x00,
0x66, 0x55, 0x44, 0x33, 0x22, 0x11,
};
static u8 ieee_hdr_rts[] =
{
0xb4, 0x00, 0x00, 0x00,
0x66, 0x55, 0x44, 0x33, 0x22, 0x11,
0x66, 0x55, 0x44, 0x33, 0x22, 0x22,
};
```
Note: The byte/bit order might not be intuitive when comparing with the standard.
### FPGA behavior control
- ACK and retransmission after FPGA sends packet
In openwifi_tx of sdr.c, many FPGA behaviors can be controled. Generally they are controled by the information from upper layer (Linux mac80211), but you can override them in driver (sdr.c)
If 802.11 ACK is expected from the peer after the packet is sent by FPGA, variable **pkt_need_ack** should be overridden to 1. In this case, the FPGA will try to receive ACK, and report the sending status (ACK is received or not) to upper layer (Linux mac80211)
The maximum times of transmission for the packet can be controled by variable **retry_limit_raw**. If no ACK is received after the packet is sent, FPGA will try retransmissions automatically if retry_limit_raw>1.
- ACK after FPGA receives packet in monitor mode
Even in monitor mode, openwifi FPGA still sends ACK after the packet is received, if the conditions are met: MAC address is matched, it is a data frame, etc. To disable this automatic ACK generation, the register 11 of xpu should be set to 16:
```
sdrctl dev sdr0 set reg xpu 11 16
```
### Options of program inject_80211
```
-m/--hw_mode (a,g,n)
-r/--rate_index (0,1,2,3,4,5,6,7)
-t/--packet_type (m/c/d/r for management/control/data/reserved)
-e/--sub_type (hex value. example:
8/A/B/C for Beacon/Disassociation/Authentication/Deauth, when packet_type m
A/B/C/D for PS-Poll/RTS/CTS/ACK, when packet_type c
0/1/2/8 for Data/Data+CF-Ack/Data+CF-Poll/QoS-Data, when packet_type d)
-a/--addr1
-b/--addr2
-i/--sgi_flag (0,1)
-n/--num_packets
-s/--payload_size
-d/--delay
-h this menu
```
### Example:
Login/ssh to the board, Then
```
cd openwifi
./wgd.sh
./monitor_ch.sh sdr0 11
(Above will turn sdr0 into the monitor mode and monitor on channel 11)
./inject_80211/inject_80211 -m n -r 0 -n 10 -s 64 sdr0
(Above will inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size via NIC sdr0)
```
When above injection command is running, you could see the injected packets with wireshark (or other packet sniffer) on another WiFi device monitoring channel 11.
Or add extra virtual monitor interface on top of sdr0, and inject packets:
```
iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up
./inject_80211/inject_80211 -m n -r 0 -n 10 -s 64 mon0 # Inject 10 802.11n packets at 6.5Mbps bitrate and 64bytes size
```
### Link performance test
To make a profound experimental analysis on the physical layer performance, we can rely on automation scripts.
The following script will inject 100 802.11n packets at different bitrates and payload sizes.
```
#!/bin/bash
HW_MODE='n'
COUNT=100
DELAY=1000
RATE=( 0 1 2 3 4 5 6 7 )
SIZE=( $(seq -s' ' 50 100 1450) ) # paload size in bytes
IF="mon0"
for (( i = 0 ; i < ${#PAYLOAD[@]} ; i++ )) do
for (( j = 0 ; j < ${#RATE[@]} ; j++ )) do
inject_80211 -m $HW_MODE -n $COUNT -d $DELAY -r ${RATE[$j]} -s ${SIZE[$i]} $IF
sleep 1
done
done
```
On the receiver side, we can use tcpdump to collect the pcap traces.
```
iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up
tcpdump -i mon0 -w trace.pcap 'wlan addr1 ff:ff:ff:ff:ff:ff and wlan addr2 66:55:44:33:22:11'
```
Wlan addresses *ff:ff:ff:ff:ff:ff* and *66:55:44:33:22:11* are specific to our injector application.
Next, we analyze the collected pcap traces using the analysis tool provided.
```
analyze_80211 trace.pcap
```
An excerpt from a sample analysis looks the following
```
HW MODE RATE(Mbps) SGI SIZE(bytes) COUNT Duration(sec)
======= ========== === =========== ===== =============
802.11n 6.5 OFF 54 100 0.11159
802.11n 13.0 OFF 54 100 0.11264
802.11n 19.5 OFF 54 100 0.11156
802.11n 26.0 OFF 54 100 0.11268
802.11n 39.0 OFF 54 100 0.11333
802.11n 52.0 OFF 54 100 0.11149
802.11n 58.5 OFF 54 100 0.11469
802.11n 65.0 OFF 54 100 0.11408
```
================================================
FILE: doc/app_notes/iq-architecture.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/iq-capture-parameter.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/iq-information-format.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/iq-screen-shot.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/iq.md
================================================
We implement the **IQ sample capture** with interesting extensions: many **trigger conditions**; **RSSI**, RF chip **AGC** **status (lock/unlock)** and **gain**, Frequency offset FPGA vs Actual(floating point python algorithm based on IQ).
(By default, openwifi Rx baseband is muted during self Tx, to unmute Rx baseband and capture self Tx signal you need to run "./sdrctl dev sdr0 set reg xpu 1 1" after the test running)
[[Quick start](#Quick-start)]
[[Understand the IQ capture feature](#Understand-the-IQ-capture-feature)]
[[Config the IQ capture and interval](#Config-the-IQ-capture-and-interval)]
[[Config the iq_len](#Config-the-iq_len)]
[[Examine frequency offset estimation FPGA VS Python](#Examine-frequency-offset-estimation-FPGA-VS-Python)]
[[Calculate SNR based on IQ](#Calculate-SNR-based-on-IQ)]
[[Compile the side channel driver and user space program](#Compile-the-side-channel-driver-and-user-space-program)]
[[Run the IQ capture together with modes other than monitor](#Run-the-IQ-capture-together-with-modes-other-than-monitor)]
[[Map the IQ information to the WiFi packet](#Map-the-IQ-information-to-the-WiFi-packet)]
## Quick start
- Power on the SDR board.
- Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
ssh root@192.168.10.122
(password: openwifi)
cd openwifi
./wgd.sh
(Wait for the script completed)
./monitor_ch.sh sdr0 11
(Monitor on channel 11. You can change 11 to other channel that is busy)
insmod side_ch.ko iq_len_init=8187
(for smaller FPGA (7Z020), iq_len_init should be <4096, like 4095, instead of 8187)
./side_ch_ctl wh3h01
(Enable the IQ capture and configure the IQ data source)
./side_ch_ctl wh11d4094
(Above command is needed only when you run with zed, adrv9364z7020, zc702 board)
./side_ch_ctl g
```
You should see on board outputs like:
```
loop 64 side info count 61
loop 128 side info count 99
...
```
If the second number (side info count 61, 99, ...) keeps increasing, that means the trigger condition is met from time to time and the IQ sample is going to the computer smoothly.
- Open another terminal on the computer, and run:
```
cd openwifi/user_space/side_ch_ctl_src
python3 iq_capture.py
(for zed, adrv9364z7020, zc702 board, add argument that euqals to iq_len_init, like 4095)
```
You might need to install beforehand: "sudo apt install python3-numpy python3-matplotlib python3-tk". Now you should see 3 figures showing run-time **IQ sample**, **AGC gain and lock status** and **RSSI (uncalibrated)**. Meanwhile the python script prints the **timestamp**.
While running, all information is also stored into a file **iq.txt**. A matlab script **test_iq_file_display.m** is offered to help you do analysis on the IQ Information offline. For zed, adrv9364z7020, zc702 board, do not forget to change the **iq_len** in the matlab script to 4095.
## Understand the IQ capture feature
The IQ information is extracted via the openwifi **side channel** infrastructure. This figure explains the related modules (also related source code file name) and how the information goes from the SDR board to the computer.
The IQ information format is shown in this figure.
For each element, the actual size is 64bit.
- timestamp: 64bit TSF timer value when the capture is triggered.
- IQ
- The first two 16bit are used for I/Q sample from the antenna currently used
- The 3rd 16bit is AD9361 AGC gain (bit7 -- lock/unlock; bit6~0 -- gain value)
- The 4th 16bit is RSSI (half dB, uncalibrated). Please check xpu.v and sdr.c to understand how the raw RSSI value is finally calibrated and reported to Linux mac80211.
The python and Matlab scripts are recommended for you to understand the IQ packet format precisely.
## Config the IQ capture and interval
The quick start guide captures a period of history IQ when the packet FCS checksum is checked by Wifi receiver (no matter pass or fail). To initiate the capture with different trigger conditions and length, configuration commands should be issued before executing "**side_ch_ctl g**". The configuration command is realized by feeding a different parameter to "**side_ch_ctl**". The main parameters that are configurable are explained in this figure.
**iq_len** is the number of IQ samples captured per trigger condition met. The capture is started from the time **pre_trigger_len** IQ samples before the trigger moment. **iq_len** is set only one time when you insert the side_ch.ko. Please check the next section for **iq_len** configuration. This section introduces the setting of pre_trigger_len and trigger condition.
- pre_trigger_len
```
./side_ch_ctl wh11dY
```
The parameter **Y** specifies the pre_trigger_len. Valid range 0 ~ 8190. It is limited by the FPGA fifo size. For **small FPGA** (zed_fmcs2, adrv9364z7020, zc702), the valid range is 0 ~ **4094**.
- trigger condition
```
./side_ch_ctl wh8dY
```
The parameter **Y** specifies the trigger condition. Valid range 0 ~ 31, which is explained in this table.
value|meaning
-----|-------
0 |receiver gives FCS checksum result. no matter pass/fail. Or free run
1 |receiver gives FCS checksum result. pass
2 |receiver gives FCS checksum result. fail
3 |the tx_intf_iq0 becomes non zero (the 1st I/Q out)
4 |receiver gives SIGNAL field checksum result. pass
5 |receiver gives SIGNAL field checksum result. fail
6 |receiver gives SIGNAL field checksum result. no matter pass/fail. HT packet
7 |receiver gives SIGNAL field checksum result. no matter pass/fail. non-HT packet
8 |receiver gives long preamble detected
9 |receiver gives short preamble detected
10|RSSI (half dB uncalibrated) goes above the threshold
11|RSSI (half dB uncalibrated) goes below the threshold
12|AD9361 AGC from lock to unlock
13|AD9361 AGC from unlock to lock
14|AD9361 AGC gain goes above the threshold
15|AD9361 AGC gain goes below the threshold
16|tx_control_state_hit when xpu tx_control_state hit the specified value (by side_ch_ctl wh5)
17|phy_tx_done signal from openofdm tx core
18|positive edge of tx_bb_is_ongoing from xpu core
19|negative edge of tx_bb_is_ongoing from xpu core
20|positive edge of tx_rf_is_ongoing from xpu core
21|negative edge of tx_rf_is_ongoing from xpu core
22|phy_tx_started and this tx packet needs ACK
23|phy_tx_done and this tx packet needs ACK
24|both tx_control_state and phy_type (0 Legacy; 1 HT; 2 HE) hit (by side_ch_ctl wh5)
25|addr1 and/or addr2 are matched. Please check the related addr1/2 match config in CSI app note
26|positive edge of tx_rf_is_ongoing and this tx packet needs ACK
27|negative edge of tx_rf_is_ongoing and this tx packet needs ACK
28|tx_bb_is_ongoing and I/Q amplitude from the other antenna is above rssi_or_iq_th
29|tx_rf_is_ongoing and I/Q amplitude from the other antenna is above rssi_or_iq_th
30|start tx, meanwhile I/Q amplitude from the other antenna is above rssi_or_iq_th
31|start tx and need for ACK, meanwhile I/Q amplitude from the other antenna is above rssi_or_iq_th
Hardware register 5 has fields for multi-purpose. bit0 for free running mode. bit7~4 for tx_control_state target value. bit 9~8 for phy_type. For example, set target tx_control_state to SEND_BLK_ACK (3) and phy_type to HE (2):
```
./side_ch_ctl wh5h230
```
If free running is wanted (alway trigger), please use the following two commands together.
```
./side_ch_ctl wh8d0
./side_ch_ctl wh5d1
```
To set the RSSI threshold
```
./side_ch_ctl wh9dY
```
The parameter **Y** specifies the RSSI threshold. Valid range 0 ~ 2047.
To set the AGC gain threshold
```
./side_ch_ctl wh10dY
```
The parameter **Y** specifies the AGC gain threshold. Valid range 0 ~ 127.
The command "**side_ch_ctl g**" will perform IQ capture every 100ms until you press ctrl+C. To use a different capture interval:
```
side_ch_ctl gN
```
The interval will become N*1ms
## Examine frequency offset estimation FPGA VS Python
The script **iq_capture_freq_offset.py** can show the FPGA estimated frequency offset and the actual frequency offset calculated by floating point python algorithm. If they are very different, you could try to override the FPGA frequency estimation module by **user_space/receiver_phase_offset_override.sh** with the result from the python algorithm.
**DO NOT FORGET** to change **LUT_SIZE** in the **iq_capture_freq_offset.py** if you are testing 80211ax.
To use the **iq_capture_freq_offset.py**, here is an example command sequence (also available at the beginning of **iq_capture_freq_offset.py**):
- On board, insert the module with iq length 1500 and set: pre trigger length 1497, the MAC address of the peer, the self MAC address, enable the MAC address match, trigger condition 25 (both addr1 and addr2 match), starting capture.
```
insmod side_ch.ko iq_len_init=1500
./side_ch_ctl wh11d1497
./side_ch_ctl wh7h635c982f
./side_ch_ctl wh6h44332236
./side_ch_ctl wh1h6001
./side_ch_ctl wh8d25
./side_ch_ctl g0
```
In the case of totally clean/non-standard channel, long preamble detected can also be used as trigger condition:
```
insmod side_ch.ko iq_len_init=1500
./side_ch_ctl wh11d1497
./side_ch_ctl wh8d8
./side_ch_ctl g0
```
- On host PC:
```
python3 iq_capture_freq_offset.py 1500
```
It will print phase_offset value (FPGA VS python) in the shell, and plot some real-time figures.
## Calculate SNR based on IQ
After the IQ is captured and the .mat file has been generated by **test_iq_file_display.m**, **show_iq_snr.m** can be used to calculate the SNR (Signal to Noise Ratio) based on the .mat file in Matlab.
It is recommended to do this SNR check with single signal/packet source in a very clean (such as cable test in non-standard channels) environment. Otherwise the SNR statistics over variant link status is less meaningful.
- The 1st step is running with .mat file as the only argument in Matlab:
```
show_iq_snr(mat_file_name)
```
It will show a figure of relative RSSI change (dB). You should decide the middle value which is roughly the middle point between the high RSSI (signal) and low RSSI.
- The 2nd step is running with .mat file and the middle value as arguments in Matlab:
```
show_iq_snr(mat_file_name, middle_value)
```
It will show the SNR in Matlab command line, and plot the figure with signal and noise regions identified.
## Config the iq_len
The **iq_len** (number of IQ sample per capture) is configurable in case you want less IQ samples per capture so that it can be triggered more times during a specific analysis period. The valid value is 1~**8187**. For **small FPGA** (zed_fmcs2, adrv9364z7020, zc702), the valid range is 0 ~ **4095**. It is independent from pre_trigger_len, and it can be less than pre_trigger_len if you want. You should align the **iq_len** value at the side_ch.ko, iq_capture.py and test_iq_file_display.m.
- When insert the kernel module, use:
```
insmod side_ch.ko iq_len_init=3000
```
Here 3000 is an example. **ATTENTION:** You need to specify **iq_len_init** explicitly to turn on IQ capture, which will turn off the default CSI mode. Insert the side_ch.ko without any parameter will run the default CSI mode.
- When launch the python script, use:
```
python3 iq_capture.py 3000
```
- When use the matlab script, please change the **iq_len** variable in the script to 3000.
## Compile the side channel driver and user space program
- side_ch.ko
```
$OPENWIFI_DIR/driver/side_ch/make_driver.sh $OPENWIFI_DIR $XILINX_DIR ARCH_BIT
(For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
```
- side_ch_ctl (take user_space/side_ch_ctl_src/side_ch_ctl.c and compile it on board!)
```
gcc -o side_ch_ctl side_ch_ctl.c
```
## Run the IQ capture together with modes other than monitor
The openwifi IQ capture feature could run with not only monitor mode but also other modes, such as AP-Client or ad-hoc mode. After the communication functionality is fully up in those modes, you can start IQ capture from "**insmod side_ch.ko**" and "**./side_ch_ctl g**" on board as described in the previous sections to extract IQ information to your computer.
## Map the IQ information to the WiFi packet
Recent tutorial: https://github.com/open-sdr/openwifi/discussions/344
Old text:
If you want to relate the IQ information to the WiFi packet, you need to capture WiFi packets (tcpdump/wireshark/etc) while capturing IQ. Then you can relate the timestamp between WiFi packet and IQ information. Please be noticed that the timestamp in the IQ information is the moment when capture is triggered, which could be different from the timestamp reported in the packet capture program. But since they share the same time base (TSF timer), you can relate them easily by analyzing the WiFi packet and IQ sample sequence.
Please learn the python and Matlab script to extract IQ information per capture according to your requirement.
================================================
FILE: doc/app_notes/iq_2ant-screen-shot.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/iq_2ant-setup.png.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/iq_2ant.md
================================================
Instead of [**normal IQ sample capture**](iq.md), this app note introduces how to enable the I/Q capture for dual antennas. Besides the I/Q from the main antenna (that is selected by baseband), the I/Q samples from the other antenna (monitoring antenna) is captured as well (coherently synchronized) in this dual antenna mode. You are suggested to read the [**normal IQ sample capture**](iq.md) to understand how we use the side channel to capture I/Q samples by different trigger conditions.
(By default, openwifi Rx baseband is muted during self Tx, to unmute Rx baseband and capture self Tx signal you need to run "./sdrctl dev sdr0 set reg xpu 1 1" after the test running)
This feature also support capturing TX I/Q (loopback) to test the baseband transmitter.
- [[Quick start for collision capture](#Quick-start-for-collision-capture)]
- [[Quick start for TX IQ capture in trigger mode](#Quick-start-for-TX-IQ-capture-in-trigger-mode)]
- [[Quick start for TX IQ capture in free running mode](#Quick-start-for-TX-IQ-capture-in-free-running-mode)]
## Quick start for collision capture
The main antenna rx0 (by default selected by baseband if you do not select explicitly by set_ant.sh) is always used for communication and I/Q capture. Meanwhile, the other antenna (rx1 -- monitoring antenna) will be also available for capturing rx I/Q if you are using AD9361 based RF board, such as fmcomms2/3 and adrv9361z7035, by turning on the **dual antenna capture** mode. In this case, you can place the other antenna (rx1) close to the communication peer (for example, the other WiFi node) to capture the potential collision by monitoring rx1 I/Q. The nature of collision is that both sides of a communication link are trying to do transmission at the same time.
The collision capture steps:
- Change rx1 AGC to manual mode instead of fast_attack in rf_init.sh by:
```
echo manual > in_voltage1_gain_control_mode
```
- Change rx1 gain to a low level, such as 20, by:
```
echo 20 > in_voltage1_hardwaregain
```
- Use the new rf_init.sh script to boot up the SDR board, and setup the working scenario.
- Setup the side channel:
```
insmod side_ch.ko iq_len_init=8187
(iq_len_init should be <4096, like 4095, if smaller FPGA, like z7020, is used)
./side_ch_ctl wh11d2000
(Set a smaller pre_trigger_len 2000, because we want to see what happens after the trigger instead of long period stored before the trigger)
```
- Put the other antenna (rx1) close to the peer WiFi node, set trigger condition to 23 (baseband tx done)
```
./side_ch_ctl wh8d23
```
- Enable the **dual antenna capture** mode
```
./side_ch_ctl wh3h11
```
- Run some traffic between the SDR board and the peer WiFi node, and start the user space I/Q capture program
```
./side_ch_ctl g
```
If the printed "**side info count**" is increasing, it means the trigger condition is met from time to time.
- On remote computer, run
```
python3 iq_capture_2ant.py
(if smaller FPGA, like z7020, is used, add a argument that equals to iq_len_init, like 4095)
```
Above script will plot the real-time rx0 and rx1 I/Q captured each time the trigger condition is met. .
In the above example, the upper half shows the signal received from the main antenna (self tx is not seen because of self muting in FPGA), the lower half shows not only the rx signal from the monitoring antenna but also the tx signal from the main antenna due to coupling.
Meanwhile the script also prints the maximum amplitude of the rx0 and rx1 I/Q samples. Check the 3rd column that is displayed by the script: Those small value printing indicate noise (most probably, because the rx1 gain is very low). The big value printing indicates a packet from rx1 (although rx1 has very low gain, rx1 is very close to the peer WiFi node). Go through the noise and the packet max I/Q amplitude numbers from rx1 printing (the 3rd column), and decide a threshold value that is significantly higher than the noise but less than those big values (packets).
- Set trigger condition to 29, which means that rx1 I/Q is found larger than a threshold while SDR is transmitting -- this means a collision condition is captured because rx1 I/Q implies the transmitting from the peer WiFi node. The threshold value is decided in the previous step (2500 is assumed here).
```
(Quit side_ch_ctl by Ctrl+C)
./side_ch_ctl wh8d29
./side_ch_ctl wh9d2500
./side_ch_ctl g
```
- Now the trigger condition can capture the case where both sides happen to transmit in an overlapped duration. If the printed "**side info count**" is increasing, it means the collision happens from time to time.
- You can also see it via iq_capture_2ant.py or do offline analysis by test_iq_2ant_file_display.m
- Check the **iq1** signal in FPGA ILA/probe (triggered by signal "iq_trigger") for further debug if you want to know what exactly happened when collision is captured.
## Quick start for TX IQ capture in trigger mode
To capture the TX I/Q (baseband loopback), a scenario where openwifi will do TX needs to be set up. Such as beacon TX when openwifi act as AP, or [packet injection](inject_80211.md).
The example command sequence on board and explanations are as follows.
```
cd openwifi
./fosdem.sh
insmod side_ch.ko iq_len_init=511
(511 I/Q samples cover the short, long preamble and some OFDM symbols. Change it according to your case)
./side_ch_ctl wh11d1
(1 sample before the trigger met will be captured. So most of the I/Q will be captured after trigger met)
./side_ch_ctl wh8d16
(trigger condition 16: phy_tx_started signal from openofdm tx core)
./side_ch_ctl wh5h2
(I/Q source selection: 2--openofdm_tx core; 4--tx_intf)
./side_ch_ctl wh3h11
./side_ch_ctl g1
```
On computer:
```
openwifi/user_space/side_ch_ctl_src/python3 iq_capture_2ant.py 511
```
## Quick start for TX IQ capture in free running mode
```
cd openwifi
./fosdem.sh
insmod side_ch.ko iq_len_init=511
(511 I/Q samples cover the short, long preamble and some OFDM symbols. Change it according to your case)
./side_ch_ctl wh11d1
(1 sample before the trigger met will be captured. So most of the I/Q will be captured after trigger met)
./side_ch_ctl wh8d0
(trigger condition 0 is needed for free running mode)
./side_ch_ctl wh5h3
(I/Q source selection: 3--openofdm_tx core; 5--tx_intf)
./side_ch_ctl wh3h11
./side_ch_ctl g1
```
On computer:
```
openwifi/user_space/side_ch_ctl_src/python3 iq_capture_2ant.py 511
```
================================================
FILE: doc/app_notes/iq_ack_timing.md
================================================
Thsi app note show how to measure the ACK timing based on [**IQ sample capture**](iq.md)
## Quick start
- Setup a normal communication link between the SDR board and other devices. (Check Quick start guide in README or other app notes)
- Setup IQ capture triggered by the event of ACK sending.
```
./sdrctl dev sdr0 set reg xpu 1 1
insmod side_ch.ko iq_len_init=8187
(For smaller FPGA (7Z020), iq_len_init should be <4096, like 4095, instead of 8187)
./side_ch_ctl wh11d4096
(For smaller FPGA (7Z020), 4094 should be 2048)
./side_ch_ctl wh3h21
(Enable the IQ capture and configure the correct IQ data composition for ACK timing check)
./side_ch_ctl wh5h20
./side_ch_ctl wh8d16
./side_ch_ctl g0
```
The 1st command keeps the receiver always ON to monitor incoming packet and ACK sent by its own. The second and the 3rd command set the capture length and pre trigger length.
The 4th command sets the target tx_control_state to SEND_DFL_ACK (check tx_control.v) -- the value is defined at bit 7~4, so 0x2 becomes 0x20.
Other useful state values: SEND_BLK_ACK 0x30, RECV_ACK 0x60. Other state, such as RECV_ACK_WAIT_SIG_VALID/0x50, is not recommended, otherwise the Matlab analysis script needs to be changed accordingly.
The next command sets the trigger condition to the tx_control_state_hit (index 16. check side_ch_control.v), which means that when the real-time tx_control_state is equal
to the target set by previous command, IQ capture will be performed once.
The trigger condition could also be the combination of tx_control_state and PHY type (0 - Legacy; 1 - HT; 2 - HE) of the received packet. This allows us to monitor
the specific ACK Tx GAP after receiving the packet with the specific PHY type. To use this, PHY type should be put into the position of "x", and trigger condition index
should be 24 instead of 16.
```
./side_ch_ctl wh5hx20
./side_ch_ctl wh8d24
```
- You should see on board outputs like (Be sure running traffics to trigger ACK event!):
```
loop 64 side info count 3
loop 128 side info count 5
...
```
If the second number (side info count 61, 99, ...) keeps increasing, that means the trigger condition is met from time to time and the IQ sample is going to the computer smoothly.
- Open another terminal on the computer, and run:
```
cd openwifi/user_space/side_ch_ctl_src
python3 iq_capture.py
(for zed, adrv9364z7020, zc702 board, add argument that euqals to iq_len_init, like 4095)
```
While running traffic, you should see 3 figures popped up with run-time **IQ sample**, **AGC gain and lock status** and **RSSI (uncalibrated)**. Meanwhile the python script prints the **timestamp**. In the IQ sample window, IQ samples of two packets are expected in the central position spaced by +/-16us (320 samples), which is the ACK timing.
While running, all information is also stored into a file **iq.txt**.
## Test methodology
The timing of ACK openwifi sent becomes complicated due to different decoding latency of incoming packet when there are different number of bytes/bits in the last OFDM symbol. We should check this after any change that potentially affects the decoding latency.
To test this, another openwifi board can be used as a client, and sends packets with different numbers of bytes in the last OFDM symbol through all MCSs. Check
[this app note](frequent_trick.md#Tx-rate-config) for overriding MCS. The following bash script can be used to send packets in different packet sizes (20 to 60 bytes in this example). DO NOT forget to set up the capture on board and launch the "python3 iq_capture.py" on the computer before running the following commands.
```
for nbyte in {20..60}; do ping 192.168.13.1 -s $nbyte -c 1; sleep 0.3; done
```
Or use any other device/test-box that can send out packet with specified MCS and size towards openwifi board.
## Analyze the ACK timing by Matlab script and Wireshark
A matlab script **test_iq_file_ack_timing_display.m** is offered to help you do analysis on the ACK timing based on **iq.txt**. For boards with small FPGA (7020), do not forget to give 4095 (**iq_len**) as the 1st argument.
```
test_iq_file_ack_timing_display(8187);
```
Figure 1 shows the timestamp of all received packets. Figure 2~4 shows the IQ sample and related signals of a specific capture. Figure 5 shows the GAP between a received ACK and the packet sent by openwifi -- Rx ACK GAP. Figure 6 shows the GAP between a received packet and the ACK sent by openwifi -- Tx ACK GAP. Normally they should around 16us. "-1" means no such an event is observed at that capture.
Above figure shows that there are two abnormal GAPs for Tx ACK. One is around 12us (Cap idx 2), the other is -1 (Cap idx 11).
To look into the details of the capture index 2, that capture index should be given as the 2nd parameter to the Matlab script.
```
test_iq_file_ack_timing_display(8187, 2);
```
From above figure, it was discovered that the DC power caused by AGC action before the actual ACK packet is regarded as the beginning of the ACK packet, that is why the GAP calculation result is smaller. This bug has been fixed already in the Matlab analysis script. Following figure shows the fixed analysis result.
To relate the captured IQ snapshot (with ACK timing in it) with the detailed packet information in Wireshark, please check this discussion on github: https://github.com/open-sdr/openwifi/discussions/344 .
================================================
FILE: doc/app_notes/mimo.png.license
================================================
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/mpdu-aggr.png.license
================================================
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/app_notes/packet-iq-self-loopback-test.md
================================================
One super power of the openwifi platform is "**Full Duplex**" which means that openwifi baseband can receive its own TX signal.
This makes the IQ sample, WiFi packet and CSI self loopback test possible. Reading the normal [IQ sample capture app note](iq.md) and [CSI radar app note](radar-self-csi.md) will help if you have issue or want to understand openwifi side channel (for IQ and CSI) deeper.
[[IQ self loopback quick start](#IQ-self-loopback-quick-start)]
[[Check the packet loopback on board](#Check-the-packet-loopback-on-board)]
[[IQ self loopback config](#IQ-self-loopback-config)]
[[CSI FPGA self loopback quick start](#CSI-FPGA-self-loopback-quick-start)]
## IQ self loopback quick start
(Please replace the IQ length **8187** by **4095** if you use low end FPGA board: zedboard/adrv9464z7020/antsdr/zc702/sdrpi)
- Power on the SDR board.
- Put the Tx and Rx antenna as close as possible.
- Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
# ssh into the SDR board, password: openwifi
ssh root@192.168.10.122
cd openwifi
# Bring up the openwifi NIC sdr0
./wgd.sh
# Setup monitor mode in WiFi channel 44. You should find a channel as clean as possible in your location. Note that some channels don't work, so stick to 44 or 48 for now.
./monitor_ch.sh sdr0 44
# Turn off CCA by setting a very high threshold that make the CSMA engine always think the channel is idle (no incoming signal is higher than this threshold)
./sdrctl dev sdr0 set reg xpu 8 1000
# Load side channel kernel module with buffer lenght of 8187 (replace this with 4095 when using low end FPGA board)
insmod side_ch.ko iq_len_init=8187
# Set 100 to register 11. It means the pre trigger length is 100, so we mainly capture IQ after trigger condition is met
./side_ch_ctl wh11d100
# Set 16 to register 8 -- set trigger condition to phy_tx_started signal from openofdm tx core
./side_ch_ctl wh8d16
# Unmute the baseband self-receiving to receive openwifi own TX signal/packet -- important for self loopback!
./sdrctl dev sdr0 set reg xpu 1 1
# Set the loopback mode to over-the-air
./side_ch_ctl wh5h0
(./side_ch_ctl wh5h4 for FPGA internal loopback)
# Relay the FPGA IQ capture to the host computer that will show the captured IQ later on)
./side_ch_ctl g0
```
You should see on outputs like:
```
loop 22848 side info count 0
loop 22912 side info count 0
...
```
Now the count is always 0, because we haven't instructed openwifi to send packet for loopback test.
- Leave above ssh session untouched. Open a new ssh session to the board from your computer. Then run on board:
```
cd openwifi/inject_80211/
make
# Build our example packet injection program
./inject_80211 -m n -r 5 -n 1 sdr0
# Inject one packet to openwifi sdr0 NIC
```
Normally in the previous ssh session, the count becomes 1. It means one packet (of IQ sample) is sent and captured via loopback over the air.
If 1 is not seen, you can try to put the receiver into reset state, so it won't block the system in case it runs into dead state
```
./sdrctl dev sdr0 set reg rx 0 1
```
- On your computer (NOT ssh onboard!), run:
```
cd openwifi/user_space/side_ch_ctl_src
python3 iq_capture.py 8187
```
You might need to install beforehand: "sudo apt install python3-numpy python3-matplotlib python3-tk".
- Leave the above host session untouched. Let's go to the second ssh session (packet injection), and do single packet Tx again:
```
./inject_80211 -m n -r 5 -n 1 sdr0
```
Normally in the 1st ssh session, the count becomes 2. You should also see IQ sample capture figures like this:
- Stop the python3 script, which plots above, in the host session. A file **iq.txt** is generated. You can use the Matlab script test_iq_file_display.m
to do further offline analysis, or feed the IQ sample to the openwifi receiver simulation, etc.
## Check the packet loopback on board
- While signal/packet is looped back, you can capture it on board via normal sniffer program for further check/analysis on the packet (bit/byte level instead of IQ level), such as tcpdump or tshark.
A new ssh session to the board should be opened to do this before running the packet injection:
```
tcpdump -i sdr0
```
Run the packet injection "./inject_80211 -m n -r 5 -n 1 sdr0" in another session, you should see the packet information printed by tcpdump from self over-the-air loopback. In case you put the receiver into reset state in the previous IQ loopback, you should put the receiver back to normal for packet loopback (otherwise the receiver won't decode the IQ signal back to packet):
```
./sdrctl dev sdr0 set reg rx 0 0
```
- You can also see the openwifi printk message of Rx packet (self Tx looped back) while the packet comes to the openwifi Rx interrupt.
A new ssh session to the board should be opened to do this before running the packet injection:
```
cd openwifi
./sdrctl dev sdr0 set reg drv_rx 7 7
./sdrctl dev sdr0 set reg drv_tx 7 7
# Turn on the openwifi Tx/Rx printk logging
```
Stop the "./side_ch_ctl g0" in the very first ssh session. Run the packet injection, then check the printk message:
```
./inject_80211/inject_80211 -m n -r 5 -n 1 sdr0
dmesg
```
You should see the printk message of packet Tx and Rx from the openwifi driver (sdr.c).
## IQ self loopback config
- By default, the loopback is via the air (from Tx antenna to Rx antenna). FPGA inernal loopback option is offered to have IQ sample and packet without
any interference. To have FPGA internal loopback, replace the "./side_ch_ctl wh5h0" during setup (the very 1st ssh session) by:
```
./side_ch_ctl wh5h4
```
- Lots of packet injection parameters can be set: number of packet, type (data/control/management), MCS/rate, size, interval, etc. Please run the packet injection
program without any arguments to see the help.
- Besides the packet Tx via injection over monitor mode for loopback test, normal WiFi mode (AP/Client/ad-hoc) can also run together with self loopback.
For instance, run **fosdem.sh** instead of **wgd.sh** to setup an openwifi AP that will transmit beacons. The wgd.sh can also be replaced with other scenario
setup scripts. Please check [Application notes](README.md)
- To understand deeper of all above commands/settings, please refer to [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md) and
[Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md)
## CSI FPGA self loopback quick start
This section will show how to connect the WiFi OFDM transmitter to the receiver directly inside FPGA, and show the ideal CSI/constellation/frequency-offset. (For CSI over the air loopback, please refer to [CSI radar app note](radar-self-csi.md))
Command sequence on board:
```
cd openwifi
./wgd.sh
./monitor_ch.sh sdr0 6
insmod side_ch.ko
./side_ch_ctl g
```
Open another ssh session on board, then:
```
cd openwifi
./sdrctl dev sdr0 set reg rx_intf 3 256
(Above command let the FPGA Tx IQ come to receiver directly. Set 256 back to 0 to let receiver back connect to AD9361 RF frontend)
./sdrctl dev sdr0 set reg rx 5 768
(Disable the receiver FFT window shift. By default it is 1 (768+1) -- good for multipath, overfitting for direct loopback)
./inject_80211/inject_80211 -m n -r 7 -n 99999 -s 1400 -d 1000000 sdr0
(Transmit 802.11n MCS7 1400Byte packet every second)
```
Command on computer:
```
cd openwifi/user_space/side_ch_ctl_src
python3 side_info_display.py
```
Now you should see the following screenshot that shows the CSI/constellation/frequency-offset over this in-FPGA ideal channel.
================================================
FILE: doc/app_notes/perf_counter.md
================================================
Counter/statistics (number of TX packet, RX packet, watchdog event, etc.) in FPGA is offered via register write/read.
[[PHY RX TX event counter in side channel](#PHY-RX-TX-event-counter-in-side-channel)]
[[PHY RX watchdog event counter in openofdm rx](#PHY-RX-watchdog-event-counter-in-openofdm-rx)]
## PHY RX watchdog event counter in openofdm rx
There is a signal_watchdog module inside openofdm_rx to detect the abnormal signal as early as possible, so that the receiver will not be busy with fake/abnormal signal for long time. (If the receiver is attracted by fake/abnormal signal easily, it could miss the normal/target packet).
To access the watchdog event counter in openofdm_rx, [sdrctl command](../README.md#sdrctl-command) is used.
To select the event you are interested in:
```
sdrctl dev sdr0 set reg rx 17 event_type
```
The event_type options:
- 0: phase_offset(sync_short) too big
- 1: Too many equalizer out small values
- 2: DC/slow-sine-wave is detected
- 3: Packet too short
- 4: Packet too long
To read the event counter (selected by register 17 above):
```
sdrctl dev sdr0 get reg rx 30
```
Write any value to above register 30 will clear the selected event counter (by register 17).
## PHY RX TX event counter in side channel
The 1st step is alway loading the side channel kernel module:
```
insmod side_ch.ko
```
The register write command is:
```
./side_ch_ctl whXdY
X -- register index
Y -- decimal value to be written
./side_ch_ctl whXhY
X -- register index
Y -- hex value to be written (useful for MAC address)
```
Write register 26~31 with arbitrary value to reset the corresponding counter to 0.
The register read command is:
```
./side_ch_ctl rhX
X -- register index
```
**Register definition:**
The register 26~31 readback value represents the number of event happened. Each register has two event sources that can be selected via bit in register 19.
register idx|source selection reg19|event
------------|----------------------|-----------
26 |reg19[0] == 0 |short_preamble_detected
26 |reg19[0] == 1 |phy_tx_start
27 |reg19[4] == 0 |long_preamble_detected
27 |reg19[4] == 1 |phy_tx_done
28 |reg19[8] == 0 |pkt_header_valid_strobe
28 |reg19[8] == 1 |rssi_above_th
29 |reg19[12] == 0 |pkt_header_valid_strobe&pkt_header_valid
29 |reg19[12] == 1 |gain_change
30 |reg19[16] == 0 |((fcs_in_strobe&addr2_match)&pkt_for_me)&is_data
30 |reg19[16] == 1 |agc_lock
31 |reg19[20] == 0 |(((fcs_in_strobe&fcs_ok)&addr2_match)&pkt_for_me)&is_data
31 |reg19[20] == 1 |tx_pkt_need_ack
Note: fcs_in_strobe means decoding is done (not necessarily CRC is correct); fcs_ok 1 means CRC correct; fcs_ok 0 means CRC not correct.
Note: addr2_match means addr2 matches to the register (addr2_target) value; pkt_for_me means addr1 matches self mac addr; is_data means the packet type is data.
Configuration register:
register idx|meaning |note
------------|----------------------|-----------
7 |addr2 target value |fcs event always needs addr2 match
9 |threshold for event rssi_above_th|check auto_lbt_th in ad9361_rf_set_channel of sdr.c to estimate a proper value
Note: addr2 (source/sender's MAC address) target setting uses only 32bit. For address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
Note: read register 62 of xpu for some addr2 captured by the receiver
================================================
FILE: doc/app_notes/radar-self-csi.md
================================================
One super power of the openwifi platform is "**Full Duplex**" which means that openwifi baseband can receive its own TX signal. Just like a radar! This brings a unique capability of "**joint radar and communication**" to openwifi. For instance, put two directional antennas to openwifi TX and RX, and the **CSI** (Channel State Information) of the self-TX signal will refect the change of the target object.
(See this https://github.com/open-sdr/openwifi/discussions/344 to understand how to map the collected data to the packet via the TSF timestamp)
## Quick start
- Power on the SDR board.
- Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
```
ssh root@192.168.10.122
(password: openwifi)
```
- On computer, build the latest driver and FPGA package after clone/update openwifi and openwifi-hw-img repository:
```
export XILINX_DIR=your_Xilinx_install_directory
(Example: export XILINX_DIR=/opt/Xilinx. The Xilinx directory should include sth like: Downloads, Vitis, etc.)
export OPENWIFI_HW_IMG_DIR=your_openwifi-hw-img_directory
(The directory where you get the open-sdr/openwifi-hw-img repo via git clone)
export BOARD_NAME=your_board_name
(Check the BOARD_NAME definitions in README)
cd openwifi/user_space
./drv_and_fpga_package_gen.sh $OPENWIFI_HW_IMG_DIR $XILINX_DIR $BOARD_NAME
scp drv_and_fpga.tar.gz root@192.168.10.122:openwifi/
scp ./side_ch_ctl_src/side_ch_ctl.c root@192.168.10.122:openwifi/
scp ./inject_80211/* root@192.168.10.122:openwifi/inject_80211/
```
- On SDR board (/root/openwifi directory):
```
cd /root/openwifi/
./wgd.sh drv_and_fpga.tar.gz
./monitor_ch.sh sdr0 1
insmod ./drv_and_fpga/side_ch.ko
gcc -o side_ch_ctl side_ch_ctl.c
./side_ch_ctl wh1h4001
./side_ch_ctl wh7h4433225a
(Above two commands ensure receiving CSI only from XX:XX:44:33:22:5a, which will be set by our own packet injector later)
./sdrctl dev sdr0 set reg xpu 1 1
(Above unmute the baseband self-receiving to receive openwifi own TX signal/packet)
./side_ch_ctl g0
```
- Open another ssh session on SDR board:
```
cd /root/openwifi/inject_80211
make
./inject_80211 -m g -r 4 -t d -e 0 -b 5a -n 99999999 -s 20 -d 1000 sdr0
(Above command injects the 802.11a/g packet, for 802.11n packet please use:
./inject_80211 -m n -r 4 -t d -e 8 -b 5a -n 99999999 -s 20 -d 1000 sdr0)
```
- Now you should see the increasing numbers in the previous ssh terminal of the SDR board.
- On your computer (NOT ssh session!), run:
```
cd openwifi/user_space/side_ch_ctl_src
python3 side_info_display.py 8 waterfall
```
You might need to install beforehand: "sudo apt install python3-numpy python3-matplotlib python3-tk". Now you should see figures showing run-time **CSI**, **CSI waterfall**, **Equalizer out** and **frequency offset**. The following photo shows the CSI change in the waterfall plot when I left my seat in front of two directional antennas (Tx/Rx antenna).
While running, all CSI data is also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do CSI analysis offline. In this case, run **test_side_info_file_display** in Matlab.
Please learn the python and Matlab script for CSI data structure per packet according to your requirement.
Do read the [normal CSI app note](csi.md) to understand the basic implementation architecture.
================================================
FILE: doc/app_notes/subcarriers.png.license
================================================
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/asic/skywater-130-pdk-and-asic-considerations.md
================================================
Hello,
The skywater PDK and free MPW shuttle are interesting. And indeed we are asked many times to consider sky130 or other ASIC process MPW.
We do agree that building a real openwifi chip will probably (or not) mean a lot for the community, user and the world.
But, due to our limited bandwidth, currently we are focusing on making the openwifi IP more stable/mature/as-good-as COTS WiFi chip by using the FPGA verification platform, so we haven’t found time to take a look at a real WiFi chip design yet.
WiFi chips could be as cheap as 0.5USD, but it doesn't mean the WiFi chip is simple. This is contrary to many people’s minds. I tried to explain the complexity of the WiFi chip in some videos, such as the FOSDEM and Libreplanet videos on this page: https://github.com/open-sdr/openwifi/blob/master/doc/videos.md . The WiFi chip is cheap only because they are sold so many per year. From this perspective, the WiFi chip is really an essential tiny thing of the modern world.
But we are definitely glad to support/answer-questions if someone else could jump in and do a solid analysis on the ASIC design effort. Some hints:
1 . The info and communication hub is our github: https://github.com/open-sdr/openwifi . The FPGA code is in https://github.com/open-sdr/openwifi-hw .
2 . The best way to get full picture and further info (resource/power/clock-speed/etc) of the openwifi FPGA design is downloading Xilinx Vivado (version is listed on our github) tool chain, and go through our full FPGA build procedure (README of openwifi-hw: https://github.com/open-sdr/openwifi-hw/blob/master/README.md ), where you will see the full system block diagram: not only the openwifi IP, but also all interfacing/peripheral IP around. Of course many of them are Xilinx/Analog-Devices specific.
3 . You don’t need to pay any fee for Xilinx Vivado, if you chose the FPGA boards (the full list of supported FPGA board is in the README of openwifi: https://github.com/open-sdr/openwifi/blob/master/README.md ) that has 7020 FPGA, because Xilinx offer free offer for that small scale FPGA.
4 . Try to find out all the vendor/3rd-part (Xilinx/Analog-Devices/etc) IPs, and evaluate/estimate how big the efforts will be if they need to be turned into sky130 or other ASIC design. As far as I remember (not full list), inside openwifi IP, we use these IP cores from Xilinx:
- FFT
- Viterbi decoder
- FIFO
- dual port RAM
- ROM
- FIR filter
- AXI stream DMA
- AXI lite bus
- integer divider
- integer multiplexer
- etc.
I guess most of them need to be ported if we go for a real chip.
5 . Also outside openwifi IP, there are interfacing/peripheral IPs from Xilinx/Analog-Devices, which can be seen if you create and open the openwifi project block diagram in Vivado (follow the openwifi-hw README). Two special things: RF and ARM processor interconnection.
- Currently the RF front-end is AD9361 (off-FPGA), which is not a dedicated WiFi front-end (2.4GH/5GHz only). Instead, AD9361 is a quite expensive front-end that supports 70M~6GHz for SDR (Software Defined Radio) applications. So of course, there will be dedicated AD9361 interfacing IPs from Analog Devices (open source as well: https://github.com/analogdevicesinc/hdl, but the license situation is complicated: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE )
- Unlike usual WiFi chips that work with processors via USB/PCIe/SDIO/etc bus, openwifi IP interconnects to the ARM processor via AXI bus. This brings us some unique benefits, such as low latency, but it also makes the IP quite platform dependent.
6 . Last but not least, considering the efforts (seems big) needed for a real openwifi ASIC, we believe that some bigger/stronger organizations (like foundation/company/person), that have rich experience on IP/licensing analysis and ASIC design, could set up an initiative to work on this openwifi chip activity. Of course, we will be more than happy to join and support it. But to be honest, the openwifi team has very limited ASIC design experiences, and we mainly focus on FPGA for now (due to the bandwidth: personal resource, funding, etc.)
Further discussions/ideas? Feel free to reach out to us!
Best regards,
Xianjun
================================================
FILE: doc/cite-openwifi-github-code.md
================================================
```
@electronic{openwifigithub,
author = {Jiao, Xianjun and Liu, Wei and Mehari, Michael and Thijs, Havinga and Muhammad, Aslam and Chen, Baiheng},
title = {open-source IEEE802.11/Wi-Fi baseband chip/FPGA design},
url = {https://github.com/open-sdr},
year = {2023},
}
```
================================================
FILE: doc/cite-openwifi-vtc-paper.md
================================================
```
@inproceedings{jiao2020openwifi,
title={openwifi: a free and open-source IEEE802. 11 SDR implementation on SoC},
author={Jiao, Xianjun and Liu, Wei and Mehari, Michael and Aslam, Muhammad and Moerman, Ingrid},
booktitle={2020 IEEE 91st Vehicular Technology Conference (VTC2020-Spring)},
pages={1--2},
year={2020},
organization={IEEE}
}
```
================================================
FILE: doc/img_build_instruction/kuiper.md
================================================
**IMPORTANT pre-conditions**:
- Install Vivado 2022.2. Make sure install Vitis as well. You should have this directory: your_Xilinx_install_directory/Vitis (NOT Vitis_HLS!)
- If the Vitis is not installed, you can add it by running "Xilinx Design Tools --> Add Design Tools for Devices 2022.2" from Xilinx program group/menu in your OS start menu, or Help menu of Vivado.
- SD card at least with 16GB
- Install packages: `sudo apt install flex bison libssl-dev device-tree-compiler u-boot-tools -y`
[[Use openwifi prebuilt img](#Use-openwifi-prebuilt-img)]
[[Build SD card from scratch](#Build-SD-card-from-scratch)]
[[Use existing SD card on new board](#Use-existing-SD-card-on-new-board)]
## Use openwifi prebuilt img
Download openwifi pre-built img (see [Quick start](../../README.md#quick-start)), and extract it to .img file.
Use dd command to flash the SD card. (Or other software like Startup Disk Creator in Ubuntu)
```
sudo dd bs=512 count=31116288 if=openwifi-xyz.img of=/dev/your_sdcard_dev
```
To have correct count value, better to check the .img file actual situation by "fdisk -l img_filename" (check the number of sectors).
Then start from the 2nd step of the [Quick start](../../README.md#quick-start) in README.
## Build SD card from scratch
Download "13 December 2023 release (2022_r2)" (image_2023-12-13-ADI-Kuiper-full.zip) from https://wiki.analog.com/resources/tools-software/linux-software/kuiper-linux?redirect=1
Extract it to .img file.
Use dd command to flash the SD card. (Or other software like Startup Disk Creator in Ubuntu)
```
sudo dd bs=512 count=24182784 if=2023-12-13-ADI-Kuiper-full.img of=/dev/your_sdcard_dev
```
(To have correct count value, better to check the .img file actual situation by "fdisk -l img_filename" (check the number of sectors). While making .img from SD card, check the SD card dev instead)
Mount the BOOT and rootfs partition of SD card to your computer.
Change the SD card file: Add following into rootfs/etc/network/interfaces
```
# The loopback interface
auto lo
iface lo inet loopback
auto eth0
iface eth0 inet static
#your static IP
address 192.168.10.122
#your gateway IP
gateway 192.168.10.1
netmask 255.255.255.0
#your network address "family"
network 192.168.10.0
broadcast 192.168.10.255
```
Change the SD card file: Add following into rootfs/etc/sysctl.conf
```
net.ipv4.ip_forward=1
```
Change the SD card file: Add following into rootfs/etc/systemd/system.conf
```
DefaultTimeoutStopSec=2s
```
Put the openwifi/kernel_boot/10-network-device.rules into rootfs/etc/udev/rules.d/
Run **update_sdcard.sh** from openwifi/user_space directory to further prepare the SD card. The last argument $SDCARD_DIR of the script is the directory (mounting point) on your computer that has BOOT and rootfs directories/partitions.
The script will build and put following things into the SD card:
- Linux kernel image file ([Update Driver](../../README.md#Update-Driver)):
- adi-linux-64/arch/arm64/boot/Image (64bit)
- adi-linux/arch/arm/boot/uImage (32bit)
- devicetree file:
- openwifi/kernel_boot/boards/zcu102_fmcs2/system.dtb (64bit)
- openwifi/kernel_boot/boards/$BOARD_NAME/devicetree.dtb (32bit)
- BOOT.BIN ([Update FPGA](../../README.md#Update-FPGA)):
- openwifi/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN
- openwifi driver ([Update Driver](../../README.md#Update-Driver)).
- openwifi/user_space files and openwifi/webserver files
After **update_sdcard.sh** finishes, please do the 2nd step "Config the correct files ..." in [Quick start](../../README.md#quick-start). Then power on the board with the SD card, connect the board to your host PC (static IP 192.168.10.1) via ethernet, and ssh to the board with password **"analog"**
```
ssh root@192.168.10.122
```
Then change password to "openwifi" via "passwd" command onbard.
Enlarge the onboard SD disk space, and reboot (https://github.com/analogdevicesinc/adi-kuiper-gen/releases)
```
raspi-config --expand-rootfs
reboot now
```
Setup routing/NAT **on the PC** for your board -- this internet connection is **important** for post installation/config.
```
sudo sysctl -w net.ipv4.ip_forward=1
sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE
sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX
```
**ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet).
If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC.
Test the connectivity. Run on board (in the ssh session):
```
route add default gw 192.168.10.1
ping IP_YOU_KNOW_ON_YOUR_NETWORK
```
If there is issue with the connectivity (ping can not reach the target), it needs to be solved before going to the next step.
Do misc configurations/installations in the ssh session onboard:
```
(You might need to set correct data and time by: date -s)
sudo apt update
chmod +x /root/openwifi/*.sh
# install and setup dhcp server
sudo apt-get -y install isc-dhcp-server
cp /root/openwifi/dhcpd.conf /etc/dhcp/dhcpd.conf
# install hostapd and other useful tools
sudo apt-get -y install hostapd
sudo apt-get -y install tcpdump
sudo apt-get -y install webfs
sudo apt-get -y install iperf
sudo apt-get -y install iperf3
sudo apt-get -y install libpcap-dev
sudo apt-get -y install bridge-utils
# build on board tools
sudo apt-get -y install libnl-3-dev
sudo apt-get -y install libnl-genl-3-dev
cd /root/openwifi/sdrctl_src
make clean
make
cp sdrctl ../
cd /root/openwifi/side_ch_ctl_src/
gcc -o side_ch_ctl side_ch_ctl.c
cp side_ch_ctl ../
cd /root/openwifi/inject_80211/
make clean
make
cd ..
```
Run openwifi in the ssh session onboard:
```
/root/openwifi/setup_once.sh (Only need to run once for new board)
cd /root/openwifi
./wgd.sh
ifconfig sdr0 up
iwlist sdr0 scan
./fosdem.sh
```
## Use existing SD card on new board
Just operate the existing/working SD card of the old board on your computer starting from the 2nd step of the [Quick start](../../README.md#quick-start) in README. Then start using the SD card on the new board.
================================================
FILE: doc/known_issue/notter.md
================================================
# Known issue
- [Network issue in quick start](#Network-issue-in-quick-start)
- [EXT4 fs error rootfs issue](#EXT4-fs-error-rootfs-issue)
- [EXT4 fs error rootfs issue while booting on zcu102](#EXT4-fs-error-rootfs-issue-while-booting-on-zcu102)
- [antsdr e200 UART console](#antsdr-e200-UART-console)
- [Client can not get IP](#Client-can-not-get-IP)
- [No space left on device](#No-space-left-on-device)
- [Ping issue due to hostname resolving issue caused by DNS server change](#Ping-issue-due-to-hostname-resolving-issue-caused-by-DNS-server-change)
- [FMCOMMS board eeprom issue causes Linux crash](#FMCOMMS-board-eeprom-issue-causes-Linux-crash)
- [Not booting due to SPI flash](#Not-booting-due-to-SPI-flash)
- [Kernel compiling issue like GCC plugins](#Kernel-compiling-issue-like-GCC-plugins)
- [Missing libidn.so.11 while run boot_bin_gen.sh](#Missing-libidn.so.11-while-run-boot_bin_gen.sh)
- [Zcu102 booting kernel panic due to RTC](#Zcu102-booting-kernel-panic-due-to-RTC)
- [Kernel panic due to hardware capacitor and current load](#Kernel-panic-due-to-hardware-capacitor-and-current-load)
- [lightdm memory leakage leads to issue after long run](#lightdm-memory-leakage-leads-to-issue-after-long-run)
- [Wrong memory size on adrv9361z7035 SoM](#Wrong-memory-size-on-adrv9361z7035-SoM)
- [Unsupported PRODUCT_ID 0xFF](#Unsupported-PRODUCT_ID-0xFF)
## Network issue in quick star
- OS: Ubuntu 22 LTS
- image: [openwifi img](https://drive.google.com/file/d/1fb8eJGJAntOciCiGFVLfQs7m7ucRtSWD/view?usp=share_link)
If can't ssh to the board via Ethernet for the 1st time, you might need to delete /etc/network/interfaces.new on SD card (on your computer).
If still can't ssh the board via Ethernet, you should use UART console (/dev/ttyUSBx, /dev/ttyCH341USBx, etc.) to monitor what happened during booting.
## EXT4 fs error rootfs issue
Sometimes, the 1st booting after flashing SD card might encounter "EXT4-fs error (device mmcblk0p2): ..." error on neptunesdr, changing SD card flashing tool might solve this issue. Some tool candidates:
- gnome-disks
- Startup Disk Creator
- win32diskimager
## EXT4 fs error rootfs issue while booting on zcu102
Issue description: same SD card can boot normally on some zcu102 boards but not on some boards else.
Many reportings on internet (while booting zcu102):
```
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2)
...
---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2) ]---
```
Need to add following blocks into the mmc entry or sdhci entry of the zcu102 devicetree:
```
xlnx,has-cd = <0x1>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x1>;
disable-wp;
no-1-8-v;
broken-cd;
xlnx,mio-bank = <1>;
/* Do not run SD in HS mode from bootloader */
sdhci-caps-mask = <0 0x200000>;
sdhci-caps = <0 0>;
max-frequency = <19000000>;
```
Suspect the main reason: sdcard speed needs to be limited by above.
Might be due to that the sd card interface degrades and becomes unstable after years.
## antsdr e200 UART console
If can't see the UART console in Linux (/dev/ttyUSB0 or /dev/ttyCH341USB0), according to https://github.com/juliagoda/CH341SER, you might need to do `sudo apt remove brltty`
## Client can not get IP
If the client can not get IP from the openwifi AP, just re-run "service isc-dhcp-server restart" on board and do re-connect from the client.
## No space left on device
It might be due to too many dmesg/log/journal, disk becomes full.
```
systemd-journald[5694]: Failed to open system journal: No space left on device
```
You can try following operations.
```
systemd-tmpfiles --clean
sudo systemd-tmpfiles --remove
rm /var/log/* -rf
apt --autoremove purge rsyslog
```
Add followings into `/etc/systemd/journald.conf`
```
SystemMaxUse=64M
Storage=volatile
RuntimeMaxUse=64M
ForwardToConsole=no
ForwardToWall=no
```
## Ping issue due to hostname resolving issue caused by DNS server change
You might need to change nameserver to 8.8.8.8 in /etc/resolv.conf on board.
## FMCOMMS board eeprom issue causes Linux crash
Some FMCOMMS2/3/4/x boards shipped with wrong/empty eeprom, so that on some platform (like ZCU102) it causes issues like Linux crash. You can follow https://github.com/analogdevicesinc/fru_tools to reprogram the eeprom.
- Insert the FMCOMMS board on a platform (such as 32bit zed/zc706/zc702/etc) that can boot and boot into Linux
- On board Linux:
```
git clone https://github.com/analogdevicesinc/fru_tools.git
cd fru_tools/
make
find /sys -name eeprom
(It might return like: /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom)
fru-dump -i /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom -b
```
- If there is issue, you will see some "mismatch" warning like:
```
read 256 bytes from /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom
fru_dump 0.8.1.7, built 04Aug2022
FRU Version number mismatch 0xff should be 0x01
```
- To reprogram the eeprom (FMCOMMS4 as an example):
```
fru-dump -i ./masterfiles/AD-FMCOMMS4-EBZ-FRU.bin -o /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom
```
- Reboot the board, and try to read eeprom again, correct information should be shown like:
```
fru-dump -i /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom -b
read 256 bytes from /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-0/0-0050/eeprom
Date of Man : Mon Jul 22 20:23:00 2013
Manufacturer : Analog Devices
Product Name : AD9364 RF Eval/Software Dev Kit
Serial Number : 00045
Part Number : AD-FMCOMMS4-EBZ
FRU File ID : Empty Field
PCB Rev : C
PCB ID : FMCOMMSFMC04A
BOM Rev : 1
```
## Not booting due to SPI flash
Before loading content on SD card, the on board SPI flash controls some configurations, such as the kernel file and AD9361 crystal frequency (ad9361_ext_refclk=0x2625a8b). When (suspect) there is an issue, the SPI flash can be restored to default by interrupting booting (hitting enter before Linux loading in the UART console), then
```
Zynq> env default -a
## Resetting to default environment
Zynq> saveenv
Saving Environment to SPI Flash...
SF: Detected n25q256a with page size 256 Bytes, erase size 4 KiB, total 32 MiB
Erasing SPI flash...Writing to SPI flash...done
```
## Kernel compiling issue like GCC plugins
Sometimes after the GNU/GCC tool chain update in the host PC or the slightly kernel update (such as 5.15.0 --> 5.15.36), it might prompt user to select among some new options while compiling kernel like:
```
...
Xen guest support on ARM (XEN) [N/y/?] n
Use a unique stack canary value for each task (STACKPROTECTOR_PER_TASK) [Y/n/?] (NEW) n
*
* GCC plugins
*
GCC plugins (GCC_PLUGINS) [Y/n/?] (NEW) n
...
```
In these cases, the best/safest way is to chose **n** and **weakest** options. Otherwise the compiling might fail or potential issues might happen.
## Missing libidn.so.11 while run boot_bin_gen.sh
You might need to prepare/fake libidn.so.11 by
```
sudo ln -s /usr/lib/x86_64-linux-gnu/libidn.so.12.6.3 /usr/lib/x86_64-linux-gnu/libidn.so.11
```
Please check/confirm what is the exact **libidn.so.12.6.3** in your system.
## Zcu102 booting kernel panic due to RTC
https://github.com/open-sdr/openwifi/issues/366
## Kernel panic due to hardware capacitor and current load
https://github.com/open-sdr/openwifi/issues/457
## lightdm memory leakage leads to issue after long run
Better to disable lightdm via systemctl
## Wrong memory size on adrv9361z7035 SoM
https://github.com/open-sdr/openwifi/issues/404 reports that Linux only sees half memory size than the actual DDR memory size in the hardware.
The root cause is the old/wrong u-boot.elf hard coded the memory size as 512MB. It is already fixed to the correct 1GB (0x40000000): https://github.com/analogdevicesinc/u-boot-xlnx/blob/master/arch/arm/dts/zynq-adrv9361.dts
The solution is re-building u-boot.elf from https://github.com/analogdevicesinc/u-boot-xlnx and re-generating BOOT.BIN for adrv9361z7035 SoM.
Steps to re-build u-boot.elf for adrv9361z7035 SoM:
```
git clone https://github.com/analogdevicesinc/u-boot-xlnx.git
cd u-boot-xlnx
source environment_setting.sh (could be XILINX_DIR/Vitis/2022.2/settings64.sh or directory of your tool chain)
export ARCH=arm
export CROSS_COMPILE=arm-linux-gnueabihf-
make zynq_adrv9361_defconfig
make -j8
make u-boot.elf
```
## Unsupported PRODUCT_ID 0xFF
https://ez.analog.com/microcontroller-no-os-drivers/f/q-a/101813/ad9361-spi32766-0-ad9361_probe-unsupported-product_id-0xff/303302
https://wiki.analog.com/resources/tools-software/linux-software/fru_dump
================================================
FILE: doc/openwifi-detail.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/publications.md
================================================
If openwifi is one of your references, please cite the VTC2020 paper: [LaTex example](cite-openwifi-vtc-paper.md)
You can also cite openwifi github code: [LaTex example](cite-openwifi-github-code.md).
Publications in category:
- [Feature Functionality and System](#Feature-Functionality-and-System)
- [TSN Time Sensitive Network and RT Real Time](#TSN-Time-Sensitive-Network-and-RT-Real-Time)
- [CSI Sensing and Security](#CSI-Sensing-and-Security)
- [WiFi and Cellular 5G 6G](#WiFi-and-Cellular-5G-6G)
## Feature Functionality and System
- [Xianjun Jiao, et al. openwifi: a free and open-source IEEE802.11 SDR implementation on SoC. VTC2020 spring Antwerp](https://www.orca-project.eu/wp-content/uploads/sites/4/2020/03/openwifi-vtc-antwerp-PID1249076.pdf)
- [Cedric Den Haese, The initial 802.11n 2*2 MIMO and diversity (CSD/Combining) work. UGent master thesis 2021](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Cedric_Den_Haese_masterproef.pdf)
- [Paul Zanna, et al. A novel method for utilizing RF information from IEEE 802.11 frames in Software Defined Networks. MethodsX 2021](https://www.sciencedirect.com/science/article/pii/S2215016121003368)
- [Thijs Havinga, et al. WIP: Achieving Self-Interference-Free Operation on SDR Platform with Critical TDD Turnaround Time. WoWMoM 2022](http://hdl.handle.net/1854/LU-8765231)
- [Yingshuo Xi, Baiming Zhang. High-Throughput Open Source Viterbi Decoder for OpenWiFi. 2022 KU Leuven master thesis](https://github.com/BaimingZhang26213/viterbi_decoder)
- [Merkebu Girmay, et al. Technology recognition and traffic characterization for wireless technologies in ITS band. Vehicular Communications Volume 39, February 2023, 100563](https://doi.org/10.1016/j.vehcom.2022.100563)
- [Thijs Havinga, et al. Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis. FCCM 2023](http://hdl.handle.net/1854/LU-01H54J3830HK78ZDAH29ZEDJHY), [[Longer/detailed info about the poster](https://arxiv.org/abs/2305.13351)]
- [Merkebu Girmay, et al. Intelligent Spectrum Sharing Between LTE and Wi-Fi Networks using Muted MBSFN Subframes. WAMICON 2023](https://ieeexplore.ieee.org/abstract/document/10124903)
- [Thijs Havinga, et al. Improved TDD operation on Software-Defined Radio platforms towards future wireless standards. Computer Communications, Volume 209, 1 September 2023, Pages 178-187](https://doi.org/10.1016/j.comcom.2023.06.026)
- [Yuyang Du, et al. The Power of Large Language Models for Wireless Communication System Development: A Case Study on FPGA Platforms. arxiv, Submitted on 14 Jul 2023 (v1), last revised 5 Sep 2023 (this version, v2)](https://arxiv.org/abs/2307.07319)
- [Muhammad Aslam, et al. A novel hardware efficient design for IEEE 802.11ax compliant OFDMA transceiver](https://www.sciencedirect.com/science/article/pii/S0140366424000926?dgcid=coauthor)
- [Trio Adiono, et al. FPGA Implementation of SFO for OFDM-based Network Enabled Li-Fi System. IEEE ISCAS 2024](https://ieeexplore.ieee.org/abstract/document/10557957)
- [Trio Adiono, et al. A Scalable Design of A Full-Stack Real-Time OFDM Baseband Processor for Network-Enabled VLC Systems. IEEE Access 2024](https://ieeexplore.ieee.org/document/10589620)
- [Roni Fagerholm, FPGA-based DECT-2020 New Radio Packet Detection. Master thesis, Aalto University, 30 September 2024](https://aaltodoc.aalto.fi/server/api/core/bitstreams/a5105c46-f4c6-4034-8024-96ed9e440feb/content)
- [Hao Zhou, et al. Large Language Model (LLM) for Telecommunications: A Comprehensive Survey on Principles, Key Techniques, and Opportunities. IEEE Communications Surveys & Tutorials 2024](https://ieeexplore.ieee.org/document/10685369)
- [Thijs Havinga, et al. Experimental Study Towards Efficient Interference Avoidance Using Wi-Fi 6 OFDMA on SDR, IEEE INFOCOM 2024](https://ieeexplore.ieee.org/document/10620761)
- [Thijs Havinga, et al. Wi-Fi 6 Cross-Technology Interference Detection and Mitigation by OFDMA: an Experimental Study. EuCNC & 6G Summit 2025](http://hdl.handle.net/1854/LU-01JZ0477NE4D3DQV6R8JCCBFJB)
- [Shyam Krishnan Venkateswaran, et al. Target wake time in IEEE 802.11 WLANs: Survey, challenges, and opportunities. Computer Communications, 2025](https://www.sciencedirect.com/science/article/pii/S0140366425000842)
- [Baiheng Chen, et al. An Experimental Study of Wi-Fi Joint Transmission With Multiple Openwifi Access Points, IEEE WCNC, 2025](https://ieeexplore.ieee.org/document/10978612)
- [Maksymilian, et al. Coordinated Spatial Reuse Scheduling With Machine Learning in IEEE 802.11 MAPC Networks. arXiv 2025](https://arxiv.org/abs/2505.07278), [Slides on IEEE 802.11 standardization conf, Warsaw, 2025](https://mentor.ieee.org/802.11/dcn/25/11-25-0710-01-aiml-mapc-c-sr-scheduling-with-multi-armed-bandits-revisited.pptx)
- [Yanzhuo Yu, et al. DOA System Based on an Eight-Channel Circular Array and Wi-Fi, Proceedings of the 3rd International Conference on Internet of Things, Communication and Intelligent Technology, 27 May 2025](https://link.springer.com/chapter/10.1007/978-981-96-2767-7_37)
- [Thijs, et al. Fine-Grained Coordinated OFDMA With Fiber Backhaul Enabled by openwifi and White Rabbit, Best paper award, ACM (mobicom) WiNTECH 2025.](https://arxiv.org/abs/2507.10210)
- [Robbe Gaeremynck, et al.Openwifi and sub-20 MHz Co-OFDMA. WNG (Wireless Next Generation) SC, IEEE 802 Plenary session, Madrid, Spain, July 27 – August 1, 2025](https://mentor.ieee.org/802.11/dcn/25/11-25-1039-00-0wng-openwifi-and-sub-20-mhz-co-ofdma.pptx)
- [Thijs, et al. Cross-Technology Interference awareness for multi-user OFDMA scheduling in IEEE 802.11ax, Ad Hoc Networks, Volume 181, 104057, 1 February 2026](https://doi.org/10.1016/j.adhoc.2025.104057)
- [Yibin Shen, et al. Law: Towards Consistent Low Latency in 802.11 Home Networks, USENIX NSDI 2026](https://zilimeng.com/papers/law-nsdi26.pdf)
- [Thijs, Flexible and Real-Time Interference Mitigation Techniques for Reliable Wireless Communication Using Software-Defined Radio, PhD dissertation, Gent University, 2025](http://hdl.handle.net/1854/LU-01KC11QRHFPRGD3WA9YQFSA7RZ)
- [Holger Santillan-Carranza, et al. FPGA-Based Simulation of Open Wi-Fi Service Using the Analog Devices SDR Platform, INGENIO 9(1):26-33, January 2026](https://www.researchgate.net/publication/400217316_FPGA-Based_Simulation_of_Open_Wi-Fi_Service_Using_the_Analog_Devices_SDR_Platform)
- [Yuhao Chen et al. WiLD: Learning-based Wireless Loss Diagnosis for Congestion Control with Ultra-low Kernel Overhead, IEEE Transactions on Network and Service Management, 13 February 2026](https://ieeexplore.ieee.org/abstract/document/11396390)
## TSN Time Sensitive Network and RT Real Time
- [Jetmir Haxhibeqiri, et al. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients. ICIT2021](https://biblio.ugent.be/publication/8700714/file/8700715.pdf)
- [Ingrid Moerman, et al. Wireless Time-Sensitive Networks: When Every Microsecond Counts. Microwaves&RF, 2021](https://www.mwrf.com/technologies/systems/article/21164984/wireless-timesensitive-networks-when-every-microsecond-counts)
- [Muhammad Aslam, et al. High precision time synchronization on Wi-Fi based multi-hop network. CNERT2021](https://biblio.ugent.be/publication/8709058/file/8709060.pdf)
- [Ingrid Moerman, et al. Interoperable Time-Sensitive Networking Towards 6G (invited presentation)](https://biblio.ugent.be/publication/8719532/file/8719533.pdf)
- [Lihao Zhang, et al. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications. IEEE Internet of Things Journal, Volume: 10, Issue: 8, 15 April 2023](https://ieeexplore.ieee.org/document/9984846)
- [Jetmir Haxhibeqiri, et al. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients. 22nd IEEE International Conference on Industrial Technology (ICIT) 2021](https://ieeexplore.ieee.org/document/9453686)
- [Jetmir Haxhibeqiri, et al. Bringing Time-Sensitive Networking to Wireless Professional Private Networks. Wireless Personal Communications 2021](https://link.springer.com/article/10.1007/s11277-021-09056-0)
- [Muhammad Aslam, et al. Hardware Efficient Clock Synchronization across Wi-Fi and Ethernet Based Network Using PTP. IEEE Transactions on Industrial Informatics 2021](https://ieeexplore.ieee.org/document/9573364)
- [Zelin Yun, et al. RT-WiFi on Software-Defined Radio: Design and Implementation. RTAS 2022 paper and demo](https://ieeexplore.ieee.org/document/9804669)
- [Pablo Avila-Campos, et al. Beacon-Based Wireless TSN Association. 2022 IEEE INFOCOM](https://imec-publications.be/bitstream/handle/20.500.12860/40111/8126_acc.pdf?sequence=2)
- [Pablo Avila-Campos, et al. Impactless Beacon-Based Wireless TSN Association Procedure. 2022 IEEE 18th International Conference on Factory Communication Systems (WFCS)](https://ieeexplore.ieee.org/abstract/document/9779186)
- [Jetmir Haxhibeqiri, et al. Safety-related Applications over Wireless Time-Sensitive Networks. IEEE ETFA 2022](https://biblio.ugent.be/publication/8770625/file/8770627.pdf)
- [Pablo Avila-Campos, et al. Removing the Wires in Time-Sensitive Networks. 2022 61st FITCE International Congress Future Telecommunications: Infrastructure and Sustainability (FITCE)](https://ieeexplore.ieee.org/abstract/document/9934268)
- [Pablo Avila-Campos, et al. Periodic Control Traffic Support in a Wireless Time-Sensitive Network. 2022 13th International Conference on Network of the Future (NoF)](https://ieeexplore.ieee.org/document/9942586)
- [Gilson Miranda, et al. The Quality-Aware and Vertical-Tailored Management of Wireless Time-Sensitive Networks. IEEE Internet of Things Magazine ( Volume: 5, Issue: 4, December 2022)](https://ieeexplore.ieee.org/abstract/document/10012491)
- [Gilson Miranda, et al. Enabling Time-Sensitive Network Management Over Multi-Domain Wired/Wi-Fi Networks. IEEE Transactions on Network and Service Management, 2023)](https://ieeexplore.ieee.org/document/10121738)
- [Jetmir Haxhibeqiri, et al. To update or not: Dynamic traffic classification for high priority traffic in wireless TSN. IEEE WFCS2023](http://hdl.handle.net/1854/LU-01GZNGJFAJQRM3NX7FY5VRB4MR)
- [Pablo Avila-Campos, et al. Residual Service Time Optimization for legacy Wireless-TSN end nodes. 2023 19th International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob). p.466-471](https://ieeexplore.ieee.org/document/10187722)
- [Dirk Dahlhaus, et al. Towards Functional Safety in Dynamic Distributed Systems. Journal of Mobile Multimedia, Vol. 20 1, 1–24.](https://biblio.ugent.be/publication/01HGD7JAZY0YAQ1T13HQV35JC0/file/01HGD7PD2WRP9QW7J1G964Z6Y7.pdf)
- [Kouros Zanbour, et al. A Comprehensive Survey of Wireless Time-Sensitive Networking (TSN): Architecture, Technologies, Applications, and Open Issues. arXiv, 2 Dec 2023](https://arxiv.org/abs/2312.01204)
- [Jetmir Haxhibeqiri, et al. Coordinated Spatial Reuse for WiFi Networks: A Centralized Approach. IEEE 20th International Conference on Factory Communication Systems (WFCS) 2024](https://ieeexplore.ieee.org/document/10540785/)
- [Jetmir Haxhibeqiri, et al. Coordinated SR and Restricted TWT for Time Sensitive Applications in WiFi 7 Networks. IEEE Communications Magazine 2024](https://ieeexplore.ieee.org/document/10634074/)
- [Ozgur Ozkaya, et al. Simulating and Validating openwifi W-TSN in ns-3, IEEE 20th International Conference on Factory Communication Systems (WFCS) 2024](https://ieeexplore.ieee.org/document/10540899)
- [Pablo Avila-Campos, et al. Impactless association methods for wi-fi based time-sensitive networks. Wireless Networks Journal, 2024](https://dl.acm.org/doi/10.1007/s11276-024-03681-w)
- [Pablo Avila-Campos, et al. Unlocking Mobility for Wi-Fi-based Wireless Time-Sensitive Networks. IEEE Access, 2024](https://ieeexplore.ieee.org/document/10443947)
- [Analog Devices, AN-2597: An OFDM-Based HDL Reference Modem Using the AD936x RF Transceivers. November, 2024](https://www.analog.com/en/resources/app-notes/an-2597.html)
- [Tianyu Zhang, et al. A Survey on Industrial Internet of Things (IIoT) Testbeds for Connectivity Research. arXiv 2024](https://arxiv.org/abs/2404.17485)
- [Louis Adriaens, High-Precision Wireless Synchronization: When Wi-Fi meets UWB. IEEE/SICE International Symposium on System Integration (SII) 2025](https://ieeexplore.ieee.org/document/10870915)
- [Yongchao Dang, Open Radio Intelligent Controller based Wireless Time Sensitive Networking for Industry 5.0. TechRxiv 2025](https://www.techrxiv.org/doi/full/10.36227/techrxiv.173750009.95972083)
- [Pablo Avila-Campos, et al. Traffic Pattern-Based Scheduling for Wireless Non-TSN End Nodes. 2025 IEEE 21st International Conference on Factory Communication Systems (WFCS)](https://ieeexplore.ieee.org/document/11077621)
- [S. Xu and L. Zhang, et al. A Hybrid TDMA/CSMA Protocol for Time-Sensitive Traffic in Robot Applications. arXiv, Sep. 2025](https://arxiv.org/abs/2509.06119v1)
- [Ingrid Moerman, et al. Deterministic communications - An end-to-end system point of view (invited presentation). Symposium on Future Network/6G challenges, Future Networks World Forum 2025](http://hdl.handle.net/1854/LU-01K9YE9V3NNKFTBDBW1D09EM6A)
- [Ingrid Moerman, et al. The role of wireless in end-to-end Deterministic Connected Systems. Plenary talk at Workshop on Communication Networks and Power Systems, 28 Nov. 2025 (WCNPS’25)](http://hdl.handle.net/1854/LU-01KBCXDFS273CRGHB8TZTS8YB8)
- [Jetmir Haxhibeqiri, et al. Distributed Multi-link Operation (MLO) for Frame Replication in Wireless Time-Sensitive Networking. The 8th International Conference on Advanced Communication Technologies and Networking (CommNet) 2025](https://ieeexplore.ieee.org/abstract/document/11288880)
## CSI Sensing and Security
- [Marco Cominelli, et al. CSI MURDER. ORCA project opencall 2019](https://ans.unibs.it/projects/csi-murder/)
- [Marco Cominelli, et al. IEEE 802.11 CSI randomization to preserve location privacy: An empirical evaluation in different scenarios. ELSEVIER Computer Networks, 2021](https://www.sciencedirect.com/science/article/abs/pii/S138912862100102X)
- [Xianjun Jiao, et al. Openwifi CSI fuzzer for authorized sensing and covert channels. ACM WiSec 2021](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)
- [Hongjian Cao, et al. OWFuzz: WiFi Protocol Fuzzing Tool Based on OpenWiFi. Blackhat asia 2021](https://www.blackhat.com/asia-21/arsenal/schedule/#owfuzz-wifi-protocol-fuzzing-tool-based-on-openwifi-22569), [[**code**]](https://github.com/alipay/Owfuzz)
- [Steven Heijse, IEEE 802.11 Physical Layer Fuzzing Using OpenWifi. UGent master thesis 2021](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Steven_Heijse_masterproef.pdf)
- [Jasper Devreker, Developing IEEE 802.11 PHY fuzzing capabilities using the open source Openwifi project. UGent master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Jasper_Devreker_masterproef.pdf)
- [Thomas Schuddinck, Cybersecurity: Breaking IEEE 802.11 Devices at the Physical Layer. UGent master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thomas_Schuddinck_masterproef.pdf)
- [Seppe Dejonckheere, The design of a CSI sensing authorisation mechanism using the open source Openwifi project. UGnet master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Seppe_Dejonckheere_masterproef.pdf)
- [Marco Cominelli, et al. On the properties of device-free multi-point CSI localization and its obfuscation. ELSEVIER Computer Communications, 2022](https://www.sciencedirect.com/science/article/pii/S014036642200086X)
- [Renato Lo Cigno, et al. Integrating CSI Sensing in Wireless Networks: Challenges to Privacy and Countermeasures. IEEE Network, 2022](https://ieeexplore.ieee.org/document/9919763)
- [Renato Lo Cigno, et al. AntiSense: Standard-compliant CSI obfuscation against unauthorized Wi-Fi sensing. ELSEVIER Computer Communications, 2022](https://www.sciencedirect.com/science/article/pii/S0140366421004916)
- [Mathy Vanhoef, et al. Testing and Improving the Correctness of Wi-Fi Frame Injection. ACM WiSec 2023](https://papers.mathyvanhoef.com/wisec2023-wifi-injection.pdf)
- [Wen Liu, et al. A New Paradigm for Device-free Indoor Localization: Deep Learning with Error Vector Spectrum in Wi-Fi Systems. PIMRC 2023](https://arxiv.org/pdf/2304.06490.pdf)
- [Paul Zanna, et al. Preventing Attacks on Wireless Networks Using SDN Controlled OODA Loops and Cyber Kill Chains. Sensors 2022, 22(23), 9481](https://www.mdpi.com/1986552)
- [Hayoung Seong, et al. Practical Covert Wireless Unidirectional Communication in IEEE 802.11 Environment, IEEE Internet of Things Journal ( Volume: 10, Issue: 2, 15 January 2023)](https://ieeexplore.ieee.org/abstract/document/9881568)
- [Fan Qi, et al. Deep Learning-based CSI Feedback in Wi-Fi Systems, arxiv, 2024](https://arxiv.org/pdf/2407.05905)
- [Lorenzo Ghiro, et al. Wi-Fi Localization Obfuscation: An implementation in openwifi. ELSEVIER Computer Communications, 2023](http://www.sciencedirect.com/science/article/pii/S0140366423001111)
- [Andreas Toftegaard Kristensen, et al. Monostatic Multi-Target Wi-Fi-Based Breathing Rate Sensing Using Openwifi, IEEE Wireless Communications and Networking Conference (WCNC) 2024](https://ieeexplore.ieee.org/document/10570912)
- [Andreas Toftegaard Kristensen, et al. An SDR-Based Monostatic Wi-Fi System with Analog Self-Interference Cancellation for Sensing, arXiv, 11 DEC 2024](https://arxiv.org/abs/2412.08612) [[**block diagram**](AnSIC-sensing-correction.png)]
- [Jesus A. Armenta-Garcia, et al. Wireless sensing applications with Wi-Fi Channel State Information, preprocessing techniques, and detection algorithms: A survey. Computer Communications Volume 224, 1 August 2024](https://www.sciencedirect.com/science/article/abs/pii/S0140366424002214?via%3Dihub)
- [Tianyang Zhang, et al. Privacy Protection in WiFi Sensing via CSI Fuzzing, 2024 IEEE/ACM Symposium on Edge Computing (SEC), 04-07 December 2024](https://ieeexplore.ieee.org/abstract/document/10818006)
- [Xianjun Jiao, et al. Single-Input-Multiple-Output Wi-Fi Radar for Vital Signal Sensing and Device Tracking, IEEE 5th International Symposium on Joint Communications & Sensing (JC&S) 2025](https://biblio.ugent.be/publication/01JMVPSR8AR08RRW9MC15FPF58)
- [Renato Lo Cigno, et al. Communication and Sensing: Wireless PHY-Layer Threats to Security and Privacy for IoT Systems and Possible Countermeasures. information, MDPI, 2025](https://www.mdpi.com/2078-2489/16/1/31)
- [Zhiming Chu, et al. Defeating CSI obfuscation mechanisms: A study on unauthorized Wi-Fi Sensing in wireless sensor network. Computer Networks, Volume 263, May 2025](https://www.sciencedirect.com/science/article/abs/pii/S1389128625001768)
- [Xinyu Liu, et al. Integration of Person Identification and Respiratory Monitoring Based on Reconfigurable Intelligent Surface. IEEE Sensors Journal, 06 June 2025](https://ieeexplore.ieee.org/abstract/document/11027648)
- [Zhiming Chu, et al. Privacy-preserving WiFi sensing in WSNs via CSI obfuscation. Computers & Security Volume 157, October 2025, 104594](https://doi.org/10.1016/j.cose.2025.104594)
- [Stepan Mazokha, et al. Real-time Device Fingerprinting and Re-identification in GNUradio, Proceedings of the 15th GNU Radio Conference, 2025](https://events.gnuradio.org/event/26/contributions/773/attachments/229/665/gr-mobrffi_paper_v1.2.pdf)
## WiFi and Cellular 5G 6G
- [Luca Baldesi, et al. ChARM: NextG Spectrum Sharing Through Data-Driven Real-Time O-RAN Dynamic Control. INFOCOM 2022](https://ece.northeastern.edu/wineslab/papers/BaldesiInfocom22.pdf)
- [Christian Arendt, et al. Empowering the Convergence of Wi-Fi and 5G for Future Private 6G Networks. 28th European Wireless Conference 2023](https://ieeexplore.ieee.org/document/10461434)
- [Liangdong Wei, et al. An Experimental Evaluation of ACK-based Passive Bandwidth Estimation Methods in Ad Hoc Networks, 9th International Conference on Computer and Communications (ICCC) 2023](https://ieeexplore.ieee.org/document/10507541)
**Openwifi was born in ORCA project (EU's Horizon2020 programme under agreement number 732174).**
================================================
FILE: doc/rf-digital-if-chain-config.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/rf-digital-if-chain-spectrum.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: doc/videos.md
================================================
- The 1st public demo video [[Youtube](https://youtu.be/NpjEaszd5u4)], [[link for CHN user](https://www.zhihu.com/zvideo/1280659393378041856)]
- FOSDEM2020 presentation [[Youtube](https://youtu.be/Mq48cGthk7M)], [[link for CHN user](https://www.zhihu.com/zvideo/1280673506397425664)]
- Low latency for gaming and general introduction [[Youtube](https://youtu.be/Notn9X482LI)], [[link for CHN user](https://www.zhihu.com/zvideo/1273823153371385856)]
- CSI (Channel State Information) [[Youtube](https://youtu.be/DanB1ClVamU)], [[link for CHN user](https://www.zhihu.com/zvideo/1297662571618148352)]
- FOSDEM2021 presentation [[Flash back](https://twitter.com/jxjputaoshu/status/1358462741703491584?s=20)], [[link for CHN user](https://www.zhihu.com/zvideo/1340748826311974912)]; [[Presentation](https://video.fosdem.org/2021/D.radio/fsr_openwifi_opensource_wifi_chip.webm)], [[link for CHN user](https://www.zhihu.com/zvideo/1345036055104360448)]
- FSF Libreplanet 2021 presentation [[Official](https://media.libreplanet.org/u/libreplanet/m/openwifi-project-the-dawn-of-the-free-libre-wifi-chip/)], [[LinuxReviews](https://linuxreviews.org/Openwifi_project:_The_dawn_of_the_free/libre_WiFi_chip)], [[link for CHN user](https://www.zhihu.com/zvideo/1373649688906883072)]
- Openwifi industrial real-time high reliable low latency applications (EU Horizon 2020 SHOP4CF project) [[Youtube](https://youtu.be/p7zkkdMvPNc)], [[link for CHN user](https://www.zhihu.com/zvideo/1378413483944538113)]
- WiFi CSI Radar: Joint communication and sensing [[Youtube](https://youtu.be/PUwpJuHZDhg)], [[link for CHN user](https://www.bilibili.com/video/BV1a94y1W7XL/?share_source=copy_web&vd_source=587e4ed61021396d31fd3a09c077969f)]
- CSI fuzzer [[Youtube](https://youtu.be/aOPYwT77Qdw)], [[link for CHN user](https://www.zhihu.com/zvideo/1378409348163506177)], and ACM WiSec interview [[Youtube](https://youtu.be/ZOCV78aTaQg)], [[link for CHN user](https://www.bilibili.com/video/BV1Mo4y1C76t?share_source=copy_web)]
- NGI zero, nlnet online session on future of European open hardware [[Session](https://nlnet.nl/news/2021/20210507-NGI-Zero-workshop-open-hardware.html)], [[Original record](https://archive.org/details/ngiforum-open-hardware-workshop-ngizero)], [[Youtube](https://youtu.be/m9Tw5VuHAfk)], [[link for CHN user](https://www.zhihu.com/zvideo/1379302398096285696)]
- High Precision Time Synchronization on Wi-Fi based Multi-Hop Network [[Youtube](https://youtu.be/m5ryRArbdC8)], [[link for CHN user](https://www.zhihu.com/zvideo/1418222775224492032)]
- FOSDEM2022 presentation [[Presentation](https://video.fosdem.org/2022/D.radio/radio_openwifi.webm)], [[link for CHN user](https://www.bilibili.com/video/BV12b4y1j7YK?share_source=copy_web)]
- [Find the corresponding Wi-Fi packet in wireshark after openwifi CSI/IQ capture](https://github.com/open-sdr/openwifi/discussions/344) [[Youtube](https://youtu.be/iiiINz7XTGA)], [[link for CHN user](https://www.bilibili.com/video/BV13w411Y7GX/?share_source=copy_web&vd_source=587e4ed61021396d31fd3a09c077969f)]
- CCC GPN22 DanielAW, How a Wifi chip works internally [[link](https://media.ccc.de/v/gpn22-380-how-a-wifi-chip-works-internally)]
- FSiC2024, An opensource Wi-Fi chip, What, Why and How? [[link](https://wiki.f-si.org/index.php?title=An_opensource_Wi-Fi_chip,_What,_Why_and_How%3F)]
================================================
FILE: driver/Makefile
================================================
# Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += sdr.o openofdm_rx/openofdm_rx.o openofdm_tx/openofdm_tx.o tx_intf/tx_intf.o rx_intf/rx_intf.o xpu/xpu.o
all:
make -C $(KDIR) M=$(PWD) modules
# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
================================================
FILE: driver/hw_def.h
================================================
// Author: Xianjun jiao, Michael Mehari, Wei Liu
// SPDX-FileCopyrightText: 2019 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
// #ifndef __HW_DEF_H_FILE__
// #define __HW_DEF_H_FILE__
const char *sdr_compatible_str = "sdr,sdr";
enum openwifi_hardware_type {
ZYNQ_AD9361 = 0,
ZYNQMP_AD9361 = 1,
RFSOC4X2 = 2,
UNKNOWN_HARDWARE,
};
enum openwifi_fpga_type {
SMALL_FPGA = 0,
LARGE_FPGA = 1,
};
//we choose 3822=(5160+2484)/2 for calibration to avoid treating 5140 as 2.4GHz
#define OPENWIFI_FREQ_MHz_TH_FOR_2_4GHZ_5GHZ 3822
enum openwifi_band {
BAND_900M = 0,
BAND_2_4GHZ,
BAND_3_65GHZ,
BAND_5_0GHZ,
//use this BAND_5_8GHZ to represent all frequencies above OPENWIFI_FREQ_TH_FOR_2_4GHZ_5GHZ
BAND_5_8GHZ,
BAND_5_9GHZ,
BAND_60GHZ,
};
// ------------------------------------tx interface----------------------------------------
const char *tx_intf_compatible_str = "sdr,tx_intf";
#define TX_INTF_REG_MULTI_RST_ADDR (0*4)
#define TX_INTF_REG_ARBITRARY_IQ_ADDR (1*4)
#define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4)
#define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4)
#define TX_INTF_REG_CSI_FUZZER_ADDR (5*4)
#define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4)
#define TX_INTF_REG_ARBITRARY_IQ_CTL_ADDR (7*4)
#define TX_INTF_REG_TX_CONFIG_ADDR (8*4)
#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4)
#define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4)
#define TX_INTF_REG_S_AXIS_FIFO_TH_ADDR (11*4)
#define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR (12*4)
#define TX_INTF_REG_BB_GAIN_ADDR (13*4)
#define TX_INTF_REG_INTERRUPT_SEL_ADDR (14*4)
#define TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR (15*4)
#define TX_INTF_REG_ANT_SEL_ADDR (16*4)
#define TX_INTF_REG_PHY_HDR_CONFIG_ADDR (17*4)
#define TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR (21*4)
#define TX_INTF_REG_PKT_INFO1_ADDR (22*4)
#define TX_INTF_REG_PKT_INFO2_ADDR (23*4)
#define TX_INTF_REG_PKT_INFO3_ADDR (24*4)
#define TX_INTF_REG_PKT_INFO4_ADDR (25*4)
#define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR (26*4)
#define TX_INTF_NUM_ANTENNA 2
#define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8)
#define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3
enum tx_intf_mode {
TX_INTF_AXIS_LOOP_BACK = 0,
TX_INTF_BYPASS,
TX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
TX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH,
TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
};
const int tx_intf_fo_mapping[] = {0, 0, 0, 0, 0, -10, 10, -10, 10};
const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v
struct tx_intf_driver_api {
u32 (*hw_init)(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
u32 (*TX_INTF_REG_MULTI_RST_read)(void);
u32 (*TX_INTF_REG_ARBITRARY_IQ_read)(void);
u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void);
u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void);
u32 (*TX_INTF_REG_CSI_FUZZER_read)(void);
u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void);
u32 (*TX_INTF_REG_ARBITRARY_IQ_CTL_read)(void);
u32 (*TX_INTF_REG_TX_CONFIG_read)(void);
u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void);
u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void);
u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void);
u32 (*TX_INTF_REG_AMPDU_ACTION_CONFIG_read)(void);
u32 (*TX_INTF_REG_BB_GAIN_read)(void);
u32 (*TX_INTF_REG_ANT_SEL_read)(void);
u32 (*TX_INTF_REG_PHY_HDR_CONFIG_read)(void);
u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void);
u32 (*TX_INTF_REG_PKT_INFO1_read)(void);
u32 (*TX_INTF_REG_PKT_INFO2_read)(void);
u32 (*TX_INTF_REG_PKT_INFO3_read)(void);
u32 (*TX_INTF_REG_PKT_INFO4_read)(void);
u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void);
void (*TX_INTF_REG_MULTI_RST_write)(u32 value);
void (*TX_INTF_REG_ARBITRARY_IQ_write)(u32 value);
void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value);
void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value);
void (*TX_INTF_REG_CSI_FUZZER_write)(u32 value);
void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value);
void (*TX_INTF_REG_ARBITRARY_IQ_CTL_write)(u32 value);
void (*TX_INTF_REG_TX_CONFIG_write)(u32 value);
void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value);
void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value);
void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value);
void (*TX_INTF_REG_AMPDU_ACTION_CONFIG_write)(u32 value);
void (*TX_INTF_REG_BB_GAIN_write)(u32 value);
void (*TX_INTF_REG_ANT_SEL_write)(u32 value);
void (*TX_INTF_REG_PHY_HDR_CONFIG_write)(u32 value);
void (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write)(u32 value);
void (*TX_INTF_REG_PKT_INFO1_write)(u32 value);
void (*TX_INTF_REG_PKT_INFO2_write)(u32 value);
void (*TX_INTF_REG_PKT_INFO3_write)(u32 value);
void (*TX_INTF_REG_PKT_INFO4_write)(u32 value);
};
// ------------------------------------rx interface----------------------------------------
const char *rx_intf_compatible_str = "sdr,rx_intf";
#define RX_INTF_REG_MULTI_RST_ADDR (0*4)
#define RX_INTF_REG_MIXER_CFG_ADDR (1*4)
#define RX_INTF_REG_INTERRUPT_TEST_ADDR (2*4)
#define RX_INTF_REG_IQ_SRC_SEL_ADDR (3*4)
#define RX_INTF_REG_IQ_CTRL_ADDR (4*4)
#define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4)
#define RX_INTF_REG_START_TRANS_TO_PS_ADDR (6*4)
#define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4)
#define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4)
#define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4)
#define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4)
#define RX_INTF_REG_BB_GAIN_ADDR (11*4)
#define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR (12*4)
#define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR (13*4)
#define RX_INTF_REG_ANT_SEL_ADDR (16*4)
#define RX_INTF_NUM_ANTENNA 2
#define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8)
#define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3
enum rx_intf_mode {
RX_INTF_AXIS_LOOP_BACK = 0,
RX_INTF_BYPASS,
RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
RX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
};
const int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10};
struct rx_intf_driver_api {
u32 io_start;
u32 base_addr;
u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
u32 (*RX_INTF_REG_MULTI_RST_read)(void);
u32 (*RX_INTF_REG_MIXER_CFG_read)(void);
u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void);
u32 (*RX_INTF_REG_IQ_CTRL_read)(void);
u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void);
u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void);
u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
u32 (*RX_INTF_REG_ANT_SEL_read)(void);
u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void);
void (*RX_INTF_REG_MULTI_RST_write)(u32 value);
void (*RX_INTF_REG_MIXER_CFG_write)(u32 value);
void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
void (*RX_INTF_REG_IQ_CTRL_write)(u32 value);
void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value);
void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value);
void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
void (*RX_INTF_REG_BB_GAIN_write)(u32 value);
void (*RX_INTF_REG_ANT_SEL_write)(u32 value);
void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value);
void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value);
void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value);
void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value);
};
// ----------------------------------openofdm rx-------------------------------
const char *openofdm_rx_compatible_str = "sdr,openofdm_rx";
#define OPENOFDM_RX_REG_MULTI_RST_ADDR (0*4)
#define OPENOFDM_RX_REG_ENABLE_ADDR (1*4)
#define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4)
#define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4)
#define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4)
#define OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR (5*4)
#define OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_ADDR (18*4)
#define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4)
enum openofdm_rx_mode {
OPENOFDM_RX_TEST = 0,
OPENOFDM_RX_NORMAL,
};
#define OPENOFDM_RX_POWER_THRES_INIT 124
// Above 118 is based on these test result (2022-03-09)
// FMCOMMS3
// 2437M
// 11a/g BPSK 6M, Rx sensitivity level dmesg report -85dBm
// priv->rssi_correction = 153; rssi_half_db/2 = 153-85=68; rssi_half_db = 136
// 5180M
// 11a/g BPSK 6m, Rx sensitivity level dmesg report -84dBm
// priv->rssi_correction = 145; rssi_half_db/2 = 145-84=61; rssi_half_db = 122
// 5320M
// 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm
// priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124
// FMCOMMS2
// 2437M
// 11a/g BPSK 6M, Rx sensitivity level dmesg report -80dBm
// priv->rssi_correction = 153; rssi_half_db/2 = 153-80=73; rssi_half_db = 146
// 5180M
// 11a/g BPSK 6m, Rx sensitivity level dmesg report -83dBm
// priv->rssi_correction = 145; rssi_half_db/2 = 145-83=62; rssi_half_db = 124
// 5320M
// 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm
// priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124
// #define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-85) //-85 will remove lots of false alarm. the best openwifi reported sensitivity is like -90/-92 (set it manually if conductive test with wifi tester)
#define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-95) //due to performance is much better (can work around -90dBm), lower it from -85dBm to -95dBm
#define OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT 64
#define OPENOFDM_RX_MIN_PLATEAU_INIT 100
#define OPENOFDM_RX_FFT_WIN_SHIFT_INIT 4
#define OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH 48
#define OPENOFDM_RX_PHASE_OFFSET_ABS_TH 11
#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf
#define OPENWIFI_MIN_SIGNAL_LEN_TH 14 //Packet shorter than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf
//due to CRC32, at least 4 bytes needed to push out expected CRC result
struct openofdm_rx_driver_api {
u32 (*hw_init)(enum openofdm_rx_mode mode);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void);
void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value);
void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value);
void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value);
void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value);
void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value);
void (*OPENOFDM_RX_REG_FFT_WIN_SHIFT_write)(u32 value);
void (*OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write)(u32 value);
};
// ---------------------------------------openofdm tx-------------------------------
const char *openofdm_tx_compatible_str = "sdr,openofdm_tx";
#define OPENOFDM_TX_REG_MULTI_RST_ADDR (0*4)
#define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR (1*4)
#define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR (2*4)
enum openofdm_tx_mode {
OPENOFDM_TX_TEST = 0,
OPENOFDM_TX_NORMAL,
};
struct openofdm_tx_driver_api {
u32 (*hw_init)(enum openofdm_tx_mode mode);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value);
void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value);
void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value);
};
// ---------------------------------------xpu low MAC controller-------------------------------
// extra filter flag together with enum ieee80211_filter_flags in mac80211.h
#define UNICAST_FOR_US (1<<9)
#define BROADCAST_ALL_ONE (1<<10)
#define BROADCAST_ALL_ZERO (1<<11)
#define MY_BEACON (1<<12)
#define MONITOR_ALL (1<<13)
const char *xpu_compatible_str = "sdr,xpu";
#define XPU_REG_MULTI_RST_ADDR (0*4)
#define XPU_REG_SRC_SEL_ADDR (1*4)
#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4)
#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4)
#define XPU_REG_BAND_CHANNEL_ADDR (4*4)
#define XPU_REG_DIFS_ADVANCE_ADDR (5*4)
#define XPU_REG_FORCE_IDLE_MISC_ADDR (6*4)
#define XPU_REG_RSSI_DB_CFG_ADDR (7*4)
#define XPU_REG_LBT_TH_ADDR (8*4)
#define XPU_REG_CSMA_DEBUG_ADDR (9*4)
#define XPU_REG_BB_RF_DELAY_ADDR (10*4)
#define XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR (11*4)
#define XPU_REG_AMPDU_ACTION_ADDR (12*4)
#define XPU_REG_SPI_DISABLE_ADDR (13*4)
#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4)
#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4)
#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4)
#define XPU_REG_CSMA_CFG_ADDR (19*4)
#define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4)
#define XPU_REG_SLICE_COUNT_START_ADDR (21*4)
#define XPU_REG_SLICE_COUNT_END_ADDR (22*4)
#define XPU_REG_CTS_TO_RTS_CONFIG_ADDR (26*4)
#define XPU_REG_FILTER_FLAG_ADDR (27*4)
#define XPU_REG_BSSID_FILTER_LOW_ADDR (28*4)
#define XPU_REG_BSSID_FILTER_HIGH_ADDR (29*4)
#define XPU_REG_MAC_ADDR_LOW_ADDR (30*4)
#define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4)
#define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4)
#define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4)
#define XPU_REG_MAC_ADDR_READ_BACK_ADDR (62*4)
#define XPU_REG_FPGA_GIT_REV_ADDR (63*4)
enum xpu_mode {
XPU_TEST = 0,
XPU_NORMAL,
};
struct xpu_driver_api {
u32 (*hw_init)(enum xpu_mode mode);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
void (*XPU_REG_MULTI_RST_write)(u32 value);
u32 (*XPU_REG_MULTI_RST_read)(void);
void (*XPU_REG_SRC_SEL_write)(u32 value);
u32 (*XPU_REG_SRC_SEL_read)(void);
void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value);
u32 (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void);
void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value);
u32 (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void);
void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value);
u32 (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void);
void (*XPU_REG_ACK_FC_FILTER_write)(u32 value);
u32 (*XPU_REG_ACK_FC_FILTER_read)(void);
void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value);
u32 (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void);
void (*XPU_REG_FILTER_FLAG_write)(u32 value);
u32 (*XPU_REG_FILTER_FLAG_read)(void);
void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value);
u32 (*XPU_REG_MAC_ADDR_LOW_read)(void);
void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value);
u32 (*XPU_REG_MAC_ADDR_HIGH_read)(void);
void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value);
u32 (*XPU_REG_BSSID_FILTER_LOW_read)(void);
void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value);
u32 (*XPU_REG_BSSID_FILTER_HIGH_read)(void);
void (*XPU_REG_BAND_CHANNEL_write)(u32 value);
u32 (*XPU_REG_BAND_CHANNEL_read)(void);
void (*XPU_REG_DIFS_ADVANCE_write)(u32 value);
u32 (*XPU_REG_DIFS_ADVANCE_read)(void);
void (*XPU_REG_FORCE_IDLE_MISC_write)(u32 value);
u32 (*XPU_REG_FORCE_IDLE_MISC_read)(void);
u32 (*XPU_REG_TRX_STATUS_read)(void);
u32 (*XPU_REG_TX_RESULT_read)(void);
u32 (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void);
u32 (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void);
void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value);
void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value);
void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value);
u32 (*XPU_REG_FC_DI_read)(void);
u32 (*XPU_REG_ADDR1_LOW_read)(void);
u32 (*XPU_REG_ADDR1_HIGH_read)(void);
u32 (*XPU_REG_ADDR2_LOW_read)(void);
u32 (*XPU_REG_ADDR2_HIGH_read)(void);
void (*XPU_REG_LBT_TH_write)(u32 value);
u32 (*XPU_REG_LBT_TH_read)(void);
void (*XPU_REG_RSSI_DB_CFG_write)(u32 value);
u32 (*XPU_REG_RSSI_DB_CFG_read)(void);
void (*XPU_REG_CSMA_DEBUG_write)(u32 value);
u32 (*XPU_REG_CSMA_DEBUG_read)(void);
void (*XPU_REG_CSMA_CFG_write)(u32 value);
u32 (*XPU_REG_CSMA_CFG_read)(void);
void (*XPU_REG_SLICE_COUNT_TOTAL_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_START_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_END_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value);
u32 (*XPU_REG_SLICE_COUNT_TOTAL_read)(void);
u32 (*XPU_REG_SLICE_COUNT_START_read)(void);
u32 (*XPU_REG_SLICE_COUNT_END_read)(void);
u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void);
u32 (*XPU_REG_SLICE_COUNT_START1_read)(void);
u32 (*XPU_REG_SLICE_COUNT_END1_read)(void);
void (*XPU_REG_BB_RF_DELAY_write)(u32 value);
void (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write)(u32 value);
u32 (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read)(void);
void (*XPU_REG_SPI_DISABLE_write)(u32 value);
u32 (*XPU_REG_SPI_DISABLE_read)(void);
void (*XPU_REG_AMPDU_ACTION_write)(u32 value);
u32 (*XPU_REG_AMPDU_ACTION_read)(void);
void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);
};
// #endif
================================================
FILE: driver/make_all.sh
================================================
#!/bin/bash
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
print_usage () {
echo "You must enter at least 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)"
echo "Further arguments (maximum 5) will be converted to #define argument in pre_def.h"
echo " "
}
print_usage
if [ "$#" -lt 2 ]; then
exit 1
fi
OPENWIFI_DIR=$(pwd)/../
XILINX_DIR=$1
ARCH_OPTION=$2
echo OPENWIFI_DIR $OPENWIFI_DIR
echo XILINX_DIR $XILINX_DIR
echo ARCH_OPTION $ARCH_OPTION
if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
echo "\$OPENWIFI_DIR is found!"
else
echo "\$OPENWIFI_DIR is not correct. Please check!"
exit 1
fi
if [ -d "$XILINX_DIR/Vitis" ]; then
echo "\$XILINX_DIR is found!"
else
echo "\$XILINX_DIR is not correct. Please check!"
exit 1
fi
if [ "$ARCH_OPTION" != "32" ] && [ "$ARCH_OPTION" != "64" ]; then
echo "\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!"
exit 1
else
echo "\$ARCH_OPTION is valid!"
fi
XILINX_ENV_FILE=$XILINX_DIR/Vitis/2022.2/settings64.sh
echo "Expect env file $XILINX_ENV_FILE"
if [ -f "$XILINX_ENV_FILE" ]; then
echo "$XILINX_ENV_FILE is found!"
else
echo "$XILINX_ENV_FILE is not correct. Please check!"
exit 1
fi
echo "#define USE_NEW_RX_INTERRUPT 1" > pre_def.h
if [[ -n $3 ]]; then
DEFINE1=$3
echo DEFINE1 $DEFINE1
echo "#define $DEFINE1" >> pre_def.h
fi
if [[ -n $4 ]]; then
DEFINE2=$4
echo DEFINE2 $DEFINE2
echo "#define $DEFINE2" >> pre_def.h
fi
if [[ -n $5 ]]; then
DEFINE3=$5
echo DEFINE3 $DEFINE3
echo "#define $DEFINE3" >> pre_def.h
fi
if [[ -n $6 ]]; then
DEFINE4=$6
echo DEFINE4 $DEFINE4
echo "#define $DEFINE4" >> pre_def.h
fi
if [[ -n $7 ]]; then
DEFINE5=$7
echo DEFINE5 $DEFINE5
echo "#define $DEFINE5" >> pre_def.h
fi
source $XILINX_ENV_FILE
if [ "$ARCH_OPTION" == "64" ]; then
LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/
ARCH="arm64"
CROSS_COMPILE="aarch64-linux-gnu-"
else
LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux/
ARCH="arm"
CROSS_COMPILE="arm-linux-gnueabihf-"
fi
# check if user entered the right path to analog device linux
if [ -d "$LINUX_KERNEL_SRC_DIR" ]; then
echo "setup linux kernel path ${LINUX_KERNEL_SRC_DIR}"
else
echo "Error: path to adi linux: ${LINUX_KERNEL_SRC_DIR} not found. Can not continue."
exit 1
fi
set -x
home_dir=$(pwd)
cd $OPENWIFI_DIR/driver/
if git log -1; then
echo "#define GIT_REV 0x"$(git log -1 --pretty=%h) > git_rev.h
else
echo "#define GIT_REV 0xFFFFFFFF" > git_rev.h
fi
cd $OPENWIFI_DIR/driver/openofdm_tx
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $OPENWIFI_DIR/driver/openofdm_rx
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $OPENWIFI_DIR/driver/tx_intf
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $OPENWIFI_DIR/driver/rx_intf
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $OPENWIFI_DIR/driver/xpu
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
# cd $OPENWIFI_DIR/driver/ad9361
# make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $OPENWIFI_DIR/driver/side_ch
./make_driver.sh $XILINX_DIR $ARCH_OPTION
cd $OPENWIFI_DIR/driver/
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $home_dir
================================================
FILE: driver/openofdm_rx/Makefile
================================================
# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += openofdm_rx.o
all:
make -C $(KDIR) M=$(PWD) modules
# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
================================================
FILE: driver/openofdm_rx/openofdm_rx.c
================================================
/*
* Author: Xianjun jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline u32 OPENOFDM_RX_REG_STATE_HISTORY_read(void){
return reg_read(OPENOFDM_RX_REG_STATE_HISTORY_ADDR);
}
static inline void OPENOFDM_RX_REG_MULTI_RST_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_MULTI_RST_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_ENABLE_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_ENABLE_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_POWER_THRES_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_SOFT_DECODING_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_FFT_WIN_SHIFT_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_ADDR, Data);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,openofdm_rx", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct openofdm_rx_driver_api openofdm_rx_driver_api_inst;
struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst;
EXPORT_SYMBOL(openofdm_rx_api);
static inline u32 hw_init(enum openofdm_rx_mode mode){
int err=0, i;
printk("%s hw_init mode %d\n", openofdm_rx_compatible_str, mode);
switch(mode)
{
case OPENOFDM_RX_TEST:
{
printk("%s hw_init mode OPENOFDM_RX_TEST\n", openofdm_rx_compatible_str);
break;
}
case OPENOFDM_RX_NORMAL:
{
printk("%s hw_init mode OPENOFDM_RX_NORMAL\n", openofdm_rx_compatible_str);
break;
}
default:
{
printk("%s hw_init mode %d is wrong!\n", openofdm_rx_compatible_str, mode);
err=1;
}
}
printk("%s hw_init input: power_thres %d dc_running_sum_th %d min_plateau %d\n", openofdm_rx_compatible_str, OPENOFDM_RX_POWER_THRES_INIT, OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT, OPENOFDM_RX_MIN_PLATEAU_INIT);
// 1) power threshold configuration and reset
openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write(1); //bit1 of slv_reg1: force ht smoothing to have better sensitivity
// Remove OPENOFDM_RX_REG_POWER_THRES_write to avoid hw_init call in openwifi_start causing inconsistency
// openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT);
openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold
openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write((OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH<<4)|OPENOFDM_RX_FFT_WIN_SHIFT_INIT);
openofdm_rx_api->OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write(OPENOFDM_RX_PHASE_OFFSET_ABS_TH);
//rst
for (i=0;i<8;i++)
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);
for (i=0;i<32;i++)
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
for (i=0;i<8;i++)
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);
printk("%s hw_init err %d\n", openofdm_rx_compatible_str, err);
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", openofdm_rx_compatible_str);
err = 0;
}
}
if (err)
return err;
openofdm_rx_api->hw_init=hw_init;
openofdm_rx_api->reg_read=reg_read;
openofdm_rx_api->reg_write=reg_write;
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write=OPENOFDM_RX_REG_MULTI_RST_write;
openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write;
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write;
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write;
openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write;
openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write=OPENOFDM_RX_REG_FFT_WIN_SHIFT_write;
openofdm_rx_api->OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write=OPENOFDM_RX_REG_PHASE_OFFSET_ABS_TH_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_rx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr);
printk("%s dev_probe openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst);
printk("%s dev_probe openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api);
printk("%s dev_probe succeed!\n", openofdm_rx_compatible_str);
err = hw_init(OPENOFDM_RX_NORMAL);
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr);
printk("%s dev_remove openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst);
printk("%s dev_remove openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api);
printk("%s dev_remove succeed!\n", openofdm_rx_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,openofdm_rx",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,openofdm_rx");
MODULE_LICENSE("GPL v2");
================================================
FILE: driver/openofdm_tx/Makefile
================================================
# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += openofdm_tx.o
all:
make -C $(KDIR) M=$(PWD) modules
# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
================================================
FILE: driver/openofdm_tx/openofdm_tx.c
================================================
/*
* axi lite register access driver
* Author: Xianjun jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline void OPENOFDM_TX_REG_MULTI_RST_write(u32 Data) {
reg_write(OPENOFDM_TX_REG_MULTI_RST_ADDR, Data);
}
static inline void OPENOFDM_TX_REG_INIT_PILOT_STATE_write(u32 Data) {
reg_write(OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR, Data);
}
static inline void OPENOFDM_TX_REG_INIT_DATA_STATE_write(u32 Data) {
reg_write(OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR, Data);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,openofdm_tx", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct openofdm_tx_driver_api openofdm_tx_driver_api_inst;
struct openofdm_tx_driver_api *openofdm_tx_api = &openofdm_tx_driver_api_inst;
EXPORT_SYMBOL(openofdm_tx_api);
static inline u32 hw_init(enum openofdm_tx_mode mode){
int err=0, i;
printk("%s hw_init mode %d\n", openofdm_tx_compatible_str, mode);
switch(mode)
{
case OPENOFDM_TX_TEST:
printk("%s hw_init mode OPENOFDM_TX_TEST\n", openofdm_tx_compatible_str);
break;
case OPENOFDM_TX_NORMAL:
printk("%s hw_init mode OPENOFDM_TX_NORMAL\n", openofdm_tx_compatible_str);
break;
default:
printk("%s hw_init mode %d is wrong!\n", openofdm_tx_compatible_str, mode);
err=1;
}
//rst
for (i=0;i<8;i++)
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0);
for (i=0;i<32;i++)
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
for (i=0;i<8;i++)
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0);
openofdm_tx_api->OPENOFDM_TX_REG_INIT_PILOT_STATE_write(0x7F);
openofdm_tx_api->OPENOFDM_TX_REG_INIT_DATA_STATE_write(0x7F);
printk("%s hw_init err %d\n", openofdm_tx_compatible_str, err);
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", openofdm_tx_compatible_str);
err = 0;
}
}
if (err)
return err;
openofdm_tx_api->hw_init=hw_init;
openofdm_tx_api->reg_read=reg_read;
openofdm_tx_api->reg_write=reg_write;
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write=OPENOFDM_TX_REG_MULTI_RST_write;
openofdm_tx_api->OPENOFDM_TX_REG_INIT_PILOT_STATE_write=OPENOFDM_TX_REG_INIT_PILOT_STATE_write;
openofdm_tx_api->OPENOFDM_TX_REG_INIT_DATA_STATE_write=OPENOFDM_TX_REG_INIT_DATA_STATE_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_tx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%08x\n", openofdm_tx_compatible_str,(u32)base_addr);
printk("%s dev_probe openofdm_tx_driver_api_inst 0x%08x\n", openofdm_tx_compatible_str, (u32)&openofdm_tx_driver_api_inst);
printk("%s dev_probe openofdm_tx_api 0x%08x\n", openofdm_tx_compatible_str, (u32)openofdm_tx_api);
printk("%s dev_probe succeed!\n", openofdm_tx_compatible_str);
err = hw_init(OPENOFDM_TX_NORMAL);
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%08x\n", openofdm_tx_compatible_str,(u32)base_addr);
printk("%s dev_remove openofdm_tx_driver_api_inst 0x%08x\n", openofdm_tx_compatible_str, (u32)&openofdm_tx_driver_api_inst);
printk("%s dev_remove openofdm_tx_api 0x%08x\n", openofdm_tx_compatible_str, (u32)openofdm_tx_api);
printk("%s dev_remove succeed!\n", openofdm_tx_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,openofdm_tx",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,openofdm_tx");
MODULE_LICENSE("GPL v2");
================================================
FILE: driver/rx_intf/Makefile
================================================
# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += rx_intf.o
all:
make -C $(KDIR) M=$(PWD) modules
# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
================================================
FILE: driver/rx_intf/rx_intf.c
================================================
/*
* axi lite register access driver
* Author: Xianjun Jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline u32 RX_INTF_REG_MULTI_RST_read(void){
return reg_read(RX_INTF_REG_MULTI_RST_ADDR);
}
static inline u32 RX_INTF_REG_MIXER_CFG_read(void){
return reg_read(RX_INTF_REG_MIXER_CFG_ADDR);
}
static inline u32 RX_INTF_REG_IQ_SRC_SEL_read(void){
return reg_read(RX_INTF_REG_IQ_SRC_SEL_ADDR);
}
static inline u32 RX_INTF_REG_IQ_CTRL_read(void){
return reg_read(RX_INTF_REG_IQ_CTRL_ADDR);
}
static inline u32 RX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){
return reg_read(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR);
}
static inline u32 RX_INTF_REG_START_TRANS_TO_PS_read(void){
return reg_read(RX_INTF_REG_START_TRANS_TO_PS_ADDR);
}
static inline u32 RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read(void){
return reg_read(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR);
}
static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){
return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR);
}
static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){
return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR);
}
static inline u32 RX_INTF_REG_CFG_DATA_TO_ANT_read(void){
return reg_read(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR);
}
static inline u32 RX_INTF_REG_ANT_SEL_read(void){
return reg_read(RX_INTF_REG_ANT_SEL_ADDR);
}
static inline u32 RX_INTF_REG_INTERRUPT_TEST_read(void) {
return reg_read(RX_INTF_REG_INTERRUPT_TEST_ADDR);
}
static inline void RX_INTF_REG_MULTI_RST_write(u32 value){
reg_write(RX_INTF_REG_MULTI_RST_ADDR, value);
}
static inline void RX_INTF_REG_M_AXIS_RST_write(u32 value){
u32 reg_val;
if (value==0) {
reg_val = RX_INTF_REG_MULTI_RST_read();
reg_val = ( reg_val&(~(1<<4)) );
RX_INTF_REG_MULTI_RST_write(reg_val);
} else {
reg_val = RX_INTF_REG_MULTI_RST_read();
reg_val = ( reg_val|(1<<4) );
RX_INTF_REG_MULTI_RST_write(reg_val);
}
}
static inline void RX_INTF_REG_MIXER_CFG_write(u32 value){
reg_write(RX_INTF_REG_MIXER_CFG_ADDR, value);
}
static inline void RX_INTF_REG_IQ_SRC_SEL_write(u32 value){
reg_write(RX_INTF_REG_IQ_SRC_SEL_ADDR, value);
}
static inline void RX_INTF_REG_IQ_CTRL_write(u32 value){
reg_write(RX_INTF_REG_IQ_CTRL_ADDR, value);
}
static inline void RX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){
reg_write(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value);
}
static inline void RX_INTF_REG_START_TRANS_TO_PS_write(u32 value){
reg_write(RX_INTF_REG_START_TRANS_TO_PS_ADDR, value);
}
static inline void RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(u32 value){
reg_write(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR, value);
}
static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){
reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value);
}
static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){
reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value);
}
static inline void RX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){
reg_write(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value);
}
static inline void RX_INTF_REG_BB_GAIN_write(u32 value) {
reg_write(RX_INTF_REG_BB_GAIN_ADDR, value);
}
static inline void RX_INTF_REG_ANT_SEL_write(u32 value){
reg_write(RX_INTF_REG_ANT_SEL_ADDR, value);
}
static inline void RX_INTF_REG_INTERRUPT_TEST_write(u32 value) {
reg_write(RX_INTF_REG_INTERRUPT_TEST_ADDR, value);
}
static inline void RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(u32 value) {
reg_write(RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR, value);
}
static inline void RX_INTF_REG_TLAST_TIMEOUT_TOP_write(u32 value) {
reg_write(RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR, value);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,rx_intf", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct rx_intf_driver_api rx_intf_driver_api_inst;
struct rx_intf_driver_api *rx_intf_api = &rx_intf_driver_api_inst;
EXPORT_SYMBOL(rx_intf_api);
static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){
int err=0, i;
u32 reg_val, mixer_cfg=0, ant_sel=0;
printk("%s hw_init mode %d\n", rx_intf_compatible_str, mode);
rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write(7000);
//rst
for (i=0;i<8;i++)
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
for (i=0;i<32;i++)
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0xFFFFFFFF);
for (i=0;i<8;i++)
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start
switch(mode)
{
case RX_INTF_AXIS_LOOP_BACK:
printk("%s hw_init mode RX_INTF_AXIS_LOOP_BACK\n", rx_intf_compatible_str);
//setting the path and mode. This must be done before our dma end reset
rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0x15);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(1);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x37);// endless mode to support sg DMA loop back, start 1 trans from sw trigger
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl);
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
// put bb_en to constant 1
reg_val = rx_intf_api->RX_INTF_REG_IQ_CTRL_read();
reg_val = (reg_val|0x8);
rx_intf_api->RX_INTF_REG_IQ_CTRL_write(reg_val);
// connect axis slave and master directly for loopback
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x1037);
// reset dma end point in our design
reg_val = rx_intf_api->RX_INTF_REG_MULTI_RST_read();
reg_val = (reg_val&(~0x14) );
rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val);
reg_val = reg_val|(0x14);
rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val);
reg_val = reg_val&(~0x14);
rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val);
//start 1 trans now from our m_axis to ps dma
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(1);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0);
break;
case RX_INTF_BW_20MHZ_AT_0MHZ_ANT0:
printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x300200F4;
ant_sel=0;
break;
case RX_INTF_BW_20MHZ_AT_0MHZ_ANT1:
printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x300200F4;
ant_sel=1;
break;
case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0:
printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x300202F6;
ant_sel=0;
break;
case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1:
printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x300202F6;
ant_sel=1;
break;
case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0:
printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x3001F602;
ant_sel=0;
break;
case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1:
printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x3001F602;
ant_sel=1;
break;
case RX_INTF_BYPASS:
printk("%s hw_init mode DDC_BYPASS\n", rx_intf_compatible_str);
mixer_cfg = 0x3001F602;
break;
default:
printk("%s hw_init mode %d is wrong!\n", rx_intf_compatible_str, mode);
err=1;
}
if (mode!=RX_INTF_AXIS_LOOP_BACK) {
// rx_intf_api->RX_INTF_REG_MIXER_CFG_write(mixer_cfg); --now rx doesn't have mixer anymore
// 0x000202F6 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: -2, -7, -12, -17MHz; zigbee 4 ch ant1: +3, +8, +13, +18MHz
// 0x0001F602 for: wifi ant0: +10MHz; wifi ant1: -10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz
// 0x0001F206 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz
// 0x2101F602 for: wifi gain 4; zigbee gain 2
// 0xFE01F602 for: wifi gain 1/2; zigbee gain 1/4
// bits definitions:
// wifi ch selection: ant0 bit1~0; ant1 bit 9~8; ch offset: 0-0MHz; 1-5MHz; 2-10MHz; 3-15MHz(severe distortion)
// wifi ch +/- selection: ant0 bit2; ant1 bit 10; 0-positive; 1-negative
// zigbee 2M mixer +/- selection: ant0 bit3; ant1 bit 11; 0-positive; 1-negative
// zigbee secondary mixer +/- selection: ant0 bit4~7; ant1 bit 12~15; 0-positive; 1-negative
// zigbee ch slip offset: ant0 bit16; ant1 bit17; 0-select ch offset 0, 5, 10, 15; 1-select ch offset 5 10 15 20
// wifi gain: bit31~28; number of bits shifted to left in 2'complement code
// zigb gain: bit27~24; number of bits shifted to left in 2'complement code
// max amplitude calibration info (agc low, ddc w/o gain adj 0x0001F602): 5GHz, max amplitude 1.26e4. According to simulation, schr shrink 1bit should be enough
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start
//rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000);
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100);
//0x000-normal; 0x100-sig and fcs valid are controlled by bit4 and bit0;
//0x111-sig and fcs high; 0x110-sig high fcs low; 0x101-sig low fcs high; 0x100-sig and fcs low
rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(30*10); // delayed interrupt, counter clock 10MHz is assumed
rx_intf_api->RX_INTF_REG_IQ_CTRL_write(0);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x10025); //now bit 5 should be 1 to let pl_to_m_axis_intf decide num_dma_symbol_to_ps automatically
//rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x00025); //bit16 enable_m_axis_auto_rst
//bit2-0: source of M AXIS transfer trigger
// -0 fcs_valid_from_acc
// -1 sig_valid_from_acc
// -2 sig_invalid_from_acc
// -3 start_1trans_s_axis_tlast_trigger
// -4 start_1trans_s_axis_tready_trigger
// -5 internal state machine together with bit5 1. By parsing signal field, num_dma_symbol_to_ps can be decided automatically
// -6 start_1trans_monitor_dma_to_ps_start_trigger
// -7 start_1trans_ext_trigger
//bit3: 1-fcs valid and invalid both connected; 0-only fcs valid connected (fcs_invalid_mode)
//bit4: 1-num_dma_symbol_to_pl from monitor; 0-num_dma_symbol_to_pl from slv_reg8
//bit5: 1-num_dma_symbol_to_ps from monitor; 0-num_dma_symbol_to_ps from slv_reg9
//bit6: 1-pl_to_m_axis_intf will try to send both ht and non-ht; 0-only send non-ht
//bit8: 1-endless S AXIS; 0-normal
//bit9: 1-endless M AXIS; 0-normal
//bit12: 1-direct loop back; 0-normal
//bit16: 1-auto m_axis rst (sig_valid_from_acc|sig_invalid_from_acc|ht_sig_valid|ht_sig_invalid|ht_unsupported); 0-normal
//bit24: 1-disable m_axis fifo_rst_by_fcs_invalid; 0-enable
//bit29,28: sig_valid_mode. 0- non-ht sig valid; 1- ht sig valid other- both
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(OPENWIFI_MAX_SIGNAL_LEN_TH<<16); //bit31~16 max pkt length threshold
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(0);
// 0-wifi_rx packet out; 1-loopback from input of wifi_rx
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl);
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(1<<8);
rx_intf_api->RX_INTF_REG_BB_GAIN_write(4);
// Remove RX_INTF_REG_ANT_SEL_write to avoid hw_init call in openwifi_start causing inconsistency
// rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel);
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0x14);//rst m/s axis
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start
}
if (mode==RX_INTF_BYPASS) {
rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(0x10); //bit4 bypass enable
}
printk("%s hw_init err %d\n", rx_intf_compatible_str, err);
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", rx_intf_compatible_str);
err = 0;
}
}
if (err)
return err;
rx_intf_api->hw_init=hw_init;
rx_intf_api->reg_read=reg_read;
rx_intf_api->reg_write=reg_write;
rx_intf_api->RX_INTF_REG_MULTI_RST_read=RX_INTF_REG_MULTI_RST_read;
rx_intf_api->RX_INTF_REG_MIXER_CFG_read=RX_INTF_REG_MIXER_CFG_read;
rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_read=RX_INTF_REG_IQ_SRC_SEL_read;
rx_intf_api->RX_INTF_REG_IQ_CTRL_read=RX_INTF_REG_IQ_CTRL_read;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_read=RX_INTF_REG_START_TRANS_TO_PS_MODE_read;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_read=RX_INTF_REG_START_TRANS_TO_PS_read;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read;
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read;
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read;
rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_read=RX_INTF_REG_CFG_DATA_TO_ANT_read;
rx_intf_api->RX_INTF_REG_ANT_SEL_read=RX_INTF_REG_ANT_SEL_read;
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_read=RX_INTF_REG_INTERRUPT_TEST_read;
rx_intf_api->RX_INTF_REG_MULTI_RST_write=RX_INTF_REG_MULTI_RST_write;
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write=RX_INTF_REG_M_AXIS_RST_write;
rx_intf_api->RX_INTF_REG_MIXER_CFG_write=RX_INTF_REG_MIXER_CFG_write;
rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write=RX_INTF_REG_IQ_SRC_SEL_write;
rx_intf_api->RX_INTF_REG_IQ_CTRL_write=RX_INTF_REG_IQ_CTRL_write;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write=RX_INTF_REG_START_TRANS_TO_PS_MODE_write;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write=RX_INTF_REG_START_TRANS_TO_PS_write;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write;
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write;
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write;
rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write=RX_INTF_REG_CFG_DATA_TO_ANT_write;
rx_intf_api->RX_INTF_REG_BB_GAIN_write=RX_INTF_REG_BB_GAIN_write;
rx_intf_api->RX_INTF_REG_ANT_SEL_write=RX_INTF_REG_ANT_SEL_write;
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write=RX_INTF_REG_INTERRUPT_TEST_write;
rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write=RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write;
rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write=RX_INTF_REG_TLAST_TIMEOUT_TOP_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
rx_intf_api->io_start = io->start;
rx_intf_api->base_addr = (u32)base_addr;
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", rx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%08x\n", rx_intf_compatible_str,(u32)base_addr);
printk("%s dev_probe rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) );
printk("%s dev_probe rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api);
printk("%s dev_probe succeed!\n", rx_intf_compatible_str);
//err = hw_init(DDC_CURRENT_CH_OFFSET_CFG,8,8);
err = hw_init(RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,8,8);
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%08x\n", rx_intf_compatible_str, (u32)base_addr);
printk("%s dev_remove rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) );
printk("%s dev_remove rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api);
printk("%s dev_remove succeed!\n", rx_intf_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,rx_intf",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,rx_intf");
MODULE_LICENSE("GPL v2");
================================================
FILE: driver/sdr.c
================================================
// Author: Xianjun Jiao, Michael Mehari, Wei Liu, Jetmir Haxhibeqiri, Pablo Avila Campos
// SPDX-FileCopyrightText: 2022 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
#include
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// #include
#define IIO_AD9361_USE_PRIVATE_H_
#include <../../drivers/iio/adc/ad9361_regs.h>
#include <../../drivers/iio/adc/ad9361.h>
#include <../../drivers/iio/adc/ad9361_private.h>
#include <../../drivers/iio/frequency/cf_axi_dds.h>
#include "../user_space/sdrctl_src/nl80211_testmode_def.h"
#include "hw_def.h"
#include "sdr.h"
#include "git_rev.h"
#ifndef RFSoC4x2
extern int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg);
extern int cf_axi_dds_datasel(struct cf_axi_dds_state *st, int channel, enum dds_data_select sel);
extern struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi);
extern int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state);
extern int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, struct ctrl_outs_control *ctrl);
extern int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, bool tx1, bool tx2, bool immed);
extern int ad9361_spi_read(struct spi_device *spi, u32 reg);
extern int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num);
#else
int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg){return(0);};
int cf_axi_dds_datasel(struct cf_axi_dds_state *st, int channel, enum dds_data_select sel){return(0);};
struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi){return(0);};
int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state){return(0);};
int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, struct ctrl_outs_control *ctrl){return(0);};
int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, bool tx1, bool tx2, bool immed){return(0);};
int ad9361_spi_read(struct spi_device *spi, u32 reg){return(0);};
int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num){return(0);};
#endif
static struct ad9361_rf_phy ad9361_phy_fake;
static struct ad9361_rf_phy_state ad9361_phy_state_fake;
// driver API of component driver
extern struct tx_intf_driver_api *tx_intf_api;
extern struct rx_intf_driver_api *rx_intf_api;
extern struct openofdm_tx_driver_api *openofdm_tx_api;
extern struct openofdm_rx_driver_api *openofdm_rx_api;
extern struct xpu_driver_api *xpu_api;
u32 gen_mpdu_crc(u8 *data_in, u32 num_bytes);
u8 gen_mpdu_delim_crc(u16 m);
u32 reverse32(u32 d);
static int openwifi_set_antenna(struct ieee80211_hw *dev, u32 tx_ant, u32 rx_ant);
static int openwifi_get_antenna(struct ieee80211_hw *dev, u32 *tx_ant, u32 *rx_ant);
int rssi_half_db_to_rssi_dbm(int rssi_half_db, int rssi_correction);
int rssi_dbm_to_rssi_half_db(int rssi_dbm, int rssi_correction);
int rssi_correction_lookup_table(u32 freq_MHz);
void ad9361_tx_calibration(struct openwifi_priv *priv, u32 actual_tx_lo);
void openwifi_rf_rx_update_after_tuning(struct openwifi_priv *priv, u32 actual_rx_lo);
static void ad9361_rf_set_channel(struct ieee80211_hw *dev, struct ieee80211_conf *conf);
static void rfsoc_rf_set_channel(struct ieee80211_hw *dev, struct ieee80211_conf *conf);
#include "sdrctl_intf.c"
#include "sysfs_intf.c"
// bit0: aggregation enable(1)/disable(0);
// bit1: tx offset tuning enable(0)/disable(1). NO USE ANY MORE
// bit1: short GI enable(1)/disable(0);
static int test_mode = 0;
// Internal indication variables after parsing test_mode
static bool AGGR_ENABLE = false;
static bool TX_OFFSET_TUNING_ENABLE = false;
static int init_tx_att = 0;
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("SDR driver");
MODULE_LICENSE("GPL v2");
module_param(test_mode, int, 0);
MODULE_PARM_DESC(myint, "test_mode. bit0: aggregation enable(1)/disable(0)");
module_param(init_tx_att, int, 0);
MODULE_PARM_DESC(myint, "init_tx_att. TX attenuation in dB*1000 example: set to 3000 for 3dB attenuation");
// ---------------rfkill---------------------------------------
static bool openwifi_is_radio_enabled(struct openwifi_priv *priv)
{
int reg;
if (priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_0MHZ_ANT0 || priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0 || priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH)
reg = ad9361_get_tx_atten(priv->ad9361_phy, 1);
else
reg = ad9361_get_tx_atten(priv->ad9361_phy, 2);
// if (reg == (AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]))
if (reg < AD9361_RADIO_OFF_TX_ATT)
return true;// 0 off, 1 on
return false;
}
void openwifi_rfkill_init(struct ieee80211_hw *hw)
{
struct openwifi_priv *priv = hw->priv;
priv->rfkill_off = openwifi_is_radio_enabled(priv);
printk("%s openwifi_rfkill_init: wireless switch is %s\n", sdr_compatible_str, priv->rfkill_off ? "on" : "off");
wiphy_rfkill_set_hw_state(hw->wiphy, !priv->rfkill_off);
wiphy_rfkill_start_polling(hw->wiphy);
}
void openwifi_rfkill_poll(struct ieee80211_hw *hw)
{
bool enabled;
struct openwifi_priv *priv = hw->priv;
enabled = openwifi_is_radio_enabled(priv);
// printk("%s openwifi_rfkill_poll: wireless radio switch turned %s\n", sdr_compatible_str, enabled ? "on" : "off");
if (unlikely(enabled != priv->rfkill_off)) {
priv->rfkill_off = enabled;
printk("%s openwifi_rfkill_poll: WARNING wireless radio switch turned %s\n", sdr_compatible_str, enabled ? "on" : "off");
wiphy_rfkill_set_hw_state(hw->wiphy, !enabled);
}
}
void openwifi_rfkill_exit(struct ieee80211_hw *hw)
{
printk("%s openwifi_rfkill_exit\n", sdr_compatible_str);
wiphy_rfkill_stop_polling(hw->wiphy);
}
//----------------rfkill end-----------------------------------
inline int rssi_dbm_to_rssi_half_db(int rssi_dbm, int rssi_correction)
{
return ((rssi_correction+rssi_dbm)<<1);
}
inline u8 freq_MHz_to_band(u32 freq_MHz)
{
//we choose 3822=(5160+2484)/2 for calibration to avoid treating 5140 as 2.4GHz
if (freq_MHz < OPENWIFI_FREQ_MHz_TH_FOR_2_4GHZ_5GHZ) {
return(BAND_2_4GHZ);
} else {//use this BAND_5_8GHZ to represent all frequencies above OPENWIFI_FREQ_TH_FOR_2_4GHZ_5GHZ
return(BAND_5_8GHZ);
}
}
inline int rssi_correction_lookup_table(u32 freq_MHz)
{
int rssi_correction;
if (freq_MHz<2412) {
rssi_correction = 153;
} else if (freq_MHz<=2484) {
rssi_correction = 153;
// } else if (freq_MHz<5160) {
} else if (freq_MHzlast_tx_quad_cal_lo = actual_tx_lo;
// do_gettimeofday(&tv);
// time_before = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec );
spi_disable = xpu_api->XPU_REG_SPI_DISABLE_read(); // backup current fpga spi disable state
xpu_api->XPU_REG_SPI_DISABLE_write(1); // disable FPGA SPI module
ad9361_do_calib_run(priv->ad9361_phy, TX_QUAD_CAL, (int)priv->ad9361_phy->state->last_tx_quad_cal_phase);
xpu_api->XPU_REG_SPI_DISABLE_write(spi_disable); // restore original SPI disable state
// do_gettimeofday(&tv);
// time_after = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec );
// printk("%s ad9361_tx_calibration %dMHz tx_quad_cal duration %lu us\n", sdr_compatible_str, actual_tx_lo, time_after-time_before);
printk("%s ad9361_tx_calibration %dMHz tx_quad_cal duration unknown us\n", sdr_compatible_str, actual_tx_lo);
}
inline void openwifi_rf_rx_update_after_tuning(struct openwifi_priv *priv, u32 actual_rx_lo)
{
int static_lbt_th, auto_lbt_th, fpga_lbt_th, receiver_rssi_dbm_th, receiver_rssi_th;
// get rssi correction value from lookup table
priv->rssi_correction = rssi_correction_lookup_table(actual_rx_lo);
// set appropriate lbt threshold
auto_lbt_th = rssi_dbm_to_rssi_half_db(-62, priv->rssi_correction); // -62dBm
static_lbt_th = rssi_dbm_to_rssi_half_db(-(priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH]), priv->rssi_correction);
fpga_lbt_th = (priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH]==0?auto_lbt_th:static_lbt_th);
xpu_api->XPU_REG_LBT_TH_write(fpga_lbt_th);
priv->last_auto_fpga_lbt_th = auto_lbt_th;
// Set rssi_half_db threshold (-85dBm equivalent) to receiver. Receiver will not react to signal lower than this rssi. See test records (OPENOFDM_RX_POWER_THRES_INIT in hw_def.h)
receiver_rssi_dbm_th = (priv->drv_rx_reg_val[DRV_RX_REG_IDX_DEMOD_TH]==0?OPENOFDM_RX_RSSI_DBM_TH_DEFAULT:(-priv->drv_rx_reg_val[DRV_RX_REG_IDX_DEMOD_TH]));
receiver_rssi_th = rssi_dbm_to_rssi_half_db(receiver_rssi_dbm_th, priv->rssi_correction);
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|receiver_rssi_th);
xpu_api->XPU_REG_BAND_CHANNEL_write( (priv->use_short_slot<<24)|(priv->band<<16)|actual_rx_lo );
printk("%s openwifi_rf_rx_update_after_tuning %dMHz rssi_correction %d fpga_lbt_th %d(%ddBm) auto %d static %d receiver th %d(%ddBm)\n", sdr_compatible_str,
actual_rx_lo, priv->rssi_correction, fpga_lbt_th, rssi_half_db_to_rssi_dbm(fpga_lbt_th, priv->rssi_correction), auto_lbt_th, static_lbt_th, receiver_rssi_th, receiver_rssi_dbm_th);
}
static void rfsoc_rf_set_channel(struct ieee80211_hw *dev,
struct ieee80211_conf *conf)
{
}
static void ad9361_rf_set_channel(struct ieee80211_hw *dev,
struct ieee80211_conf *conf)
{
struct openwifi_priv *priv = dev->priv;
u32 actual_rx_lo;
u32 actual_tx_lo;
u32 diff_tx_lo;
bool change_flag;
actual_rx_lo = conf->chandef.chan->center_freq - priv->rx_freq_offset_to_lo_MHz;
change_flag = (actual_rx_lo != priv->actual_rx_lo);
printk("%s ad9361_rf_set_channel target %dMHz rx offset %dMHz current %dMHz change flag %d\n", sdr_compatible_str,
conf->chandef.chan->center_freq, priv->rx_freq_offset_to_lo_MHz, priv->actual_rx_lo, change_flag);
// if (change_flag && priv->rf_reg_val[RF_TX_REG_IDX_FREQ_MHZ]==0 && priv->rf_reg_val[RF_RX_REG_IDX_FREQ_MHZ]==0) {
if (change_flag) {
actual_tx_lo = conf->chandef.chan->center_freq - priv->tx_freq_offset_to_lo_MHz;
diff_tx_lo = priv->last_tx_quad_cal_lo > actual_tx_lo ? priv->last_tx_quad_cal_lo - actual_tx_lo : actual_tx_lo - priv->last_tx_quad_cal_lo;
printk("%s ad9361_rf_set_channel target %dMHz tx offset %dMHz current %dMHz diff_tx_lo %dMHz\n", sdr_compatible_str,
conf->chandef.chan->center_freq, priv->tx_freq_offset_to_lo_MHz, priv->actual_tx_lo, diff_tx_lo);
// -------------------Tx Lo tuning-------------------
clk_set_rate(priv->ad9361_phy->clks[TX_RFPLL], ( ((u64)1000000ull)*((u64)actual_tx_lo) )>>1);
priv->actual_tx_lo = actual_tx_lo;
// -------------------Rx Lo tuning-------------------
clk_set_rate(priv->ad9361_phy->clks[RX_RFPLL], ( ((u64)1000000ull)*((u64)actual_rx_lo) )>>1);
priv->actual_rx_lo = actual_rx_lo;
priv->band = freq_MHz_to_band(actual_rx_lo);
// call Tx Quadrature calibration if frequency change is more than 100MHz
if (diff_tx_lo > 100)
ad9361_tx_calibration(priv, actual_tx_lo);
openwifi_rf_rx_update_after_tuning(priv, actual_rx_lo);
printk("%s ad9361_rf_set_channel %dMHz done\n", sdr_compatible_str,conf->chandef.chan->center_freq);
}
}
const struct openwifi_rf_ops ad9361_rf_ops = {
.name = "ad9361",
// .init = ad9361_rf_init,
// .stop = ad9361_rf_stop,
.set_chan = ad9361_rf_set_channel,
// .calc_rssi = ad9361_rf_calc_rssi,
};
const struct openwifi_rf_ops rfsoc4x2_rf_ops = {
.name = "rfsoc4x2",
// .init = ad9361_rf_init,
// .stop = ad9361_rf_stop,
.set_chan = rfsoc_rf_set_channel,
// .calc_rssi = ad9361_rf_calc_rssi,
};
u16 reverse16(u16 d) {
union u16_byte2 tmp0, tmp1;
tmp0.a = d;
tmp1.c[0] = tmp0.c[1];
tmp1.c[1] = tmp0.c[0];
return(tmp1.a);
}
u32 reverse32(u32 d) {
union u32_byte4 tmp0, tmp1;
tmp0.a = d;
tmp1.c[0] = tmp0.c[3];
tmp1.c[1] = tmp0.c[2];
tmp1.c[2] = tmp0.c[1];
tmp1.c[3] = tmp0.c[0];
return(tmp1.a);
}
static int openwifi_init_tx_ring(struct openwifi_priv *priv, int ring_idx)
{
struct openwifi_ring *ring = &(priv->tx_ring[ring_idx]);
int i;
ring->stop_flag = -1;
ring->bd_wr_idx = 0;
ring->bd_rd_idx = 0;
ring->bds = kmalloc(sizeof(struct openwifi_buffer_descriptor)*NUM_TX_BD,GFP_KERNEL);
if (ring->bds==NULL) {
printk("%s openwifi_init_tx_ring: WARNING Cannot allocate TX ring\n",sdr_compatible_str);
return -ENOMEM;
}
for (i = 0; i < NUM_TX_BD; i++) {
ring->bds[i].skb_linked=NULL; // for tx, skb is from upper layer
//at first right after skb allocated, head, data, tail are the same.
ring->bds[i].dma_mapping_addr = 0; // for tx, mapping is done after skb is received from upper layer in tx routine
ring->bds[i].seq_no = 0xffff; // invalid value
ring->bds[i].prio = 0xff; // invalid value
ring->bds[i].len_mpdu = 0; // invalid value
}
return 0;
}
static void openwifi_free_tx_ring(struct openwifi_priv *priv, int ring_idx)
{
struct openwifi_ring *ring = &(priv->tx_ring[ring_idx]);
int i;
ring->stop_flag = -1;
ring->bd_wr_idx = 0;
ring->bd_rd_idx = 0;
for (i = 0; i < NUM_TX_BD; i++) {
if (ring->bds[i].skb_linked == 0 && ring->bds[i].dma_mapping_addr == 0)
continue;
if (ring->bds[i].dma_mapping_addr != 0)
dma_unmap_single(priv->tx_chan->device->dev, ring->bds[i].dma_mapping_addr,ring->bds[i].skb_linked->len, DMA_MEM_TO_DEV);
// if (ring->bds[i].skb_linked!=NULL)
// dev_kfree_skb(ring->bds[i].skb_linked); // only use dev_kfree_skb when there is exception
if ( (ring->bds[i].dma_mapping_addr != 0 && ring->bds[i].skb_linked == 0) ||
(ring->bds[i].dma_mapping_addr == 0 && ring->bds[i].skb_linked != 0))
printk("%s openwifi_free_tx_ring: WARNING ring %d i %d skb_linked %p dma_mapping_addr %08x\n", sdr_compatible_str,
ring_idx, i, (void*)(ring->bds[i].skb_linked), (unsigned int)(ring->bds[i].dma_mapping_addr));
ring->bds[i].skb_linked=NULL;
ring->bds[i].dma_mapping_addr = 0;
ring->bds[i].seq_no = 0xffff; // invalid value
ring->bds[i].prio = 0xff; // invalid value
ring->bds[i].len_mpdu = 0; // invalid value
}
if (ring->bds)
kfree(ring->bds);
ring->bds = NULL;
}
static int openwifi_init_rx_ring(struct openwifi_priv *priv)
{
int i;
u8 *pdata_tmp;
priv->rx_cyclic_buf = dma_alloc_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,&priv->rx_cyclic_buf_dma_mapping_addr,GFP_KERNEL);
if (!priv->rx_cyclic_buf) {
printk("%s openwifi_init_rx_ring: WARNING dma_alloc_coherent failed!\n", sdr_compatible_str);
dma_free_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,priv->rx_cyclic_buf,priv->rx_cyclic_buf_dma_mapping_addr);
return(-1);
}
// Set tsft_low and tsft_high to 0. If they are not zero, it means there is a packet in the buffer by DMA
for (i=0; irx_cyclic_buf + i*RX_BD_BUF_SIZE; // our header insertion is at the beginning
(*((u16*)(pdata_tmp+10))) = 0;
}
printk("%s openwifi_init_rx_ring: NUM_RX_BD %d RX_BD_BUF_SIZE %d pkt existing flag are cleared!\n", sdr_compatible_str,
NUM_RX_BD, RX_BD_BUF_SIZE);
return 0;
}
static void openwifi_free_rx_ring(struct openwifi_priv *priv)
{
if (priv->rx_cyclic_buf)
dma_free_coherent(priv->rx_chan->device->dev,RX_BD_BUF_SIZE*NUM_RX_BD,priv->rx_cyclic_buf,priv->rx_cyclic_buf_dma_mapping_addr);
priv->rx_cyclic_buf_dma_mapping_addr = 0;
priv->rx_cyclic_buf = 0;
}
static int rx_dma_setup(struct ieee80211_hw *dev){
struct openwifi_priv *priv = dev->priv;
struct dma_device *rx_dev = priv->rx_chan->device;
priv->rxd = rx_dev->device_prep_dma_cyclic(priv->rx_chan,priv->rx_cyclic_buf_dma_mapping_addr,RX_BD_BUF_SIZE*NUM_RX_BD,RX_BD_BUF_SIZE,DMA_DEV_TO_MEM,DMA_CTRL_ACK|DMA_PREP_INTERRUPT);
if (!(priv->rxd)) {
openwifi_free_rx_ring(priv);
printk("%s rx_dma_setup: WARNING rx_dev->device_prep_dma_cyclic %p\n", sdr_compatible_str, (void*)(priv->rxd));
return(-1);
}
priv->rxd->callback = 0;
priv->rxd->callback_param = 0;
priv->rx_cookie = priv->rxd->tx_submit(priv->rxd);
if (dma_submit_error(priv->rx_cookie)) {
printk("%s rx_dma_setup: WARNING dma_submit_error(rx_cookie) %d\n", sdr_compatible_str, (u32)(priv->rx_cookie));
return(-1);
}
dma_async_issue_pending(priv->rx_chan);
return(0);
}
inline int rssi_half_db_to_rssi_dbm(int rssi_half_db, int rssi_correction)
{
int rssi_db, rssi_dbm;
rssi_db = (rssi_half_db>>1);
rssi_dbm = rssi_db - rssi_correction;
rssi_dbm = (rssi_dbm < (-128)? (-128) : rssi_dbm);
return rssi_dbm;
}
static irqreturn_t openwifi_rx_interrupt(int irq, void *dev_id)
{
struct ieee80211_hw *dev = dev_id;
struct openwifi_priv *priv = dev->priv;
struct ieee80211_rx_status rx_status = {0};
struct sk_buff *skb;
struct ieee80211_hdr *hdr;
u32 addr1_low32, addr2_low32=0, addr3_low32=0, len, rate_idx, tsft_low, tsft_high, loop_count=0;//, fc_di;
bool ht_flag, short_gi, ht_aggr, ht_aggr_last;
// u32 dma_driver_buf_idx_mod;
u8 *pdata_tmp;
u8 fcs_ok;//, target_buf_idx;//, phy_rx_sn_hw;
s8 signal, phase_offset;
u16 agc_status_and_pkt_exist_flag, rssi_half_db, addr1_high16, addr2_high16=0, addr3_high16=0, seq_no=0;
bool content_ok, len_overflow, is_unicast;
#ifdef USE_NEW_RX_INTERRUPT
int i;
spin_lock(&priv->lock);
for (i=0; irx_cyclic_buf + i*RX_BD_BUF_SIZE;
agc_status_and_pkt_exist_flag = (*((u16*)(pdata_tmp+10))); //check rx_intf_pl_to_m_axis.v. FPGA TODO: add pkt exist 1bit flag next to gpio_status_lock_by_sig_valid
if ( agc_status_and_pkt_exist_flag==0 ) // no packet in the buffer
continue;
#else
static u8 target_buf_idx_old = 0;
spin_lock(&priv->lock);
while(1) { // loop all rx buffers that have new rx packets
pdata_tmp = priv->rx_cyclic_buf + target_buf_idx_old*RX_BD_BUF_SIZE; // our header insertion is at the beginning
agc_status_and_pkt_exist_flag = (*((u16*)(pdata_tmp+10)));
if ( agc_status_and_pkt_exist_flag==0 ) // no packet in the buffer
break;
#endif
tsft_low = (*((u32*)(pdata_tmp+0 )));
tsft_high = (*((u32*)(pdata_tmp+4 )));
rssi_half_db = (*((u16*)(pdata_tmp+8 )));
len = (*((u16*)(pdata_tmp+12)));
len_overflow = (len>(RX_BD_BUF_SIZE-16)?true:false);
rate_idx = (*((u16*)(pdata_tmp+14)));
ht_flag = ((rate_idx&0x10)!=0);
short_gi = ((rate_idx&0x20)!=0);
ht_aggr = (ht_flag & ((rate_idx&0x40)!=0));
ht_aggr_last = (ht_flag & ((rate_idx&0x80)!=0));
phase_offset = (rate_idx>>8);
rate_idx = (rate_idx&0x1F);
fcs_ok = ( len_overflow?0:(*(( u8*)(pdata_tmp+16+len-1))) );
//phy_rx_sn_hw = (fcs_ok&(NUM_RX_BD-1));
// phy_rx_sn_hw = (fcs_ok&0x7f);//0x7f is FPGA limitation
// dma_driver_buf_idx_mod = (state.residue&0x7f);
fcs_ok = ((fcs_ok&0x80)!=0);
if ( (len>=14 && (!len_overflow)) && (rate_idx>=8 && rate_idx<=23)) {
// if ( phy_rx_sn_hw!=dma_driver_buf_idx_mod) {
// printk("%s openwifi_rx: WARNING sn %d next buf_idx %d!\n", sdr_compatible_str,phy_rx_sn_hw,dma_driver_buf_idx_mod);
// }
content_ok = true;
} else {
printk("%s openwifi_rx: WARNING content! len%d overflow%d rate_idx%d\n", sdr_compatible_str,
len, len_overflow, rate_idx);
content_ok = false;
}
signal = rssi_half_db_to_rssi_dbm(rssi_half_db, priv->rssi_correction);
hdr = (struct ieee80211_hdr *)(pdata_tmp+16);
if (len>=20) {
addr2_low32 = *((u32*)(hdr->addr2+2));
addr2_high16 = *((u16*)(hdr->addr2));
}
addr1_low32 = *((u32*)(hdr->addr1+2));
addr1_high16 = *((u16*)(hdr->addr1));
if ( priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_ANY ) {
if (len>=26) {
addr3_low32 = *((u32*)(hdr->addr3+2));
addr3_high16 = *((u16*)(hdr->addr3));
}
if (len>=28)
seq_no = ( (hdr->seq_ctrl&IEEE80211_SCTL_SEQ)>>4 );
is_unicast = (addr1_low32!=0xffffffff || addr1_high16!=0xffff);
if ( (( is_unicast)&&(priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_UNICAST)) ||
((!is_unicast)&&(priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_BROADCAST)) ||
(( fcs_ok==0)&&(priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_ERROR)) )
printk("%s openwifi_rx: %dB ht%daggr%d/%d sgi%d %dM FC%04x DI%04x ADDR%04x%08x/%04x%08x/%04x%08x SC%d fcs%d buf_idx%d %ddBm fo %d\n", sdr_compatible_str,
len, ht_flag, ht_aggr, ht_aggr_last, short_gi, wifi_rate_table[rate_idx], hdr->frame_control, hdr->duration_id,
reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32),
#ifdef USE_NEW_RX_INTERRUPT
seq_no, fcs_ok, i, signal, phase_offset);
#else
seq_no, fcs_ok, target_buf_idx_old, signal, phase_offset);
#endif
}
// priv->phy_rx_sn_hw_old = phy_rx_sn_hw;
if (content_ok) {
skb = dev_alloc_skb(len);
if (skb) {
skb_put_data(skb,pdata_tmp+16,len);
rx_status.antenna = priv->runtime_rx_ant_cfg;
// def in ieee80211_rate openwifi_rates 0~11. 0~3 11b(1M~11M), 4~11 11a/g(6M~54M)
rx_status.rate_idx = wifi_rate_table_mapping[rate_idx];
rx_status.signal = signal;
rx_status.freq = dev->conf.chandef.chan->center_freq;
// rx_status.freq = priv->actual_rx_lo;
rx_status.band = dev->conf.chandef.chan->band;
// rx_status.band = (rx_status.freq<2500?NL80211_BAND_2GHZ:NL80211_BAND_5GHZ);
rx_status.mactime = ( ( (u64)tsft_low ) | ( ((u64)tsft_high)<<32 ) );
rx_status.flag |= RX_FLAG_MACTIME_START;
if (!fcs_ok)
rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
if (rate_idx <= 15)
rx_status.encoding = RX_ENC_LEGACY;
else
rx_status.encoding = RX_ENC_HT;
rx_status.bw = RATE_INFO_BW_20;
if (short_gi)
rx_status.enc_flags |= RX_ENC_FLAG_SHORT_GI;
if(ht_aggr)
{
rx_status.ampdu_reference = priv->ampdu_reference;
rx_status.flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN;
if (ht_aggr_last)
rx_status.flag |= RX_FLAG_AMPDU_IS_LAST;
}
memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); // put rx_status into skb->cb, from now on skb->cb is not dma_dsts any more.
ieee80211_rx_irqsafe(dev, skb); // call mac80211 function
// printk("%s openwifi_rx: addr1_low32 %08x self addr %08x\n", sdr_compatible_str, addr1_low32, ( *( (u32*)(priv->mac_addr+2) ) ));
if (addr1_low32 == ( *( (u32*)(priv->mac_addr+2) ) ) && priv->stat.stat_enable) {
agc_status_and_pkt_exist_flag = (agc_status_and_pkt_exist_flag&0x7f);
if (len>=20) {// rx stat
if (addr2_low32 == priv->stat.rx_target_sender_mac_addr || priv->stat.rx_target_sender_mac_addr==0) {
if ( ieee80211_is_data(hdr->frame_control) ) {
priv->stat.rx_data_pkt_mcs_realtime = rate_idx;
priv->stat.rx_data_pkt_num_total++;
if (!fcs_ok) {
priv->stat.rx_data_pkt_num_fail++;
priv->stat.rx_data_pkt_fail_mcs_realtime = rate_idx;
priv->stat.rx_data_fail_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;
} else {
priv->stat.rx_data_ok_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;
}
} else if ( ieee80211_is_mgmt(hdr->frame_control) ) {
priv->stat.rx_mgmt_pkt_mcs_realtime = rate_idx;
priv->stat.rx_mgmt_pkt_num_total++;
if (!fcs_ok) {
priv->stat.rx_mgmt_pkt_num_fail++;
priv->stat.rx_mgmt_pkt_fail_mcs_realtime = rate_idx;
priv->stat.rx_mgmt_fail_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;
} else {
priv->stat.rx_mgmt_ok_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;
}
}
}
} else if ( ieee80211_is_ack(hdr->frame_control) ) {
priv->stat.rx_ack_pkt_mcs_realtime = rate_idx;
priv->stat.rx_ack_pkt_num_total++;
if (!fcs_ok) {
priv->stat.rx_ack_pkt_num_fail++;
} else {
priv->stat.rx_ack_ok_agc_gain_value_realtime = agc_status_and_pkt_exist_flag;
}
}
}
} else
printk("%s openwifi_rx: WARNING dev_alloc_skb failed!\n", sdr_compatible_str);
if(ht_aggr_last)
priv->ampdu_reference++;
}
(*((u16*)(pdata_tmp+10))) = 0; // clear the field (set by rx_intf_pl_to_m_axis.v) to indicate the packet has been processed
loop_count++;
#ifndef USE_NEW_RX_INTERRUPT
target_buf_idx_old=((target_buf_idx_old+1)&(NUM_RX_BD-1));
#endif
}
if ( loop_count!=1 && (priv->drv_rx_reg_val[DRV_RX_REG_IDX_PRINT_CFG]&DMESG_LOG_ERROR) )
printk("%s openwifi_rx: WARNING loop_count %d\n", sdr_compatible_str,loop_count);
// openwifi_rx_out:
spin_unlock(&priv->lock);
return IRQ_HANDLED;
}
static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
{
struct ieee80211_hw *dev = dev_id;
struct openwifi_priv *priv = dev->priv;
struct openwifi_ring *ring, *drv_ring_tmp;
struct sk_buff *skb;
struct ieee80211_tx_info *info;
struct ieee80211_hdr *hdr;
u32 reg_val1, hw_queue_len, reg_val2, dma_fifo_no_room_flag, num_slot_random, cw, loop_count=0, addr1_low32, mcs_for_sysfs;
u16 seq_no, pkt_cnt, blk_ack_ssn, start_idx;
u8 nof_retx=-1, last_bd_rd_idx, i, prio, queue_idx, nof_retx_stat;
u64 blk_ack_bitmap;
// u16 prio_rd_idx_store[64]={0};
bool tx_fail=false, fpga_queue_has_room=false;
bool use_ht_aggr, pkt_need_ack, use_ht_rate, prio_wake_up_flag = false;
spin_lock(&priv->lock);
while(1) { // loop all packets that have been sent by FPGA
reg_val1 = tx_intf_api->TX_INTF_REG_PKT_INFO1_read();
reg_val2 = tx_intf_api->TX_INTF_REG_PKT_INFO2_read();
blk_ack_bitmap = (tx_intf_api->TX_INTF_REG_PKT_INFO3_read() | ((u64)tx_intf_api->TX_INTF_REG_PKT_INFO4_read())<<32);
if (reg_val1!=0xFFFFFFFF) {
nof_retx = (reg_val1&0xF);
last_bd_rd_idx = ((reg_val1>>5)&(NUM_TX_BD-1));
prio = ((reg_val1>>17)&0x3);
num_slot_random = ((reg_val1>>19)&0x1FF);
//num_slot_random = ((0xFF80000 ®_val1)>>(2+5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
cw = ((reg_val1>>28)&0xF);
//cw = ((0xF0000000 & reg_val1) >> 28);
if(cw > 10) {
cw = 10 ;
num_slot_random += 512 ;
}
pkt_cnt = (reg_val2&0x3F);
blk_ack_ssn = ((reg_val2>>6)&0xFFF);
queue_idx = ((reg_val1>>15)&(MAX_NUM_HW_QUEUE-1));
dma_fifo_no_room_flag = tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read();
hw_queue_len = tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read();
// check which linux prio is stopped by this queue (queue_idx)
for (i=0; itx_ring[i]);
if ( drv_ring_tmp->stop_flag == prio ) {
if ( ((dma_fifo_no_room_flag>>i)&1)==0 && (NUM_TX_BD-((hw_queue_len>>(i*8))&0xFF))>=RING_ROOM_THRESHOLD )
fpga_queue_has_room=true;
else
fpga_queue_has_room=false;
// Wake up Linux queue due to the current fpga queue releases some room
if( priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_NORMAL_QUEUE_STOP )
printk("%s openwifi_tx_interrupt: WARNING ieee80211_wake_queue prio%d i%d queue%d no room flag%x hwq len%08x wr%d rd%d\n", sdr_compatible_str,
prio, i, queue_idx, dma_fifo_no_room_flag, hw_queue_len, drv_ring_tmp->bd_wr_idx, last_bd_rd_idx);
if (fpga_queue_has_room) {
prio_wake_up_flag = true;
drv_ring_tmp->stop_flag = -1;
if (priv->stat.stat_enable) {
priv->stat.tx_prio_wakeup_num[prio]++;
priv->stat.tx_queue_wakeup_num[i]++;
}
} else {
if( priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_NORMAL_QUEUE_STOP )
printk("%s openwifi_tx_interrupt: WARNING no room! prio_wake_up_flag%d\n", sdr_compatible_str, prio_wake_up_flag);
}
}
}
if (prio_wake_up_flag)
ieee80211_wake_queue(dev, prio);
if (priv->stat.stat_enable) {
priv->stat.tx_prio_interrupt_num[prio] = priv->stat.tx_prio_interrupt_num[prio] + pkt_cnt;
priv->stat.tx_queue_interrupt_num[queue_idx] = priv->stat.tx_queue_interrupt_num[queue_idx] + pkt_cnt;
}
ring = &(priv->tx_ring[queue_idx]);
for(i = 1; i <= pkt_cnt; i++)
{
ring->bd_rd_idx = (last_bd_rd_idx + i - pkt_cnt + 64)%64;
seq_no = ring->bds[ring->bd_rd_idx].seq_no;
if (seq_no == 0xffff) {// it has been forced cleared by the openwifi_tx (due to out-of-order Tx of different queues to the air?)
printk("%s openwifi_tx_interrupt: WARNING wr%d rd%d last_bd_rd_idx%d i%d pkt_cnt%d prio%d fpga q%d hwq len%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%u\n", sdr_compatible_str,
ring->bd_wr_idx, ring->bd_rd_idx, last_bd_rd_idx, i, pkt_cnt, prio, queue_idx, hw_queue_len, ring->bds[ring->bd_rd_idx].prio, ring->bds[ring->bd_rd_idx].len_mpdu, seq_no, ring->bds[ring->bd_rd_idx].skb_linked, (long long int)(ring->bds[ring->bd_rd_idx].dma_mapping_addr));
continue;
}
skb = ring->bds[ring->bd_rd_idx].skb_linked;
dma_unmap_single(priv->tx_chan->device->dev,ring->bds[ring->bd_rd_idx].dma_mapping_addr,
skb->len, DMA_MEM_TO_DEV);
info = IEEE80211_SKB_CB(skb);
use_ht_aggr = ((info->flags&IEEE80211_TX_CTL_AMPDU)!=0);
ieee80211_tx_info_clear_status(info);
// Aggregation packet
if (use_ht_aggr)
{
start_idx = (seq_no>=blk_ack_ssn) ? (seq_no-blk_ack_ssn) : (seq_no+((~blk_ack_ssn+1)&0x0FFF));
tx_fail = (((blk_ack_bitmap>>start_idx)&0x1)==0);
info->flags |= IEEE80211_TX_STAT_AMPDU;
info->status.ampdu_len = 1;
info->status.ampdu_ack_len = (tx_fail == true) ? 0 : 1;
skb_pull(skb, LEN_MPDU_DELIM);
//skb_trim(skb, num_byte_pad_skb);
}
// Normal packet
else
{
tx_fail = ((blk_ack_bitmap&0x1)==0);
info->flags &= (~IEEE80211_TX_CTL_AMPDU);
}
pkt_need_ack = (!(info->flags & IEEE80211_TX_CTL_NO_ACK));
// do statistics for data packet that needs ack
hdr = (struct ieee80211_hdr *)skb->data;
addr1_low32 = *((u32*)(hdr->addr1+2));
if ( priv->stat.stat_enable && pkt_need_ack && (addr1_low32 == priv->stat.rx_target_sender_mac_addr || priv->stat.rx_target_sender_mac_addr==0) ) {
use_ht_rate = (((info->control.rates[0].flags)&IEEE80211_TX_RC_MCS)!=0);
mcs_for_sysfs = ieee80211_get_tx_rate(dev, info)->hw_value;
if (use_ht_rate)
mcs_for_sysfs = (mcs_for_sysfs | 0x80000000);
if ( ieee80211_is_data(hdr->frame_control) ) {
nof_retx_stat = (nof_retx<=5?nof_retx:5);
priv->stat.tx_data_pkt_need_ack_num_total++;
priv->stat.tx_data_pkt_mcs_realtime = mcs_for_sysfs;
priv->stat.tx_data_pkt_need_ack_num_retx[nof_retx_stat]++;
if (tx_fail) {
priv->stat.tx_data_pkt_need_ack_num_total_fail++;
priv->stat.tx_data_pkt_fail_mcs_realtime = mcs_for_sysfs;
priv->stat.tx_data_pkt_need_ack_num_retx_fail[nof_retx_stat]++;
}
} else if ( ieee80211_is_mgmt(hdr->frame_control) ) {
nof_retx_stat = (nof_retx<=2?nof_retx:2);
priv->stat.tx_mgmt_pkt_need_ack_num_total++;
priv->stat.tx_mgmt_pkt_mcs_realtime = mcs_for_sysfs;
priv->stat.tx_mgmt_pkt_need_ack_num_retx[nof_retx_stat]++;
if (tx_fail) {
priv->stat.tx_mgmt_pkt_need_ack_num_total_fail++;
priv->stat.tx_mgmt_pkt_fail_mcs_realtime = mcs_for_sysfs;
priv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[nof_retx_stat]++;
}
}
}
if ( tx_fail == false )
info->flags |= IEEE80211_TX_STAT_ACK;
info->status.rates[0].count = nof_retx + 1; //according to our test, the 1st rate is the most important. we only do retry on the 1st rate
info->status.rates[1].idx = -1;
// info->status.rates[2].idx = -1;
// info->status.rates[3].idx = -1;//in mac80211.h: #define IEEE80211_TX_MAX_RATES 4
info->status.antenna = priv->runtime_tx_ant_cfg;
if ( ( (!pkt_need_ack)&&(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_BROADCAST) ) || ( (pkt_need_ack)&&(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_UNICAST) ) ){
printk("%s openwifi_tx_interrupt: tx_result [nof_retx %d pass %d] SC%d prio%d q%d wr%d rd%d num_slot%d cw%d hwq len%08x no_room_flag%x\n", sdr_compatible_str,
nof_retx+1, !tx_fail, seq_no, prio, queue_idx, ring->bd_wr_idx, ring->bd_rd_idx, num_slot_random, cw, hw_queue_len, dma_fifo_no_room_flag);
}
ieee80211_tx_status_irqsafe(dev, skb);
ring->bds[ring->bd_rd_idx].prio = 0xff; // invalid value
ring->bds[ring->bd_rd_idx].len_mpdu = 0; // invalid value
ring->bds[ring->bd_rd_idx].seq_no = 0xffff;
ring->bds[ring->bd_rd_idx].skb_linked = NULL;
ring->bds[ring->bd_rd_idx].dma_mapping_addr = 0;
}
loop_count++;
// printk("%s openwifi_tx_interrupt: loop %d prio %d rd %d\n", sdr_compatible_str, loop_count, prio, ring->bd_rd_idx);
} else
break;
}
if ( loop_count!=1 && ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&DMESG_LOG_ERROR) )
printk("%s openwifi_tx_interrupt: WARNING loop_count %d\n", sdr_compatible_str, loop_count);
spin_unlock(&priv->lock);
return IRQ_HANDLED;
}
u32 crc_table[16] = {0x4DBDF21C, 0x500AE278, 0x76D3D2D4, 0x6B64C2B0, 0x3B61B38C, 0x26D6A3E8, 0x000F9344, 0x1DB88320, 0xA005713C, 0xBDB26158, 0x9B6B51F4, 0x86DC4190, 0xD6D930AC, 0xCB6E20C8, 0xEDB71064, 0xF0000000};
u32 gen_mpdu_crc(u8 *data_in, u32 num_bytes)
{
u32 i, crc = 0;
u8 idx;
for( i = 0; i < num_bytes; i++)
{
idx = (crc & 0x0F) ^ (data_in[i] & 0x0F);
crc = (crc >> 4) ^ crc_table[idx];
idx = (crc & 0x0F) ^ ((data_in[i] >> 4) & 0x0F);
crc = (crc >> 4) ^ crc_table[idx];
}
return crc;
}
u8 gen_mpdu_delim_crc(u16 m)
{
u8 i, temp, c[8] = {1, 1, 1, 1, 1, 1, 1, 1}, mpdu_delim_crc;
for (i = 0; i < 16; i++)
{
temp = c[7] ^ ((m >> i) & 0x01);
c[7] = c[6];
c[6] = c[5];
c[5] = c[4];
c[4] = c[3];
c[3] = c[2];
c[2] = c[1] ^ temp;
c[1] = c[0] ^ temp;
c[0] = temp;
}
mpdu_delim_crc = ((~c[7] & 0x01) << 0) | ((~c[6] & 0x01) << 1) | ((~c[5] & 0x01) << 2) | ((~c[4] & 0x01) << 3) | ((~c[3] & 0x01) << 4) | ((~c[2] & 0x01) << 5) | ((~c[1] & 0x01) << 6) | ((~c[0] & 0x01) << 7);
return mpdu_delim_crc;
}
static inline struct gpio_led_data * //please align with the implementation in leds-gpio.c
cdev_to_gpio_led_data(struct led_classdev *led_cdev)
{
return container_of(led_cdev, struct gpio_led_data, cdev);
}
inline int calc_n_ofdm(int num_octet, int n_dbps)
{
int num_bit, num_ofdm_sym;
num_bit = 22+num_octet*8;
num_ofdm_sym = (num_bit/n_dbps) + ((num_bit%n_dbps)!=0);
return (num_ofdm_sym);
}
inline __le16 gen_ht_duration_id(__le16 frame_control, __le16 aid, u8 qos_hdr, bool use_ht_aggr, u8 rate_hw_value, u16 sifs)
{
// COTS wifi ht QoS data duration field analysis (lots of capture):
// ht non-aggr QoS data: 44, type 2 (data frame) sub-type 8 (1000) 21.7/52/57.8/58.5/65Mbps
// ack ht 36 + 4*[(22+14*8)/78] = 36 + 4*2 = 44
// ack legacy 20 + 4*[(22+14*8)/72] = 20 + 4*2 = 28
// ht non-aggr QoS data: 60, type 2 (data frame) sub-type 8 (1000) 6.5Mbps
// ack ht 36 + 4*[(22+14*8)/26] = 36 + 4*6 = 60
// ack legacy 20 + 4*[(22+14*8)/24] = 20 + 4*6 = 44
// ht aggr QoS data: 52, type 2 (data frame) sub-type 8 (1000) 19.5/28.9/39/57.8/65/72.2Mbps
// ack ht 36 + 4*[(22+32*8)/78] = 36 + 4*4 = 52
// ack legacy 20 + 4*[(22+32*8)/72] = 20 + 4*4 = 36
// ht aggr QoS data: 60, type 2 (data frame) sub-type 8 (1000) 13/14.4Mbps
// ack ht 36 + 4*[(22+32*8)/52] = 36 + 4*6 = 60
// ack legacy 20 + 4*[(22+32*8)/48] = 20 + 4*6 = 44
// ht and legacy rate mapping is ont one on one, instead it is modulation combined with coding rate
// modulate coding ht-mcs ht-n_dbps legacy-mcs legacy-n_dbps
// BPSK 1/2 0 26 4 24
// QPSK 1/2 1 52 6 48
// QPSK 3/4 2 78 7 72
// 16QAM 1/2 3 104 8 96
// 16QAM 3/4 4 156 9 144
// 64QAM 2/3 5 208 10 192
// 64QAM 3/4 6 234 11 216
// conclusion: duration is: assume ack/blk-ack uses legacy, plus SIFS
// other observation: ht always use QoS data, not data (sub-type)
// other observation: management/control frame always in non-ht
__le16 dur = 0;
u16 n_dbps;
int num_octet, num_ofdm_sym;
if (ieee80211_is_pspoll(frame_control)) {
dur = (aid|0xc000);
} else if (ieee80211_is_data_qos(frame_control) && (~(qos_hdr&IEEE80211_QOS_CTL_ACK_POLICY_NOACK))) {
rate_hw_value = (rate_hw_value>6?6:rate_hw_value);
n_dbps = (rate_hw_value==0?wifi_n_dbps_table[4]:wifi_n_dbps_table[rate_hw_value+5]);
num_octet = (use_ht_aggr?32:14); //32 bytes for compressed block ack; 14 bytes for normal ack
num_ofdm_sym = calc_n_ofdm(num_octet, n_dbps);
dur = sifs + 20 + 4*num_ofdm_sym; // 20us legacy preamble
// printk("%s gen_ht_duration_id: num_octet %d n_dbps %d num_ofdm_sym %d dur %d\n", sdr_compatible_str,
// num_octet, n_dbps, num_ofdm_sym, dur);
} else {
printk("%s openwifi_tx: WARNING gen_ht_duration_id wrong pkt type!\n", sdr_compatible_str);
}
return dur;
}
inline void report_pkt_loss_due_to_driver_drop(struct ieee80211_hw *dev, struct sk_buff *skb)
{
struct openwifi_priv *priv = dev->priv;
struct ieee80211_tx_info *info;
info = IEEE80211_SKB_CB(skb);
ieee80211_tx_info_clear_status(info);
info->status.rates[0].count = 1;
info->status.rates[1].idx = -1;
info->status.antenna = priv->runtime_tx_ant_cfg;
ieee80211_tx_status_irqsafe(dev, skb);
}
static void openwifi_tx(struct ieee80211_hw *dev,
struct ieee80211_tx_control *control,
struct sk_buff *skb)
{
struct openwifi_priv *priv = dev->priv;
unsigned long flags;
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
struct openwifi_ring *ring = NULL;
struct sk_buff *skb_new; // temp skb for internal use
struct ieee80211_tx_info *info_skipped;
dma_addr_t dma_mapping_addr;
unsigned int i, j, empty_bd_idx = 0;
u16 rate_signal_value, len_mpdu, len_psdu, num_dma_symbol, len_mpdu_delim_pad=0, num_byte_pad;
u32 num_dma_byte, addr1_low32, addr2_low32=0, addr3_low32=0, tx_config, cts_reg=0, phy_hdr_config;//, openofdm_state_history;
u16 addr1_high16, addr2_high16=0, addr3_high16=0, sc, seq_no=0, cts_duration=0, sifs, ack_duration=0, traffic_pkt_duration, n_dbps;
u8 cts_rate_hw_value=0, cts_rate_signal_value=0, rate_hw_value, pkt_need_ack, retry_limit_raw,use_short_gi,*dma_buf,retry_limit_hw_value,rc_flags,qos_hdr,prio,queue_idx,drv_ring_idx;
bool drv_seqno=false, use_rts_cts, use_cts_protect, ht_aggr_start=false, use_ht_rate, use_ht_aggr, cts_use_traffic_rate=false, force_use_cts_protect=false;
__le16 frame_control,duration_id;
u32 dma_fifo_no_room_flag, hw_queue_len, delay_count=0;
u16 aid = 0;
enum dma_status status;
static u32 addr1_low32_prev = -1;
static u8 rate_hw_value_prev = -1;
static u8 pkt_need_ack_prev = -1;
static u16 addr1_high16_prev = -1;
static __le16 duration_id_prev = -1;
static u8 prio_prev = -1;
static u8 retry_limit_raw_prev = -1;
static u8 use_short_gi_prev = -1;
// static bool led_status=0;
// struct gpio_led_data *led_dat = cdev_to_gpio_led_data(priv->led[3]);
// if ( (priv->phy_tx_sn&7) ==0 ) {
// openofdm_state_history = openofdm_rx_api->OPENOFDM_RX_REG_STATE_HISTORY_read();
// if (openofdm_state_history!=openofdm_state_history_old){
// led_status = (~led_status);
// openofdm_state_history_old = openofdm_state_history;
// gpiod_set_value(led_dat->gpiod, led_status);
// }
// }
if (skb->data_len>0) {// more data are not in linear data area skb->data
printk("%s openwifi_tx: WARNING skb->data_len>0\n", sdr_compatible_str);
goto openwifi_tx_early_out;
}
len_mpdu = skb->len;
// get Linux priority/queue setting info and target mac address
prio = skb_get_queue_mapping(skb);
if (prio >= MAX_NUM_HW_QUEUE) {
printk("%s openwifi_tx: WARNING prio%d\n", sdr_compatible_str, prio);
goto openwifi_tx_early_out;
}
addr1_low32 = *((u32*)(hdr->addr1+2));
// ---- DO your idea here! Map Linux/SW "prio" to driver "drv_ring_idx" (then 1on1 to FPGA queue_idx) ---
if (priv->slice_idx == 0xFFFFFFFF) {// use Linux default prio setting, if there isn't any slice config
drv_ring_idx = prio;
} else {// customized prio to drv_ring_idx mapping
// check current packet belonging to which slice/hw-queue
for (i=0; idest_mac_addr_queue_map[i] == addr1_low32 ) {
break;
}
}
drv_ring_idx = (i>=MAX_NUM_HW_QUEUE?prio:i); // if no address is hit
}
ring = &(priv->tx_ring[drv_ring_idx]);
spin_lock_irqsave(&priv->lock, flags);
if (ring->bds[ring->bd_wr_idx].seq_no != 0xffff) { // not cleared yet by interrupt
for (i=1; ibds[(ring->bd_wr_idx+i)&(NUM_TX_BD-1)].seq_no == 0xffff) {
empty_bd_idx = i;
break;
}
}
hw_queue_len = tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read();
if (empty_bd_idx) { // clear all bds before the empty bd and report failure to Linux
if (priv->stat.stat_enable) {
priv->stat.tx_prio_stop0_fake_num[prio]++;
priv->stat.tx_queue_stop0_fake_num[drv_ring_idx]++;
}
for (i=0; ibd_wr_idx+i)&(NUM_TX_BD-1) );
printk("%s openwifi_tx: WARNING fake stop queue empty_bd_idx%d i%d lnx prio%d map to q%d stop%d hwq len%d wr%d rd%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%u\n", sdr_compatible_str,
empty_bd_idx, i, prio, drv_ring_idx, ring->stop_flag, hw_queue_len, ring->bd_wr_idx, ring->bd_rd_idx, ring->bds[j].prio, ring->bds[j].len_mpdu, ring->bds[j].seq_no, ring->bds[j].skb_linked,(long long int)(ring->bds[j].dma_mapping_addr));
// tell Linux this skb failed
skb_new = ring->bds[j].skb_linked;
dma_unmap_single(priv->tx_chan->device->dev,ring->bds[j].dma_mapping_addr,
skb_new->len, DMA_MEM_TO_DEV);
info_skipped = IEEE80211_SKB_CB(skb_new);
ieee80211_tx_info_clear_status(info_skipped);
info_skipped->status.rates[0].count = 1;
info_skipped->status.rates[1].idx = -1;
info_skipped->status.antenna = priv->runtime_tx_ant_cfg;
ieee80211_tx_status_irqsafe(dev, skb_new);
ring->bds[j].prio = 0xff; // invalid value
ring->bds[j].len_mpdu = 0; // invalid value
ring->bds[j].seq_no = 0xffff;
ring->bds[j].skb_linked = NULL;
ring->bds[j].dma_mapping_addr = 0;
}
if (ring->stop_flag != -1) { //the interrupt seems will never come, we need to wake up the queue in case the interrupt will never wake it up
ieee80211_wake_queue(dev, ring->stop_flag);
ring->stop_flag = -1;
}
} else {
j = ring->bd_wr_idx;
printk("%s openwifi_tx: WARNING real stop queue lnx prio%d map to q%d stop%d hwq len%d wr%d rd%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%u\n", sdr_compatible_str,
prio, drv_ring_idx, ring->stop_flag, hw_queue_len, ring->bd_wr_idx, ring->bd_rd_idx, ring->bds[j].prio, ring->bds[j].len_mpdu, ring->bds[j].seq_no, ring->bds[j].skb_linked, (long long int)(ring->bds[j].dma_mapping_addr));
ieee80211_stop_queue(dev, prio); // here we should stop those prio related to the queue idx flag set in TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read
ring->stop_flag = prio;
if (priv->stat.stat_enable) {
priv->stat.tx_prio_stop0_real_num[prio]++;
priv->stat.tx_queue_stop0_real_num[drv_ring_idx]++;
}
spin_unlock_irqrestore(&priv->lock, flags);
goto openwifi_tx_early_out;
}
}
spin_unlock_irqrestore(&priv->lock, flags);
// -------------------- end of Map Linux/SW "prio" to driver "drv_ring_idx" ------------------
// get other info from packet header
addr1_high16 = *((u16*)(hdr->addr1));
if (len_mpdu>=20) {
addr2_low32 = *((u32*)(hdr->addr2+2));
addr2_high16 = *((u16*)(hdr->addr2));
}
if (len_mpdu>=26) {
addr3_low32 = *((u32*)(hdr->addr3+2));
addr3_high16 = *((u16*)(hdr->addr3));
}
frame_control=hdr->frame_control;
pkt_need_ack = (!(info->flags&IEEE80211_TX_CTL_NO_ACK));
retry_limit_raw = info->control.rates[0].count;
rc_flags = info->control.rates[0].flags;
use_rts_cts = ((rc_flags&IEEE80211_TX_RC_USE_RTS_CTS)!=0);
use_cts_protect = ((rc_flags&IEEE80211_TX_RC_USE_CTS_PROTECT)!=0);
use_ht_rate = ((rc_flags&IEEE80211_TX_RC_MCS)!=0);
use_short_gi = ((rc_flags&IEEE80211_TX_RC_SHORT_GI)!=0);
use_ht_aggr = ((info->flags&IEEE80211_TX_CTL_AMPDU)!=0);
qos_hdr = (*(ieee80211_get_qos_ctl(hdr)));
// get Linux rate (MCS) setting
rate_hw_value = ieee80211_get_tx_rate(dev, info)->hw_value;
// drv_tx_reg_val[DRV_TX_REG_IDX_RATE]
// override rate legacy: 4:6M, 5:9M, 6:12M, 7:18M, 8:24M, 9:36M, 10:48M, 11:54M
// drv_tx_reg_val[DRV_TX_REG_IDX_RATE_HT]
// override rate ht: 4:6.5M, 5:13M, 6:19.5M,7:26M, 8:39M, 9:52M, 10:58.5M, 11:65M
if ( ieee80211_is_data(hdr->frame_control) ) {//rate override command
if (use_ht_rate && priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE_HT]>0) {
rate_hw_value = (priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE_HT]&0xF)-4;
use_short_gi = ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE_HT]&0x10)==0x10);
} else if ((!use_ht_rate) && priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE]>0)
rate_hw_value = (priv->drv_tx_reg_val[DRV_TX_REG_IDX_RATE]&0xF);
// TODO: need to map rate_hw_value back to info->control.rates[0].idx!!!
}
// Workaround for a FPGA bug: if aggr happens on ht mcs 0, the tx core will never end, running eneless and stuck the low MAC!
if (use_ht_aggr && rate_hw_value==0)
rate_hw_value = 1;
// sifs = (priv->actual_rx_lo<2500?10:16);
sifs = 16; // for ofdm, sifs is always 16
if (control != NULL) { // get aid for gen_ht_duration_id only when control->sta is not NULL
if (control->sta != NULL) {
aid = control->sta->aid;
}
}
if (use_ht_rate) {
// printk("%s openwifi_tx: rate_hw_value %d aggr %d sifs %d\n", sdr_compatible_str, rate_hw_value, use_ht_aggr, sifs);
hdr->duration_id = gen_ht_duration_id(frame_control, aid, qos_hdr, use_ht_aggr, rate_hw_value, sifs); //linux only do it for 11a/g, not for 11n and later
}
duration_id = hdr->duration_id;
if (use_rts_cts)
printk("%s openwifi_tx: WARNING sn %d use_rts_cts is not supported!\n", sdr_compatible_str, ring->bd_wr_idx);
if (use_cts_protect) {
cts_rate_hw_value = ieee80211_get_rts_cts_rate(dev, info)->hw_value;
cts_duration = le16_to_cpu(ieee80211_ctstoself_duration(dev,info->control.vif,len_mpdu,info));
} else if (force_use_cts_protect) { // could override mac80211 setting here.
cts_rate_hw_value = 4; //wifi_mcs_table_11b_force_up[] translate it to 1011(6M)
if (pkt_need_ack)
ack_duration = 44;//assume the ack we wait use 6Mbps: 4*ceil((22+14*8)/24) + 20(preamble+SIGNAL)
n_dbps = (use_ht_rate?wifi_n_dbps_ht_table[rate_hw_value+4]:wifi_n_dbps_table[rate_hw_value]);
traffic_pkt_duration = (use_ht_rate?36:20) + 4*calc_n_ofdm(len_mpdu, n_dbps);
cts_duration = traffic_pkt_duration + sifs + pkt_need_ack*(sifs+ack_duration);
}
// this is 11b stuff
// if (info->flags&IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
// printk("%s openwifi_tx: WARNING IEEE80211_TX_RC_USE_SHORT_PREAMBLE\n", sdr_compatible_str);
if (len_mpdu>=28) {
if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
priv->seqno += 0x10;
drv_seqno = true;
}
hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
}
sc = hdr->seq_ctrl;
seq_no = (sc&IEEE80211_SCTL_SEQ)>>4;
}
// printk("%s openwifi_tx: rate&try: %d %d %03x; %d %d %03x; %d %d %03x; %d %d %03x\n", sdr_compatible_str,
// info->status.rates[0].idx,info->status.rates[0].count,info->status.rates[0].flags,
// info->status.rates[1].idx,info->status.rates[1].count,info->status.rates[1].flags,
// info->status.rates[2].idx,info->status.rates[2].count,info->status.rates[2].flags,
// info->status.rates[3].idx,info->status.rates[3].count,info->status.rates[3].flags);
// -----------end of preprocess some info from header and skb----------------
// /* HW will perform RTS-CTS when only RTS flags is set.
// * HW will perform CTS-to-self when both RTS and CTS flags are set.
// * RTS rate and RTS duration will be used also for CTS-to-self.
// */
// if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
// tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
// rts_duration = ieee80211_rts_duration(dev, priv->vif[0], // assume all vif have the same config
// len_mpdu, info);
// printk("%s openwifi_tx: rc_flags & IEEE80211_TX_RC_USE_RTS_CTS\n", sdr_compatible_str);
// } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
// tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
// rts_duration = ieee80211_ctstoself_duration(dev, priv->vif[0], // assume all vif have the same config
// len_mpdu, info);
// printk("%s openwifi_tx: rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT\n", sdr_compatible_str);
// }
if(use_ht_aggr)
{
if(ieee80211_is_data_qos(frame_control) == false)
{
printk("%s openwifi_tx: WARNING packet is not QoS packet!\n", sdr_compatible_str);
goto openwifi_tx_early_out;
}
// psdu = [ MPDU DEL | MPDU | CRC | MPDU padding ]
len_mpdu_delim_pad = ((len_mpdu + LEN_PHY_CRC)%4 == 0) ? 0 :(4 - (len_mpdu + LEN_PHY_CRC)%4);
len_psdu = LEN_MPDU_DELIM + len_mpdu + LEN_PHY_CRC + len_mpdu_delim_pad;
if( (addr1_low32 != addr1_low32_prev) || (addr1_high16 != addr1_high16_prev) || (duration_id != duration_id_prev) ||
(rate_hw_value != rate_hw_value_prev) || (use_short_gi != use_short_gi_prev) ||
(prio != prio_prev) || (retry_limit_raw != retry_limit_raw_prev) || (pkt_need_ack != pkt_need_ack_prev) )
{
addr1_low32_prev = addr1_low32;
addr1_high16_prev = addr1_high16;
duration_id_prev = duration_id;
rate_hw_value_prev = rate_hw_value;
use_short_gi_prev = use_short_gi;
prio_prev = prio;
retry_limit_raw_prev = retry_limit_raw;
pkt_need_ack_prev = pkt_need_ack;
ht_aggr_start = true;
}
}
else
{
// psdu = [ MPDU ]
len_psdu = len_mpdu;
// // Don't need to reset _prev variables every time when it is not ht aggr qos data. Reason:
// // 1. In 99.9999% cases, the ht always use qos data and goes to prio/queue_idx 2. By not resetting the variable to -1, we can have continuous aggregation packet operation in FPGA queue 2.
// // 2. In other words, the aggregation operation for queue 2 in FPGA won't be interrupted by other non aggregation packets (control/management/beacon/etc.) that go to queue 0 (or other queues than 2).
// // 3. From wired domain and upper level ( DSCP, AC (0~3), WMM management, 802.11D service classes and user priority (UP) ) to chip/FPGA queue index, thre should be some (complicated) mapping relationship.
// // 4. More decent design is setting these aggregation flags (ht_aggr_start) per queue/prio here in driver. But since now only queue 2 and 0 are used (data goes to queue 2, others go to queue 0) in normal (most) cases, let's not go to the decent (complicated) solution immediately.
// addr1_low32_prev = -1;
// addr1_high16_prev = -1;
// duration_id_prev = -1;
// use_short_gi_prev = -1;
// rate_hw_value_prev = -1;
// prio_prev = -1;
// retry_limit_raw_prev = -1;
// pkt_need_ack_prev = -1;
}
num_dma_symbol = (len_psdu>>TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS) + ((len_psdu&(TX_INTF_NUM_BYTE_PER_DMA_SYMBOL-1))!=0);
if ( ( (!pkt_need_ack)&&(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_BROADCAST) ) || ( (pkt_need_ack)&&(priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_UNICAST) ) )
printk("%s openwifi_tx: %dB RC%x %dM FC%04x DI%04x ADDR%04x%08x/%04x%08x/%04x%08x flag%08x QoS%02x SC%d_%d retr%d ack%d prio%d q%d wr%d rd%d\n", sdr_compatible_str,
len_mpdu, rc_flags, (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]),frame_control,duration_id,
reverse16(addr1_high16), reverse32(addr1_low32), reverse16(addr2_high16), reverse32(addr2_low32), reverse16(addr3_high16), reverse32(addr3_low32),
info->flags, qos_hdr, seq_no, drv_seqno, retry_limit_raw, pkt_need_ack, prio, drv_ring_idx,
// use_rts_cts,use_cts_protect|force_use_cts_protect,wifi_rate_all[cts_rate_hw_value],cts_duration,
ring->bd_wr_idx,ring->bd_rd_idx);
// check whether the packet is bigger than DMA buffer size
num_dma_byte = (num_dma_symbol< TX_BD_BUF_SIZE) {
printk("%s openwifi_tx: WARNING sn %d num_dma_byte > TX_BD_BUF_SIZE\n", sdr_compatible_str, ring->bd_wr_idx);
goto openwifi_tx_early_out;
}
// Copy MPDU delimiter and padding into sk_buff
if(use_ht_aggr)
{
// when skb does not have enough headroom, skb_push will cause kernel panic. headroom needs to be extended if necessary
if (skb_headroom(skb)bd_wr_idx, skb_headroom(skb), LEN_MPDU_DELIM);
if ((skb_new = skb_realloc_headroom(skb, LEN_MPDU_DELIM)) == NULL) {
printk("%s openwifi_tx: WARNING sn %d skb_realloc_headroom failed!\n", sdr_compatible_str, ring->bd_wr_idx);
goto openwifi_tx_early_out;
}
if (skb->sk != NULL)
skb_set_owner_w(skb_new, skb->sk);
dev_kfree_skb(skb);
skb = skb_new;
}
skb_push( skb, LEN_MPDU_DELIM );
dma_buf = skb->data;
// fill in MPDU delimiter
*((u16*)(dma_buf+0)) = ((u16)(len_mpdu+LEN_PHY_CRC) << 4) & 0xFFF0;
*((u8 *)(dma_buf+2)) = gen_mpdu_delim_crc(*((u16 *)dma_buf));
*((u8 *)(dma_buf+3)) = 0x4e;
// Extend sk_buff to hold CRC + MPDU padding + empty MPDU delimiter
num_byte_pad = num_dma_byte - (LEN_MPDU_DELIM + len_mpdu);
if (skb_tailroom(skb)bd_wr_idx, skb_tailroom(skb), num_byte_pad);
if ((skb_new = skb_copy_expand(skb, skb_headroom(skb), num_byte_pad, GFP_KERNEL)) == NULL) {
printk("%s openwifi_tx: WARNING(AGGR) sn %d skb_copy_expand failed!\n", sdr_compatible_str, ring->bd_wr_idx);
goto openwifi_tx_early_out;
}
if (skb->sk != NULL)
skb_set_owner_w(skb_new, skb->sk);
dev_kfree_skb(skb);
skb = skb_new;
}
skb_put( skb, num_byte_pad );
// fill in MPDU CRC
*((u32*)(dma_buf+LEN_MPDU_DELIM+len_mpdu)) = gen_mpdu_crc(dma_buf+LEN_MPDU_DELIM, len_mpdu);
// fill in MPDU delimiter padding
memset(dma_buf+LEN_MPDU_DELIM+len_mpdu+LEN_PHY_CRC, 0, len_mpdu_delim_pad);
// num_dma_byte is on 8-byte boundary and len_psdu is on 4 byte boundary.
// If they have different lengths, add "empty MPDU delimiter" for alignment
if(num_dma_byte == len_psdu + 4)
{
*((u32*)(dma_buf+len_psdu)) = 0x4e140000;
len_psdu = num_dma_byte;
}
}
else
{
// Extend sk_buff to hold padding
num_byte_pad = num_dma_byte - len_mpdu;
if (skb_tailroom(skb)bd_wr_idx, skb_tailroom(skb), num_byte_pad);
if ((skb_new = skb_copy_expand(skb, skb_headroom(skb), num_byte_pad, GFP_KERNEL)) == NULL) {
printk("%s openwifi_tx: WARNING sn %d skb_copy_expand failed!\n", sdr_compatible_str, ring->bd_wr_idx);
goto openwifi_tx_early_out;
}
if (skb->sk != NULL)
skb_set_owner_w(skb_new, skb->sk);
dev_kfree_skb(skb);
skb = skb_new;
}
skb_put( skb, num_byte_pad );
dma_buf = skb->data;
}
// for(i = 0; i <= num_dma_symbol; i++)
// printk("%16llx\n", (*(u64*)(&(dma_buf[i*8]))));
retry_limit_hw_value = ( retry_limit_raw==0?0:((retry_limit_raw - 1)&0xF) );
queue_idx = drv_ring_idx; // from driver ring idx to FPGA queue_idx mapping
if (use_cts_protect || force_use_cts_protect) {
rate_signal_value = (use_ht_rate ? rate_hw_value : wifi_mcs_table_11b_force_up[rate_hw_value]);
cts_rate_signal_value = wifi_mcs_table_11b_force_up[cts_rate_hw_value];
cts_reg = ((use_cts_protect|force_use_cts_protect)<<31 | cts_use_traffic_rate<<30 | cts_duration<<8 | cts_rate_signal_value<<4 | rate_signal_value);
}
phy_hdr_config = ( ht_aggr_start<<20 | rate_hw_value<<16 | use_ht_rate<<15 | use_short_gi<<14 | use_ht_aggr<<13 | len_psdu );
tx_config = ( prio<<26 | ring->bd_wr_idx<<20 | queue_idx<<18 | retry_limit_hw_value<<14 | pkt_need_ack<<13 | num_dma_symbol );
/* We must be sure that tx_flags is written last because the HW
* looks at it to check if the rest of data is valid or not
*/
//wmb();
// entry->flags = cpu_to_le32(tx_flags);
/* We must be sure this has been written before following HW
* register write, because this write will make the HW attempts
* to DMA the just-written data
*/
//wmb();
spin_lock_irqsave(&priv->lock, flags); // from now on, we'd better avoid interrupt because ring->stop_flag is shared with interrupt
// -------------check whether FPGA dma fifo and queue (queue_idx) has enough room-------------
dma_fifo_no_room_flag = tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read();
hw_queue_len = tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read();
if ( ((dma_fifo_no_room_flag>>queue_idx)&1) || ((NUM_TX_BD-((hw_queue_len>>(queue_idx*8))&0xFF))<=RING_ROOM_THRESHOLD) || ring->stop_flag>=0 ) {
if( priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG]&DMESG_LOG_NORMAL_QUEUE_STOP )
printk("%s openwifi_tx: WARNING ieee80211_stop_queue prio%d queue%d no room flag%x hwq len%08x request%d wr%d rd%d\n", sdr_compatible_str,
prio, queue_idx, dma_fifo_no_room_flag, hw_queue_len, num_dma_symbol, ring->bd_wr_idx, ring->bd_rd_idx);
ieee80211_stop_queue(dev, prio); // here we should stop those prio related to the queue idx flag set in TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read
ring->stop_flag = prio;
if (priv->stat.stat_enable) {
priv->stat.tx_prio_stop1_num[prio]++;
priv->stat.tx_queue_stop1_num[queue_idx]++;
}
// goto openwifi_tx_early_out_after_lock;
}
// --------end of check whether FPGA fifo (queue_idx) has enough room------------
status = dma_async_is_tx_complete(priv->tx_chan, priv->tx_cookie, NULL, NULL);
while(delay_count<100 && status!=DMA_COMPLETE) {
status = dma_async_is_tx_complete(priv->tx_chan, priv->tx_cookie, NULL, NULL);
delay_count++;
udelay(4);
// udelay(priv->stat.dbg_ch1);
}
if (status!=DMA_COMPLETE) {
printk("%s openwifi_tx: WARNING status!=DMA_COMPLETE\n", sdr_compatible_str);
goto openwifi_tx_early_out_after_lock;
}
//-------------------------fire skb DMA to hardware----------------------------------
dma_mapping_addr = dma_map_single(priv->tx_chan->device->dev, dma_buf,
num_dma_byte, DMA_MEM_TO_DEV);
if (dma_mapping_error(priv->tx_chan->device->dev,dma_mapping_addr)) {
// dev_err(priv->tx_chan->device->dev, "sdr,sdr openwifi_tx: WARNING TX DMA mapping error\n");
printk("%s openwifi_tx: WARNING sn %d TX DMA mapping error\n", sdr_compatible_str, ring->bd_wr_idx);
goto openwifi_tx_early_out_after_lock;
}
sg_init_table(&(priv->tx_sg), 1); // only need to be initialized once in openwifi_start
sg_dma_address( &(priv->tx_sg) ) = dma_mapping_addr;
sg_dma_len( &(priv->tx_sg) ) = num_dma_byte;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write(cts_reg);
tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config);
tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_write(phy_hdr_config);
priv->txd = priv->tx_chan->device->device_prep_slave_sg(priv->tx_chan, &(priv->tx_sg),1,DMA_MEM_TO_DEV, DMA_CTRL_ACK | DMA_PREP_INTERRUPT, NULL);
if (!(priv->txd)) {
printk("%s openwifi_tx: WARNING sn %d device_prep_slave_sg %p\n", sdr_compatible_str, ring->bd_wr_idx, (void*)(priv->txd));
goto openwifi_tx_after_dma_mapping;
}
priv->tx_cookie = priv->txd->tx_submit(priv->txd);
if (dma_submit_error(priv->tx_cookie)) {
printk("%s openwifi_tx: WARNING sn %d dma_submit_error(tx_cookie) %d\n", sdr_compatible_str, ring->bd_wr_idx, (u32)(priv->tx_cookie));
goto openwifi_tx_after_dma_mapping;
}
// seems everything is ok. let's mark this pkt in bd descriptor ring
ring->bds[ring->bd_wr_idx].prio = prio;
ring->bds[ring->bd_wr_idx].len_mpdu = len_mpdu;
ring->bds[ring->bd_wr_idx].seq_no = seq_no;
ring->bds[ring->bd_wr_idx].skb_linked = skb;
ring->bds[ring->bd_wr_idx].dma_mapping_addr = dma_mapping_addr;
ring->bd_wr_idx = ((ring->bd_wr_idx+1)&(NUM_TX_BD-1));
dma_async_issue_pending(priv->tx_chan);
spin_unlock_irqrestore(&priv->lock, flags);
if (priv->stat.stat_enable) {
priv->stat.tx_prio_num[prio]++;
priv->stat.tx_queue_num[queue_idx]++;
}
return;
openwifi_tx_after_dma_mapping:
dma_unmap_single(priv->tx_chan->device->dev, dma_mapping_addr, num_dma_byte, DMA_MEM_TO_DEV);
openwifi_tx_early_out_after_lock:
spin_unlock_irqrestore(&priv->lock, flags);
report_pkt_loss_due_to_driver_drop(dev, skb);
// dev_kfree_skb(skb);
// printk("%s openwifi_tx: WARNING openwifi_tx_after_dma_mapping phy_tx_sn %d queue %d\n", sdr_compatible_str,priv->phy_tx_sn,queue_idx);
return;
openwifi_tx_early_out:
report_pkt_loss_due_to_driver_drop(dev, skb);
// dev_kfree_skb(skb);
// printk("%s openwifi_tx: WARNING openwifi_tx_early_out phy_tx_sn %d queue %d\n", sdr_compatible_str,priv->phy_tx_sn,queue_idx);
}
static int openwifi_set_antenna(struct ieee80211_hw *dev, u32 tx_ant, u32 rx_ant)
{
struct openwifi_priv *priv = dev->priv;
u8 fpga_tx_ant_setting, target_rx_ant;
u32 atten_mdb_tx0, atten_mdb_tx1;
struct ctrl_outs_control ctrl_out;
int ret;
printk("%s openwifi_set_antenna: tx_ant%d rx_ant%d\n",sdr_compatible_str,tx_ant,rx_ant);
if (tx_ant >= 4 || tx_ant == 0) {
return -EINVAL;
} else if (rx_ant >= 3 || rx_ant == 0) {
return -EINVAL;
}
fpga_tx_ant_setting = ((tx_ant<=2)?(tx_ant):(tx_ant+16));
target_rx_ant = ((rx_ant&1)?0:1);
// try rf chip setting firstly, only update internal state variable when rf chip succeed
atten_mdb_tx0 = ((tx_ant&1)?(AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]):AD9361_RADIO_OFF_TX_ATT);
atten_mdb_tx1 = ((tx_ant&2)?(AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]):AD9361_RADIO_OFF_TX_ATT);
ret = ad9361_set_tx_atten(priv->ad9361_phy, atten_mdb_tx0, true, false, true);
if (ret < 0) {
printk("%s openwifi_set_antenna: WARNING ad9361_set_tx_atten ant0 %d FAIL!\n",sdr_compatible_str, atten_mdb_tx0);
return -EINVAL;
} else {
printk("%s openwifi_set_antenna: ad9361_set_tx_atten ant0 %d OK\n",sdr_compatible_str, atten_mdb_tx0);
}
ret = ad9361_set_tx_atten(priv->ad9361_phy, atten_mdb_tx1, false, true, true);
if (ret < 0) {
printk("%s openwifi_set_antenna: WARNING ad9361_set_tx_atten ant1 %d FAIL!\n",sdr_compatible_str, atten_mdb_tx1);
return -EINVAL;
} else {
printk("%s openwifi_set_antenna: ad9361_set_tx_atten ant1 %d OK\n",sdr_compatible_str, atten_mdb_tx1);
}
ctrl_out.en_mask = priv->ctrl_out.en_mask;
ctrl_out.index = (target_rx_ant==0?AD9361_CTRL_OUT_INDEX_ANT0:AD9361_CTRL_OUT_INDEX_ANT1);
ret = ad9361_ctrl_outs_setup(priv->ad9361_phy, &(ctrl_out));
if (ret < 0) {
printk("%s openwifi_set_antenna: WARNING ad9361_ctrl_outs_setup en_mask 0x%02x index 0x%02x FAIL!\n",sdr_compatible_str, ctrl_out.en_mask, ctrl_out.index);
return -EINVAL;
} else {
printk("%s openwifi_set_antenna: ad9361_ctrl_outs_setup en_mask 0x%02x index 0x%02x\n",sdr_compatible_str, ctrl_out.en_mask, ctrl_out.index);
}
tx_intf_api->TX_INTF_REG_ANT_SEL_write(fpga_tx_ant_setting);
ret = tx_intf_api->TX_INTF_REG_ANT_SEL_read();
if (ret != fpga_tx_ant_setting) {
printk("%s openwifi_set_antenna: WARNING TX_INTF_REG_ANT_SEL_write target %d read back %d\n",sdr_compatible_str, fpga_tx_ant_setting, ret);
return -EINVAL;
} else {
printk("%s openwifi_set_antenna: TX_INTF_REG_ANT_SEL_write value %d\n",sdr_compatible_str, ret);
}
rx_intf_api->RX_INTF_REG_ANT_SEL_write(target_rx_ant);
ret = rx_intf_api->RX_INTF_REG_ANT_SEL_read();
if (ret != target_rx_ant) {
printk("%s openwifi_set_antenna: WARNING RX_INTF_REG_ANT_SEL_write target %d read back %d\n",sdr_compatible_str, target_rx_ant, ret);
return -EINVAL;
} else {
printk("%s openwifi_set_antenna: RX_INTF_REG_ANT_SEL_write value %d\n",sdr_compatible_str, ret);
}
// update internal state variable
priv->runtime_tx_ant_cfg = tx_ant;
priv->runtime_rx_ant_cfg = rx_ant;
if (TX_OFFSET_TUNING_ENABLE)
priv->tx_intf_cfg = ((tx_ant&1)?TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0:TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1);//NO USE
else {
if (tx_ant == 3)
priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH;
else
priv->tx_intf_cfg = ((tx_ant&1)?TX_INTF_BW_20MHZ_AT_0MHZ_ANT0:TX_INTF_BW_20MHZ_AT_0MHZ_ANT1);
}
priv->rx_intf_cfg = (target_rx_ant==0?RX_INTF_BW_20MHZ_AT_0MHZ_ANT0:RX_INTF_BW_20MHZ_AT_0MHZ_ANT1);
priv->ctrl_out.index=ctrl_out.index;
priv->tx_freq_offset_to_lo_MHz = tx_intf_fo_mapping[priv->tx_intf_cfg];
priv->rx_freq_offset_to_lo_MHz = rx_intf_fo_mapping[priv->rx_intf_cfg];
return 0;
}
static int openwifi_get_antenna(struct ieee80211_hw *dev, u32 *tx_ant, u32 *rx_ant)
{
struct openwifi_priv *priv = dev->priv;
*tx_ant = priv->runtime_tx_ant_cfg;
*rx_ant = priv->runtime_rx_ant_cfg;
printk("%s openwifi_get_antenna: tx_ant%d rx_ant%d\n",sdr_compatible_str, *tx_ant, *rx_ant);
printk("%s openwifi_get_antenna: drv tx cfg %d offset %d drv rx cfg %d offset %d drv ctrl_out sel %x\n",sdr_compatible_str,
priv->tx_intf_cfg, priv->tx_freq_offset_to_lo_MHz, priv->rx_intf_cfg, priv->rx_freq_offset_to_lo_MHz, priv->ctrl_out.index);
printk("%s openwifi_get_antenna: fpga tx sel %d rx sel %d\n", sdr_compatible_str,
tx_intf_api->TX_INTF_REG_ANT_SEL_read(), rx_intf_api->RX_INTF_REG_ANT_SEL_read());
printk("%s openwifi_get_antenna: rf tx att0 %d tx att1 %d ctrl_out sel %x\n", sdr_compatible_str,
ad9361_get_tx_atten(priv->ad9361_phy, 1), ad9361_get_tx_atten(priv->ad9361_phy, 2), ad9361_spi_read(priv->ad9361_phy->spi, REG_CTRL_OUTPUT_POINTER));
return 0;
}
static int openwifi_start(struct ieee80211_hw *dev)
{
struct openwifi_priv *priv = dev->priv;
int ret, i;
u32 reg;
for (i=0; ivif[i] = NULL;
}
// //keep software registers persistent between NIC down and up for multiple times
/*memset(priv->drv_tx_reg_val, 0, sizeof(priv->drv_tx_reg_val));
memset(priv->drv_rx_reg_val, 0, sizeof(priv->drv_rx_reg_val));
memset(priv->drv_xpu_reg_val, 0, sizeof(priv->drv_xpu_reg_val));
memset(priv->rf_reg_val,0,sizeof(priv->rf_reg_val));
priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_GIT_REV] = GIT_REV;*/
//turn on radio
openwifi_set_antenna(dev, priv->runtime_tx_ant_cfg, priv->runtime_rx_ant_cfg);
reg = ad9361_get_tx_atten(priv->ad9361_phy, ((priv->runtime_tx_ant_cfg==1 || priv->runtime_tx_ant_cfg==3)?1:2));
if (reg == (AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT])) {
priv->rfkill_off = 1;// 0 off, 1 on
printk("%s openwifi_start: rfkill radio on\n",sdr_compatible_str);
}
else
printk("%s openwifi_start: WARNING rfkill radio on failed. tx att read %d require %d\n",sdr_compatible_str, reg, AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]);
rx_intf_api->hw_init(priv->rx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type);
openofdm_tx_api->hw_init(priv->openofdm_tx_cfg);
openofdm_rx_api->hw_init(priv->openofdm_rx_cfg);
xpu_api->hw_init(priv->xpu_cfg);
xpu_api->XPU_REG_MAC_ADDR_write(priv->mac_addr);
printk("%s openwifi_start: rx_intf_cfg %d openofdm_rx_cfg %d tx_intf_cfg %d openofdm_tx_cfg %d\n",sdr_compatible_str, priv->rx_intf_cfg, priv->openofdm_rx_cfg, priv->tx_intf_cfg, priv->openofdm_tx_cfg);
printk("%s openwifi_start: rx_freq_offset_to_lo_MHz %d tx_freq_offset_to_lo_MHz %d\n",sdr_compatible_str, priv->rx_freq_offset_to_lo_MHz, priv->tx_freq_offset_to_lo_MHz);
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable tx interrupt
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); // disable rx interrupt by interrupt test mode
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status
// priv->rx_chan = dma_request_slave_channel(&(priv->pdev->dev), "rx_dma_s2mm");
priv->rx_chan = dma_request_chan(&(priv->pdev->dev), "rx_dma_s2mm");
if (IS_ERR(priv->rx_chan) || priv->rx_chan==NULL) {
ret = PTR_ERR(priv->rx_chan);
if (ret != -EPROBE_DEFER) {
pr_err("%s openwifi_start: No Rx channel ret %d priv->rx_chan 0x%p\n",sdr_compatible_str, ret, priv->rx_chan);
goto err_dma;
}
}
// priv->tx_chan = dma_request_slave_channel(&(priv->pdev->dev), "tx_dma_mm2s");
priv->tx_chan = dma_request_chan(&(priv->pdev->dev), "tx_dma_mm2s");
if (IS_ERR(priv->tx_chan) || priv->tx_chan==NULL) {
ret = PTR_ERR(priv->tx_chan);
if (ret != -EPROBE_DEFER) {
pr_err("%s openwifi_start: No Tx channel ret %d priv->tx_chan 0x%p\n",sdr_compatible_str, ret, priv->tx_chan);
goto err_dma;
}
}
printk("%s openwifi_start: DMA channel setup successfully. priv->rx_chan 0x%p priv->tx_chan 0x%p\n",sdr_compatible_str, priv->rx_chan, priv->tx_chan);
ret = openwifi_init_rx_ring(priv);
if (ret) {
printk("%s openwifi_start: openwifi_init_rx_ring ret %d\n", sdr_compatible_str,ret);
goto err_free_rings;
}
priv->seqno=0;
for (i=0; iirq_rx = irq_of_parse_and_map(priv->pdev->dev.of_node, 1);
ret = request_irq(priv->irq_rx, openwifi_rx_interrupt,
IRQF_SHARED, "sdr,rx_pkt_intr", dev);
if (ret) {
wiphy_err(dev->wiphy, "openwifi_start:failed to register IRQ handler openwifi_rx_interrupt\n");
goto err_free_rings;
} else {
printk("%s openwifi_start: irq_rx %d\n", sdr_compatible_str, priv->irq_rx);
}
priv->irq_tx = irq_of_parse_and_map(priv->pdev->dev.of_node, 3);
ret = request_irq(priv->irq_tx, openwifi_tx_interrupt,
IRQF_SHARED, "sdr,tx_itrpt", dev);
if (ret) {
wiphy_err(dev->wiphy, "openwifi_start: failed to register IRQ handler openwifi_tx_interrupt\n");
goto err_free_rings;
} else {
printk("%s openwifi_start: irq_tx %d\n", sdr_compatible_str, priv->irq_tx);
}
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000); // enable rx interrupt get normal fcs valid pass through ddc to ARM
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4); //enable tx interrupt
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(0); // release M AXIS
xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0); // reset tsf timer
priv->stat.csma_cfg0 = xpu_api->XPU_REG_FORCE_IDLE_MISC_read();
// disable ad9361 auto calibration and enable openwifi fpga spi control
priv->ad9361_phy->state->auto_cal_en = false; // turn off auto Tx quadrature calib.
priv->ad9361_phy->state->manual_tx_quad_cal_en = true; // turn on manual Tx quadrature calib.
xpu_api->XPU_REG_SPI_DISABLE_write(0);
// normal_out:
printk("%s openwifi_start: normal end\n", sdr_compatible_str);
return 0;
err_free_rings:
openwifi_free_rx_ring(priv);
for (i=0; ipriv;
u32 reg, reg1;
int i;
// enable ad9361 auto calibration and disable openwifi fpga spi control
priv->ad9361_phy->state->auto_cal_en = true; // turn on auto Tx quadrature calib.
priv->ad9361_phy->state->manual_tx_quad_cal_en = false; // turn off manual Tx quadrature calib.
xpu_api->XPU_REG_SPI_DISABLE_write(1);
//turn off radio
#if 1
ad9361_tx_mute(priv->ad9361_phy, 1);
reg = ad9361_get_tx_atten(priv->ad9361_phy, 2);
reg1 = ad9361_get_tx_atten(priv->ad9361_phy, 1);
if (reg == AD9361_RADIO_OFF_TX_ATT && reg1 == AD9361_RADIO_OFF_TX_ATT ) {
priv->rfkill_off = 0;// 0 off, 1 on
printk("%s openwifi_stop: rfkill radio off\n",sdr_compatible_str);
}
else
printk("%s openwifi_stop: WARNING rfkill radio off failed. tx att read %d %d require %d\n",sdr_compatible_str, reg, reg1, AD9361_RADIO_OFF_TX_ATT);
#endif
//ieee80211_stop_queue(dev, 0);
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable tx interrupt
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); // disable fcs_valid by interrupt test mode
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status
for (i=0; ivif[i] = NULL;
}
openwifi_free_rx_ring(priv);
for (i=0; irx_chan));
dmaengine_terminate_all(priv->rx_chan);
dma_release_channel(priv->rx_chan);
pr_info("%s openwifi_stop: dropped channel %s\n", sdr_compatible_str, dma_chan_name(priv->tx_chan));
dmaengine_terminate_all(priv->tx_chan);
dma_release_channel(priv->tx_chan);
//priv->rf->stop(dev);
free_irq(priv->irq_rx, dev);
free_irq(priv->irq_tx, dev);
// normal_out:
printk("%s openwifi_stop\n", sdr_compatible_str);
}
static u64 openwifi_get_tsf(struct ieee80211_hw *dev,
struct ieee80211_vif *vif)
{
u32 tsft_low, tsft_high;
tsft_low = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();
tsft_high = xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read();
//printk("%s openwifi_get_tsf: %08x%08x\n", sdr_compatible_str,tsft_high,tsft_low);
return( ( (u64)tsft_low ) | ( ((u64)tsft_high)<<32 ) );
}
static void openwifi_set_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u64 tsf)
{
u32 tsft_high = ((tsf >> 32)&0xffffffff);
u32 tsft_low = (tsf&0xffffffff);
xpu_api->XPU_REG_TSF_LOAD_VAL_write(tsft_high,tsft_low);
printk("%s openwifi_set_tsf: %08x%08x\n", sdr_compatible_str,tsft_high,tsft_low);
}
static void openwifi_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
{
xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0);
printk("%s openwifi_reset_tsf\n", sdr_compatible_str);
}
static int openwifi_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
{
printk("%s openwifi_set_rts_threshold WARNING value %d\n", sdr_compatible_str,value);
return(0);
}
static void openwifi_beacon_work(struct work_struct *work)
{
struct openwifi_vif *vif_priv =
container_of(work, struct openwifi_vif, beacon_work.work);
struct ieee80211_vif *vif =
container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
struct ieee80211_hw *dev = vif_priv->dev;
struct ieee80211_mgmt *mgmt;
struct sk_buff *skb;
/* don't overflow the tx ring */
if (ieee80211_queue_stopped(dev, 0))
goto resched;
/* grab a fresh beacon */
skb = ieee80211_beacon_get(dev, vif);
if (!skb)
goto resched;
/*
* update beacon timestamp w/ TSF value
* TODO: make hardware update beacon timestamp
*/
mgmt = (struct ieee80211_mgmt *)skb->data;
mgmt->u.beacon.timestamp = cpu_to_le64(openwifi_get_tsf(dev, vif));
/* TODO: use actual beacon queue */
skb_set_queue_mapping(skb, 0);
openwifi_tx(dev, NULL, skb);
resched:
/*
* schedule next beacon
* TODO: use hardware support for beacon timing
*/
schedule_delayed_work(&vif_priv->beacon_work, usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
// printk("%s openwifi_beacon_work beacon_int %d\n", sdr_compatible_str, vif->bss_conf.beacon_int);
}
static int openwifi_add_interface(struct ieee80211_hw *dev,
struct ieee80211_vif *vif)
{
int i;
struct openwifi_priv *priv = dev->priv;
struct openwifi_vif *vif_priv;
switch (vif->type) {
case NL80211_IFTYPE_AP:
case NL80211_IFTYPE_STATION:
case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_MONITOR:
case NL80211_IFTYPE_MESH_POINT:
break;
default:
return -EOPNOTSUPP;
}
// let's support more than 1 interface
for (i=0; ivif[i] == NULL)
break;
}
printk("%s openwifi_add_interface start. vif for loop result %d\n", sdr_compatible_str, i);
if (i==MAX_NUM_VIF)
return -EBUSY;
priv->vif[i] = vif;
/* Initialize driver private area */
vif_priv = (struct openwifi_vif *)&vif->drv_priv;
vif_priv->idx = i;
vif_priv->dev = dev;
INIT_DELAYED_WORK(&vif_priv->beacon_work, openwifi_beacon_work);
vif_priv->enable_beacon = false;
priv->mac_addr[0] = vif->addr[0];
priv->mac_addr[1] = vif->addr[1];
priv->mac_addr[2] = vif->addr[2];
priv->mac_addr[3] = vif->addr[3];
priv->mac_addr[4] = vif->addr[4];
priv->mac_addr[5] = vif->addr[5];
xpu_api->XPU_REG_MAC_ADDR_write(priv->mac_addr); // set mac addr in fpga
printk("%s openwifi_add_interface end with vif idx %d addr %02x:%02x:%02x:%02x:%02x:%02x\n", sdr_compatible_str,vif_priv->idx,
vif->addr[0],vif->addr[1],vif->addr[2],vif->addr[3],vif->addr[4],vif->addr[5]);
return 0;
}
static void openwifi_remove_interface(struct ieee80211_hw *dev,
struct ieee80211_vif *vif)
{
struct openwifi_vif *vif_priv;
struct openwifi_priv *priv = dev->priv;
vif_priv = (struct openwifi_vif *)&vif->drv_priv;
priv->vif[vif_priv->idx] = NULL;
printk("%s openwifi_remove_interface vif idx %d\n", sdr_compatible_str, vif_priv->idx);
}
static int openwifi_config(struct ieee80211_hw *dev, u32 changed)
{
struct openwifi_priv *priv = dev->priv;
struct ieee80211_conf *conf = &dev->conf;
static struct ieee80211_conf channel_conf_tmp;
static struct ieee80211_channel channel_tmp;
channel_conf_tmp.chandef.chan = (&channel_tmp);
if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
if ( priv->stat.restrict_freq_mhz>0 && (conf->chandef.chan->center_freq != priv->stat.restrict_freq_mhz) ) {
printk("%s openwifi_config avoid Linux requested freq %dMHz (restrict freq %dMHz)\n", sdr_compatible_str,
conf->chandef.chan->center_freq, priv->stat.restrict_freq_mhz);
channel_conf_tmp.chandef.chan->center_freq = priv->stat.restrict_freq_mhz;
priv->rf->set_chan(dev, &channel_conf_tmp);
} else {
priv->rf->set_chan(dev, conf);
}
} else
printk("%s openwifi_config changed flag %08x\n", sdr_compatible_str, changed);
return 0;
}
static void openwifi_bss_info_changed(struct ieee80211_hw *dev,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *info,
u32 changed)
{
struct openwifi_priv *priv = dev->priv;
struct openwifi_vif *vif_priv;
u32 bssid_low, bssid_high;
vif_priv = (struct openwifi_vif *)&vif->drv_priv;
//be careful: we don have valid chip, so registers addresses in priv->map->BSSID[0] are not valid! should not print it!
//printk("%s openwifi_bss_info_changed map bssid %02x%02x%02x%02x%02x%02x\n",sdr_compatible_str,priv->map->BSSID[0],priv->map->BSSID[1],priv->map->BSSID[2],priv->map->BSSID[3],priv->map->BSSID[4],priv->map->BSSID[5]);
if (changed & BSS_CHANGED_BSSID) {
printk("%s openwifi_bss_info_changed BSS_CHANGED_BSSID %02x%02x%02x%02x%02x%02x\n",sdr_compatible_str,info->bssid[0],info->bssid[1],info->bssid[2],info->bssid[3],info->bssid[4],info->bssid[5]);
// write new bssid to our HW, and do not change bssid filter
//u32 bssid_filter_high = xpu_api->XPU_REG_BSSID_FILTER_HIGH_read();
bssid_low = ( *( (u32*)(info->bssid) ) );
bssid_high = ( *( (u16*)(info->bssid+4) ) );
//bssid_filter_high = (bssid_filter_high&0x80000000);
//bssid_high = (bssid_high|bssid_filter_high);
xpu_api->XPU_REG_BSSID_FILTER_LOW_write(bssid_low);
xpu_api->XPU_REG_BSSID_FILTER_HIGH_write(bssid_high);
}
if (changed & BSS_CHANGED_BEACON_INT) {
printk("%s openwifi_bss_info_changed WARNING BSS_CHANGED_BEACON_INT %x\n",sdr_compatible_str,info->beacon_int);
}
if (changed & BSS_CHANGED_TXPOWER)
printk("%s openwifi_bss_info_changed WARNING BSS_CHANGED_TXPOWER %x\n",sdr_compatible_str,info->txpower);
if (changed & BSS_CHANGED_ERP_CTS_PROT)
printk("%s openwifi_bss_info_changed WARNING BSS_CHANGED_ERP_CTS_PROT %x\n",sdr_compatible_str,info->use_cts_prot);
if (changed & BSS_CHANGED_BASIC_RATES)
printk("%s openwifi_bss_info_changed WARNING BSS_CHANGED_BASIC_RATES %x\n",sdr_compatible_str,info->basic_rates);
if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
printk("%s openwifi_bss_info_changed WARNING BSS_CHANGED_ERP_SLOT %d BSS_CHANGED_ERP_PREAMBLE %d short slot %d\n",sdr_compatible_str,
changed&BSS_CHANGED_ERP_SLOT,changed&BSS_CHANGED_ERP_PREAMBLE,info->use_short_slot);
if (info->use_short_slot && priv->use_short_slot==false) {
priv->use_short_slot=true;
xpu_api->XPU_REG_BAND_CHANNEL_write( (priv->use_short_slot<<24)|(priv->band<<16)|priv->actual_rx_lo );
} else if ((!info->use_short_slot) && priv->use_short_slot==true) {
priv->use_short_slot=false;
xpu_api->XPU_REG_BAND_CHANNEL_write( (priv->use_short_slot<<24)|(priv->band<<16)|priv->actual_rx_lo );
}
}
if (changed & BSS_CHANGED_BEACON_ENABLED) {
printk("%s openwifi_bss_info_changed WARNING BSS_CHANGED_BEACON_ENABLED\n",sdr_compatible_str);
vif_priv->enable_beacon = info->enable_beacon;
}
if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
cancel_delayed_work_sync(&vif_priv->beacon_work);
if (vif_priv->enable_beacon) {
schedule_work(&vif_priv->beacon_work.work);
printk("%s openwifi_bss_info_changed WARNING enable_beacon\n",sdr_compatible_str);
}
printk("%s openwifi_bss_info_changed WARNING BSS_CHANGED_BEACON_ENABLED %d BSS_CHANGED_BEACON %d\n",sdr_compatible_str,
changed&BSS_CHANGED_BEACON_ENABLED,changed&BSS_CHANGED_BEACON);
}
}
// helper function
u32 log2val(u32 val){
u32 ret_val = 0 ;
while(val>1){
val = val >> 1 ;
ret_val ++ ;
}
return ret_val ;
}
static int openwifi_conf_tx(struct ieee80211_hw *dev, struct ieee80211_vif *vif, u16 queue,
const struct ieee80211_tx_queue_params *params)
{
struct openwifi_priv *priv = dev->priv;
u32 reg_val, cw_min_exp, cw_max_exp;
if (priv->stat.cw_max_min_cfg == 0) {
printk("%s openwifi_conf_tx: [queue %d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d, aifs and txop ignored\n",
sdr_compatible_str,queue,params->aifs,params->cw_min,params->cw_max,params->txop);
reg_val=xpu_api->XPU_REG_CSMA_CFG_read();
cw_min_exp = (log2val(params->cw_min + 1) & 0x0F);
cw_max_exp = (log2val(params->cw_max + 1) & 0x0F);
switch(queue){
case 0: reg_val = ( (reg_val & 0xFFFFFF00) | ((cw_min_exp | (cw_max_exp << 4)) << 0) ); break;
case 1: reg_val = ( (reg_val & 0xFFFF00FF) | ((cw_min_exp | (cw_max_exp << 4)) << 8) ); break;
case 2: reg_val = ( (reg_val & 0xFF00FFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 16) ); break;
case 3: reg_val = ( (reg_val & 0x00FFFFFF) | ((cw_min_exp | (cw_max_exp << 4)) << 24) ); break;
default: printk("%s openwifi_conf_tx: WARNING queue %d does not exist",sdr_compatible_str, queue); return(0);
}
} else {
reg_val = priv->stat.cw_max_min_cfg;
printk("%s openwifi_conf_tx: override cw max min for q3 to q0: %d %d; %d %d; %d %d; %d %d\n",
sdr_compatible_str,
(1<<((reg_val>>28)&0xF))-1,
(1<<((reg_val>>24)&0xF))-1,
(1<<((reg_val>>20)&0xF))-1,
(1<<((reg_val>>16)&0xF))-1,
(1<<((reg_val>>12)&0xF))-1,
(1<<((reg_val>> 8)&0xF))-1,
(1<<((reg_val>> 4)&0xF))-1,
(1<<((reg_val>> 0)&0xF))-1);
}
xpu_api->XPU_REG_CSMA_CFG_write(reg_val);
return(0);
}
static u64 openwifi_prepare_multicast(struct ieee80211_hw *dev,
struct netdev_hw_addr_list *mc_list)
{
printk("%s openwifi_prepare_multicast\n", sdr_compatible_str);
return netdev_hw_addr_list_count(mc_list);
}
static void openwifi_configure_filter(struct ieee80211_hw *dev,
unsigned int changed_flags,
unsigned int *total_flags,
u64 multicast)
{
struct openwifi_priv *priv = dev->priv;
u32 filter_flag;
(*total_flags) &= SDR_SUPPORTED_FILTERS;
(*total_flags) |= FIF_ALLMULTI; //because we need to pass all multicast (no matter it is for us or not) to upper layer
filter_flag = (*total_flags);
filter_flag = (filter_flag|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO);
//filter_flag = (filter_flag|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MONITOR_ALL); // all pkt will be delivered to arm
//if (priv->vif[0]->type == NL80211_IFTYPE_MONITOR)
if ((filter_flag&0xf0) == 0xf0) //FIF_BCN_PRBRESP_PROMISC/FIF_CONTROL/FIF_OTHER_BSS/FIF_PSPOLL are set means monitor mode
filter_flag = (filter_flag|MONITOR_ALL);
else
filter_flag = (filter_flag&(~MONITOR_ALL));
if ( !(filter_flag&FIF_BCN_PRBRESP_PROMISC) )
filter_flag = (filter_flag|MY_BEACON);
filter_flag = (filter_flag|FIF_PSPOLL);
if (priv->stat.rx_monitor_all)
filter_flag = (filter_flag|MONITOR_ALL);
xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag|HIGH_PRIORITY_DISCARD_FLAG);
//xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag); //do not discard any pkt
printk("%s openwifi_configure_filter MON %d M_BCN %d BST0 %d BST1 %d UST %d PB_RQ %d PS_PL %d O_BSS %d CTL %d BCN_PRP %d PCP_FL %d FCS_FL %d ALL_MUT %d\n", sdr_compatible_str,
(filter_flag>>13)&1,(filter_flag>>12)&1,(filter_flag>>11)&1,(filter_flag>>10)&1,(filter_flag>>9)&1,(filter_flag>>8)&1,(filter_flag>>7)&1,(filter_flag>>6)&1,(filter_flag>>5)&1,(filter_flag>>4)&1,(filter_flag>>3)&1,(filter_flag>>2)&1,(filter_flag>>1)&1);
}
static int openwifi_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_ampdu_params *params)
{
struct ieee80211_sta *sta = params->sta;
enum ieee80211_ampdu_mlme_action action = params->action;
// struct openwifi_priv *priv = hw->priv;
u16 max_tx_bytes, buf_size;
u32 ampdu_action_config;
if (!AGGR_ENABLE) {
return -EOPNOTSUPP;
}
switch (action)
{
case IEEE80211_AMPDU_TX_START:
ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, params->tid);
printk("%s openwifi_ampdu_action: start TX aggregation. tid %d\n", sdr_compatible_str, params->tid);
break;
case IEEE80211_AMPDU_TX_STOP_CONT:
case IEEE80211_AMPDU_TX_STOP_FLUSH:
case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, params->tid);
printk("%s openwifi_ampdu_action: stop TX aggregation. tid %d\n", sdr_compatible_str, params->tid);
break;
case IEEE80211_AMPDU_TX_OPERATIONAL:
buf_size = 4;
// buf_size = (params->buf_size) - 1;
max_tx_bytes = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + sta->ht_cap.ampdu_factor)) - 1;
ampdu_action_config = ( sta->ht_cap.ampdu_density<<24 | buf_size<<16 | max_tx_bytes );
tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_write(ampdu_action_config);
printk("%s openwifi_ampdu_action: TX operational. tid %d max_tx_bytes %d ampdu_density %d buf_size %d\n",
sdr_compatible_str, params->tid, max_tx_bytes, sta->ht_cap.ampdu_density, buf_size);
break;
case IEEE80211_AMPDU_RX_START:
printk("%s openwifi_ampdu_action: start RX aggregation. tid %d\n", sdr_compatible_str, params->tid);
break;
case IEEE80211_AMPDU_RX_STOP:
printk("%s openwifi_ampdu_action: stop RX aggregation. tid %d\n", sdr_compatible_str, params->tid);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static const struct ieee80211_ops openwifi_ops = {
.tx = openwifi_tx,
.start = openwifi_start,
.stop = openwifi_stop,
.add_interface = openwifi_add_interface,
.remove_interface = openwifi_remove_interface,
.config = openwifi_config,
.set_antenna = openwifi_set_antenna,
.get_antenna = openwifi_get_antenna,
.bss_info_changed = openwifi_bss_info_changed,
.conf_tx = openwifi_conf_tx,
.prepare_multicast = openwifi_prepare_multicast,
.configure_filter = openwifi_configure_filter,
.rfkill_poll = openwifi_rfkill_poll,
.get_tsf = openwifi_get_tsf,
.set_tsf = openwifi_set_tsf,
.reset_tsf = openwifi_reset_tsf,
.set_rts_threshold = openwifi_set_rts_threshold,
.ampdu_action = openwifi_ampdu_action,
.testmode_cmd = openwifi_testmode_cmd,
};
static const struct of_device_id openwifi_dev_of_ids[] = {
{ .compatible = "sdr,sdr", },
{}
};
MODULE_DEVICE_TABLE(of, openwifi_dev_of_ids);
static int custom_match_spi_dev(struct device *dev, const void *data)
{
const char *name = data;
bool ret = sysfs_streq(name, dev->of_node->name);
printk("%s custom_match_spi_dev %s %s %d\n", sdr_compatible_str,name, dev->of_node->name, ret);
return ret;
}
static int custom_match_platform_dev(struct device *dev, const void *data)
{
struct platform_device *plat_dev = to_platform_device(dev);
const char *name = data;
char *name_in_sys_bus_platform_devices = strstr(plat_dev->name, name);
bool match_flag = (name_in_sys_bus_platform_devices != NULL);
if (match_flag) {
printk("%s custom_match_platform_dev %s\n", sdr_compatible_str,plat_dev->name);
}
return(match_flag);
}
static int openwifi_dev_probe(struct platform_device *pdev)
{
struct ieee80211_hw *dev;
struct openwifi_priv *priv;
struct device_node *dt_node;
int err=1, rand_val;
const char *fpga_model;
u32 reg, i;//, reg1;
struct device_node *np = pdev->dev.of_node;
struct device *tmp_dev;
struct platform_device *tmp_pdev;
struct iio_dev *tmp_indio_dev;
// struct gpio_leds_priv *tmp_led_priv;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(openwifi_dev_of_ids, np);
if (match) {
printk("%s openwifi_dev_probe: match!\n", sdr_compatible_str);
err = 0;
}
}
if (err)
return err;
dev = ieee80211_alloc_hw(sizeof(*priv), &openwifi_ops);
if (!dev) {
printk(KERN_ERR "%s openwifi_dev_probe: ieee80211 alloc failed\n",sdr_compatible_str);
err = -ENOMEM;
goto err_free_dev;
}
priv = dev->priv;
priv->pdev = pdev;
err = of_property_read_string(of_find_node_by_path("/"), "model", &fpga_model);
if(err < 0) {
priv->hardware_type = UNKNOWN_HARDWARE;
priv->fpga_type = SMALL_FPGA;
printk("%s openwifi_dev_probe: WARNING unknown openwifi FPGA model %d\n",sdr_compatible_str, err);
printk("%s openwifi_dev_probe: Try to detect TI lmk04828. If it exist, treate the board as RFSoC4x2\n",sdr_compatible_str);
dt_node = of_find_node_by_name(NULL, "lmk");
if (dt_node != NULL) {
printk("%s openwifi_dev_probe: found device tree node name %s\n",sdr_compatible_str, dt_node->name);
priv->hardware_type = RFSOC4X2;
priv->fpga_type = LARGE_FPGA;
} else {
printk("%s openwifi_dev_probe: WARNING device tree lmk node is not detected! %d\n",sdr_compatible_str, err);
}
} else {
if(strstr(fpga_model, "ZCU102") != NULL) {
priv->hardware_type = ZYNQMP_AD9361;
} else {
priv->hardware_type = ZYNQ_AD9361;
}
// LARGE FPGAs (i.e. ZCU102, Z7035, ZC706)
if(strstr(fpga_model, "ZCU102") != NULL || strstr(fpga_model, "Z7035") != NULL || strstr(fpga_model, "ZC706") != NULL) {
priv->fpga_type = LARGE_FPGA;
// SMALL FPGA: (i.e. ZED, ZC702, Z7020)
}// else if(strstr(fpga_model, "ZED") != NULL || strstr(fpga_model, "ZC702") != NULL || strstr(fpga_model, "Z7020") != NULL) {
else { // ALL others are SAMLL_FPGA
priv->fpga_type = SMALL_FPGA;
}
}
priv->actual_rx_lo = 1000; //Some value aligned with rf_init/rf_init_11n.sh that is not WiFi channel to force ad9361_rf_set_channel execution triggered by Linux
priv->actual_tx_lo = 1000; //Some value aligned with rf_init/rf_init_11n.sh that is not WiFi channel to force ad9361_rf_set_channel execution triggered by Linux
priv->band = freq_MHz_to_band(priv->actual_rx_lo);
priv->use_short_slot = false; //this can be changed by openwifi_bss_info_changed: BSS_CHANGED_ERP_SLOT
priv->ampdu_reference = 0;
priv->last_tx_quad_cal_lo = 1000;
if (priv->hardware_type != RFSOC4X2) {
// //-------------find ad9361-phy driver for lo/channel control---------------
tmp_dev = bus_find_device( &spi_bus_type, NULL, "ad9361-phy", custom_match_spi_dev );
if (tmp_dev == NULL) {
printk(KERN_ERR "%s find_dev ad9361-phy failed\n",sdr_compatible_str);
err = -ENODEV;
goto err_free_dev;
}
printk("%s bus_find_device ad9361-phy: %s. driver_data pointer %p\n", sdr_compatible_str, ((struct spi_device*)tmp_dev)->modalias, (void*)(((struct spi_device*)tmp_dev)->dev.driver_data));
if (((struct spi_device*)tmp_dev)->dev.driver_data == NULL) {
printk(KERN_ERR "%s find_dev ad9361-phy failed. dev.driver_data == NULL\n",sdr_compatible_str);
err = -ENODEV;
goto err_free_dev;
}
priv->ad9361_phy = ad9361_spi_to_phy((struct spi_device*)tmp_dev);
if (!(priv->ad9361_phy)) {
printk(KERN_ERR "%s ad9361_spi_to_phy failed\n",sdr_compatible_str);
err = -ENODEV;
goto err_free_dev;
}
printk("%s ad9361_spi_to_phy ad9361-phy: %s\n", sdr_compatible_str, priv->ad9361_phy->spi->modalias);
// //-------------find driver: axi_ad9361 hdl ref design module, dac channel---------------
tmp_dev = bus_find_device( &platform_bus_type, NULL, "cf-ad9361-dds-core-lpc", custom_match_platform_dev );
if (!tmp_dev) {
printk(KERN_ERR "%s bus_find_device platform_bus_type cf-ad9361-dds-core-lpc failed\n",sdr_compatible_str);
err = -ENODEV;
goto err_free_dev;
}
tmp_pdev = to_platform_device(tmp_dev);
if (!tmp_pdev) {
printk(KERN_ERR "%s to_platform_device failed\n",sdr_compatible_str);
err = -ENODEV;
goto err_free_dev;
}
tmp_indio_dev = platform_get_drvdata(tmp_pdev);
if (!tmp_indio_dev) {
printk(KERN_ERR "%s platform_get_drvdata failed\n",sdr_compatible_str);
err = -ENODEV;
goto err_free_dev;
}
priv->dds_st = iio_priv(tmp_indio_dev);
if (!(priv->dds_st)) {
printk(KERN_ERR "%s iio_priv failed\n",sdr_compatible_str);
err = -ENODEV;
goto err_free_dev;
}
printk("%s openwifi_dev_probe: cf-ad9361-dds-core-lpc dds_st->version %08x chip_info->name %s\n",sdr_compatible_str,priv->dds_st->version,priv->dds_st->chip_info->name);
cf_axi_dds_datasel(priv->dds_st, -1, DATA_SEL_DMA);
printk("%s openwifi_dev_probe: cf_axi_dds_datasel DATA_SEL_DMA\n",sdr_compatible_str);
// //-------------find driver: axi_ad9361 hdl ref design module, adc channel---------------
// turn off radio by muting tx
// ad9361_tx_mute(priv->ad9361_phy, 1);
// reg = ad9361_get_tx_atten(priv->ad9361_phy, 2);
// reg1 = ad9361_get_tx_atten(priv->ad9361_phy, 1);
// if (reg == AD9361_RADIO_OFF_TX_ATT && reg1 == AD9361_RADIO_OFF_TX_ATT ) {
// priv->rfkill_off = 0;// 0 off, 1 on
// printk("%s openwifi_dev_probe: rfkill radio off\n",sdr_compatible_str);
// }
// else
// printk("%s openwifi_dev_probe: WARNING rfkill radio off failed. tx att read %d %d require %d\n",sdr_compatible_str, reg, reg1, AD9361_RADIO_OFF_TX_ATT);
} else { //construct a fake ad9361_phy as a temporary solution
priv->ad9361_phy = &ad9361_phy_fake;
priv->ad9361_phy->state = &ad9361_phy_state_fake;
}
// //-----------------------------parse the test_mode input--------------------------------
if (test_mode&1)
AGGR_ENABLE = true;
// if (test_mode&2)
// TX_OFFSET_TUNING_ENABLE = false;
priv->rssi_correction = rssi_correction_lookup_table(5220);//5220MHz. this will be set in real-time by _rf_set_channel()
priv->last_auto_fpga_lbt_th = rssi_dbm_to_rssi_half_db(-78, priv->rssi_correction);//-78dBm. a magic value. just to avoid uninitialized
//priv->rf_bw = 20000000; // Signal quality issue! NOT use for now. 20MHz or 40MHz. 40MHz need ddc/duc. 20MHz works in bypass mode
priv->rf_bw = 40000000; // 20MHz or 40MHz. 40MHz need ddc/duc. 20MHz works in bypass mode
priv->xpu_cfg = XPU_NORMAL;
priv->openofdm_tx_cfg = OPENOFDM_TX_NORMAL;
priv->openofdm_rx_cfg = OPENOFDM_RX_NORMAL;
printk("%s openwifi_dev_probe: priv->rf_bw == %dHz. bool for 20000000 %d, 40000000 %d\n",sdr_compatible_str, priv->rf_bw, (priv->rf_bw==20000000) , (priv->rf_bw==40000000) );
if (priv->rf_bw == 20000000) { //DO NOT USE. Not used for long time.
priv->rx_intf_cfg = RX_INTF_BYPASS;
priv->tx_intf_cfg = TX_INTF_BYPASS;
//priv->rx_freq_offset_to_lo_MHz = 0;
//priv->tx_freq_offset_to_lo_MHz = 0;
} else if (priv->rf_bw == 40000000) {
//priv->rx_intf_cfg = RX_INTF_BW_20MHZ_AT_P_10MHZ; //work
//priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1; //work
// // test ddc at central, duc at central+10M. It works. And also change rx BW from 40MHz to 20MHz in rf_init.sh. Rx sampling rate is still 40Msps
priv->rx_intf_cfg = RX_INTF_BW_20MHZ_AT_0MHZ_ANT0;
if (TX_OFFSET_TUNING_ENABLE)
priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0; // Let's use rx0 tx0 as default mode, because it works for both 9361 and 9364
else
priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_0MHZ_ANT0;
// // try another antenna option
//priv->rx_intf_cfg = RX_INTF_BW_20MHZ_AT_0MHZ_ANT1;
//priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0;
#if 0
if (priv->rx_intf_cfg == DDC_BW_20MHZ_AT_N_10MHZ) {
priv->rx_freq_offset_to_lo_MHz = -10;
} else if (priv->rx_intf_cfg == DDC_BW_20MHZ_AT_P_10MHZ) {
priv->rx_freq_offset_to_lo_MHz = 10;
} else if (priv->rx_intf_cfg == DDC_BW_20MHZ_AT_0MHZ) {
priv->rx_freq_offset_to_lo_MHz = 0;
} else {
printk("%s openwifi_dev_probe: Warning! priv->rx_intf_cfg == %d\n",sdr_compatible_str,priv->rx_intf_cfg);
}
#endif
} else {
printk("%s openwifi_dev_probe: Warning! priv->rf_bw == %dHz (should be 20000000 or 40000000)\n",sdr_compatible_str, priv->rf_bw);
err = -EBADRQC;
goto err_free_dev;
}
printk("%s openwifi_dev_probe: test_mode %x AGGR_ENABLE %d TX_OFFSET_TUNING_ENABLE %d init_tx_att %d\n", sdr_compatible_str, test_mode, AGGR_ENABLE, TX_OFFSET_TUNING_ENABLE, init_tx_att);
priv->runtime_tx_ant_cfg = ((priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_0MHZ_ANT0 || priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0)?1:(priv->tx_intf_cfg==TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH?3:2));
priv->runtime_rx_ant_cfg = (priv->rx_intf_cfg==RX_INTF_BW_20MHZ_AT_0MHZ_ANT0?1:2);
priv->ctrl_out.en_mask=AD9361_CTRL_OUT_EN_MASK;
priv->ctrl_out.index =(priv->rx_intf_cfg==RX_INTF_BW_20MHZ_AT_0MHZ_ANT0?AD9361_CTRL_OUT_INDEX_ANT0:AD9361_CTRL_OUT_INDEX_ANT1);
memset(priv->drv_rx_reg_val,0,sizeof(priv->drv_rx_reg_val));
memset(priv->drv_tx_reg_val,0,sizeof(priv->drv_tx_reg_val));
memset(priv->drv_xpu_reg_val,0,sizeof(priv->drv_xpu_reg_val));
memset(priv->rf_reg_val,0,sizeof(priv->rf_reg_val));
priv->rf_reg_val[RF_TX_REG_IDX_ATT] = init_tx_att;
//let's by default turn radio on when probing
err = openwifi_set_antenna(dev, priv->runtime_tx_ant_cfg, priv->runtime_rx_ant_cfg);
if (err) {
printk("%s openwifi_dev_probe: WARNING openwifi_set_antenna FAIL %d\n",sdr_compatible_str, err);
err = -EIO;
goto err_free_dev;
}
reg = ad9361_spi_read(priv->ad9361_phy->spi, REG_CTRL_OUTPUT_POINTER);
printk("%s openwifi_dev_probe: ad9361_spi_read REG_CTRL_OUTPUT_POINTER 0x%02x\n",sdr_compatible_str, reg);
reg = ad9361_spi_read(priv->ad9361_phy->spi, REG_CTRL_OUTPUT_ENABLE);
printk("%s openwifi_dev_probe: ad9361_spi_read REG_CTRL_OUTPUT_ENABLE 0x%02x\n",sdr_compatible_str, reg);
reg = ad9361_get_tx_atten(priv->ad9361_phy, ((priv->runtime_tx_ant_cfg==1 || priv->runtime_tx_ant_cfg==3)?1:2));
if (reg == (AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT])) {
priv->rfkill_off = 1;// 0 off, 1 on
printk("%s openwifi_dev_probe: rfkill radio on\n",sdr_compatible_str);
} else
printk("%s openwifi_dev_probe: WARNING rfkill radio on failed. tx att read %d require %d\n",sdr_compatible_str, reg, AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]);
priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_GIT_REV] = GIT_REV;
// //set ad9361 in certain mode
#if 0
err = ad9361_set_trx_clock_chain_freq(priv->ad9361_phy,priv->rf_bw);
printk("%s openwifi_dev_probe: ad9361_set_trx_clock_chain_freq %dHz err %d\n",sdr_compatible_str, priv->rf_bw,err);
err = ad9361_update_rf_bandwidth(priv->ad9361_phy,priv->rf_bw,priv->rf_bw);
printk("%s openwifi_dev_probe: ad9361_update_rf_bandwidth %dHz err %d\n",sdr_compatible_str, priv->rf_bw,err);
rx_intf_api->hw_init(priv->rx_intf_cfg,8,8);
tx_intf_api->hw_init(priv->tx_intf_cfg,8,8,priv->fpga_type);
openofdm_tx_api->hw_init(priv->openofdm_tx_cfg);
openofdm_rx_api->hw_init(priv->openofdm_rx_cfg);
printk("%s openwifi_dev_probe: rx_intf_cfg %d openofdm_rx_cfg %d tx_intf_cfg %d openofdm_tx_cfg %d\n",sdr_compatible_str, priv->rx_intf_cfg, priv->openofdm_rx_cfg, priv->tx_intf_cfg, priv->openofdm_tx_cfg);
printk("%s openwifi_dev_probe: rx_freq_offset_to_lo_MHz %d tx_freq_offset_to_lo_MHz %d\n",sdr_compatible_str, priv->rx_freq_offset_to_lo_MHz, priv->tx_freq_offset_to_lo_MHz);
#endif
dev->max_rates = 1; //maximum number of alternate rate retry stages the hw can handle.
SET_IEEE80211_DEV(dev, &pdev->dev);
platform_set_drvdata(pdev, dev);
BUILD_BUG_ON(sizeof(priv->rates_2GHz) != sizeof(openwifi_2GHz_rates));
BUILD_BUG_ON(sizeof(priv->rates_5GHz) != sizeof(openwifi_5GHz_rates));
BUILD_BUG_ON(sizeof(priv->channels_2GHz) != sizeof(openwifi_2GHz_channels));
BUILD_BUG_ON(sizeof(priv->channels_5GHz) != sizeof(openwifi_5GHz_channels));
memcpy(priv->rates_2GHz, openwifi_2GHz_rates, sizeof(openwifi_2GHz_rates));
memcpy(priv->rates_5GHz, openwifi_5GHz_rates, sizeof(openwifi_5GHz_rates));
memcpy(priv->channels_2GHz, openwifi_2GHz_channels, sizeof(openwifi_2GHz_channels));
memcpy(priv->channels_5GHz, openwifi_5GHz_channels, sizeof(openwifi_5GHz_channels));
priv->band_2GHz.band = NL80211_BAND_2GHZ;
priv->band_2GHz.channels = priv->channels_2GHz;
priv->band_2GHz.n_channels = ARRAY_SIZE(priv->channels_2GHz);
priv->band_2GHz.bitrates = priv->rates_2GHz;
priv->band_2GHz.n_bitrates = ARRAY_SIZE(priv->rates_2GHz);
priv->band_2GHz.ht_cap.ht_supported = true;
if (test_mode&2)
priv->band_2GHz.ht_cap.cap = IEEE80211_HT_CAP_SGI_20; //SGI -- short GI seems bring unnecessary stability issue
if (AGGR_ENABLE) {
priv->band_2GHz.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K;
priv->band_2GHz.ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_2;
}
memset(&priv->band_2GHz.ht_cap.mcs, 0, sizeof(priv->band_2GHz.ht_cap.mcs));
priv->band_2GHz.ht_cap.mcs.rx_mask[0] = 0xff;
priv->band_2GHz.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
dev->wiphy->bands[NL80211_BAND_2GHZ] = &(priv->band_2GHz);
priv->band_5GHz.band = NL80211_BAND_5GHZ;
priv->band_5GHz.channels = priv->channels_5GHz;
priv->band_5GHz.n_channels = ARRAY_SIZE(priv->channels_5GHz);
priv->band_5GHz.bitrates = priv->rates_5GHz;
priv->band_5GHz.n_bitrates = ARRAY_SIZE(priv->rates_5GHz);
priv->band_5GHz.ht_cap.ht_supported = true;
if (test_mode&2)
priv->band_5GHz.ht_cap.cap = IEEE80211_HT_CAP_SGI_20; //SGI -- short GI seems bring unnecessary stability issue
if (AGGR_ENABLE) {
priv->band_5GHz.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K;
priv->band_5GHz.ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_2;
}
memset(&priv->band_5GHz.ht_cap.mcs, 0, sizeof(priv->band_5GHz.ht_cap.mcs));
priv->band_5GHz.ht_cap.mcs.rx_mask[0] = 0xff;
priv->band_5GHz.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
dev->wiphy->bands[NL80211_BAND_5GHZ] = &(priv->band_5GHz);
printk("%s openwifi_dev_probe: band_2GHz.n_channels %d n_bitrates %d band_5GHz.n_channels %d n_bitrates %d\n",sdr_compatible_str,
priv->band_2GHz.n_channels,priv->band_2GHz.n_bitrates,priv->band_5GHz.n_channels,priv->band_5GHz.n_bitrates);
// ieee80211_hw_set(dev, HOST_BROADCAST_PS_BUFFERING); // remove this because we don't want: mac80211.h: host buffers frame for PS and we fetch them via ieee80211_get_buffered_bc()
ieee80211_hw_set(dev, RX_INCLUDES_FCS);
ieee80211_hw_set(dev, BEACON_TX_STATUS);//mac80211.h: The device/driver provides TX status for sent beacons.
ieee80211_hw_set(dev, REPORTS_TX_ACK_STATUS);//mac80211.h: Hardware can provide ack status reports of Tx frames to the stack
// * @IEEE80211_HW_AP_LINK_PS: When operating in AP mode the device
// * autonomously manages the PS status of connected stations. When
// * this flag is set mac80211 will not trigger PS mode for connected
// * stations based on the PM bit of incoming frames.
// * Use ieee80211_start_ps()/ieee8021_end_ps() to manually configure
// * the PS mode of connected stations.
ieee80211_hw_set(dev, AP_LINK_PS);
if (AGGR_ENABLE) {
ieee80211_hw_set(dev, AMPDU_AGGREGATION);
}
dev->extra_tx_headroom = LEN_MPDU_DELIM;
dev->vif_data_size = sizeof(struct openwifi_vif);
dev->wiphy->interface_modes =
BIT(NL80211_IFTYPE_MONITOR)|
BIT(NL80211_IFTYPE_P2P_GO) |
BIT(NL80211_IFTYPE_P2P_CLIENT) |
BIT(NL80211_IFTYPE_AP) |
BIT(NL80211_IFTYPE_STATION) |
BIT(NL80211_IFTYPE_ADHOC) |
BIT(NL80211_IFTYPE_MESH_POINT) |
BIT(NL80211_IFTYPE_OCB);
dev->wiphy->iface_combinations = &openwifi_if_comb;
dev->wiphy->n_iface_combinations = 1;
dev->wiphy->available_antennas_tx = NUM_TX_ANT_MASK;
dev->wiphy->available_antennas_rx = NUM_RX_ANT_MASK;
dev->wiphy->regulatory_flags = (REGULATORY_STRICT_REG|REGULATORY_CUSTOM_REG); // use our own config within strict regulation
//dev->wiphy->regulatory_flags = REGULATORY_CUSTOM_REG; // use our own config
wiphy_apply_custom_regulatory(dev->wiphy, &sdr_regd);
/* we declare to MAC80211 all the queues except for beacon queue
* that will be eventually handled by DRV.
* TX rings are arranged in such a way that lower is the IDX,
* higher is the priority, in order to achieve direct mapping
* with mac80211, however the beacon queue is an exception and it
* is mapped on the highst tx ring IDX.
*/
dev->queues = MAX_NUM_HW_QUEUE;
ieee80211_hw_set(dev, SIGNAL_DBM);
wiphy_ext_feature_set(dev->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
if (priv->hardware_type == RFSOC4X2) {
priv->rf = &rfsoc4x2_rf_ops;
} else {
priv->rf = &ad9361_rf_ops;
}
memset(priv->dest_mac_addr_queue_map,0,sizeof(priv->dest_mac_addr_queue_map));
priv->slice_idx = 0xFFFFFFFF;
sg_init_table(&(priv->tx_sg), 1);
get_random_bytes(&rand_val, sizeof(rand_val));
rand_val%=250;
priv->mac_addr[0]=0x66; priv->mac_addr[1]=0x55; priv->mac_addr[2]=0x44; priv->mac_addr[3]=0x33; priv->mac_addr[4]=0x22;
priv->mac_addr[5]=rand_val+1;
//priv->mac_addr[5]=0x11;
if (!is_valid_ether_addr(priv->mac_addr)) {
printk(KERN_WARNING "%s openwifi_dev_probe: WARNING Invalid hwaddr! Using randomly generated MAC addr\n",sdr_compatible_str);
eth_random_addr(priv->mac_addr);
}
printk("%s openwifi_dev_probe: mac_addr %02x:%02x:%02x:%02x:%02x:%02x\n",sdr_compatible_str,priv->mac_addr[0],priv->mac_addr[1],priv->mac_addr[2],priv->mac_addr[3],priv->mac_addr[4],priv->mac_addr[5]);
SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
spin_lock_init(&priv->lock);
err = ieee80211_register_hw(dev);
if (err) {
pr_err(KERN_ERR "%s openwifi_dev_probe: WARNING Cannot register device\n",sdr_compatible_str);
err = -EIO;
goto err_free_dev;
} else {
printk("%s openwifi_dev_probe: ieee80211_register_hw %d\n",sdr_compatible_str, err);
}
// create sysfs for arbitrary iq setting
sysfs_bin_attr_init(&priv->bin_iq);
priv->bin_iq.attr.name = "tx_intf_iq_data";
priv->bin_iq.attr.mode = S_IWUSR | S_IRUGO;
priv->bin_iq.write = openwifi_tx_intf_bin_iq_write;
priv->bin_iq.read = openwifi_tx_intf_bin_iq_read;
priv->bin_iq.size = 4096;
err = sysfs_create_bin_file(&pdev->dev.kobj, &priv->bin_iq);
printk("%s openwifi_dev_probe: sysfs_create_bin_file %d\n",sdr_compatible_str, err);
if (err < 0)
goto err_free_dev;
priv->tx_intf_arbitrary_iq_num = 0;
// priv->tx_intf_arbitrary_iq[0] = 1;
// priv->tx_intf_arbitrary_iq[1] = 2;
err = sysfs_create_group(&pdev->dev.kobj, &tx_intf_attribute_group);
printk("%s openwifi_dev_probe: sysfs_create_group tx_intf_attribute_group %d\n",sdr_compatible_str, err);
if (err < 0)
goto err_free_dev;
priv->tx_intf_iq_ctl = 0;
// create sysfs for stat
err = sysfs_create_group(&pdev->dev.kobj, &stat_attribute_group);
printk("%s openwifi_dev_probe: sysfs_create_group stat_attribute_group %d\n",sdr_compatible_str, err);
if (err < 0)
goto err_free_dev;
priv->stat.stat_enable = 0; // by default disable
for (i=0; istat.tx_prio_num[i] = 0;
priv->stat.tx_prio_interrupt_num[i] = 0;
priv->stat.tx_prio_stop0_fake_num[i] = 0;
priv->stat.tx_prio_stop0_real_num[i] = 0;
priv->stat.tx_prio_stop1_num[i] = 0;
priv->stat.tx_prio_wakeup_num[i] = 0;
}
for (i=0; istat.tx_queue_num[i] = 0;
priv->stat.tx_queue_interrupt_num[i] = 0;
priv->stat.tx_queue_stop0_fake_num[i] = 0;
priv->stat.tx_queue_stop0_real_num[i] = 0;
priv->stat.tx_queue_stop1_num[i] = 0;
priv->stat.tx_queue_wakeup_num[i] = 0;
}
priv->stat.tx_data_pkt_need_ack_num_total = 0;
priv->stat.tx_data_pkt_need_ack_num_total_fail = 0;
for (i=0; i<6; i++) {
priv->stat.tx_data_pkt_need_ack_num_retx[i] = 0;
priv->stat.tx_data_pkt_need_ack_num_retx_fail[i] = 0;
}
priv->stat.tx_data_pkt_mcs_realtime = 0;
priv->stat.tx_data_pkt_fail_mcs_realtime = 0;
priv->stat.tx_mgmt_pkt_need_ack_num_total = 0;
priv->stat.tx_mgmt_pkt_need_ack_num_total_fail = 0;
for (i=0; i<3; i++) {
priv->stat.tx_mgmt_pkt_need_ack_num_retx[i] = 0;
priv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[i] = 0;
}
priv->stat.tx_mgmt_pkt_mcs_realtime = 0;
priv->stat.tx_mgmt_pkt_fail_mcs_realtime = 0;
priv->stat.rx_monitor_all = 0;
priv->stat.rx_target_sender_mac_addr = 0;
priv->stat.rx_data_ok_agc_gain_value_realtime = 0;
priv->stat.rx_data_fail_agc_gain_value_realtime = 0;
priv->stat.rx_mgmt_ok_agc_gain_value_realtime = 0;
priv->stat.rx_mgmt_fail_agc_gain_value_realtime = 0;
priv->stat.rx_ack_ok_agc_gain_value_realtime = 0;
priv->stat.rx_monitor_all = 0;
priv->stat.rx_data_pkt_num_total = 0;
priv->stat.rx_data_pkt_num_fail = 0;
priv->stat.rx_mgmt_pkt_num_total = 0;
priv->stat.rx_mgmt_pkt_num_fail = 0;
priv->stat.rx_ack_pkt_num_total = 0;
priv->stat.rx_ack_pkt_num_fail = 0;
priv->stat.rx_data_pkt_mcs_realtime = 0;
priv->stat.rx_data_pkt_fail_mcs_realtime = 0;
priv->stat.rx_mgmt_pkt_mcs_realtime = 0;
priv->stat.rx_mgmt_pkt_fail_mcs_realtime = 0;
priv->stat.rx_ack_pkt_mcs_realtime = 0;
priv->stat.restrict_freq_mhz = 0;
priv->stat.csma_cfg0 = 0;
priv->stat.cw_max_min_cfg = 0;
priv->stat.dbg_ch0 = 0;
priv->stat.dbg_ch1 = 0;
priv->stat.dbg_ch2 = 0;
// // //--------------------hook leds (not complete yet)--------------------------------
// tmp_dev = bus_find_device( &platform_bus_type, NULL, "leds", custom_match_platform_dev ); //leds is the name in devicetree, not "compatible" field
// if (!tmp_dev) {
// printk(KERN_ERR "%s bus_find_device platform_bus_type leds-gpio failed\n",sdr_compatible_str);
// err = -ENOMEM;
// goto err_free_dev;
// }
// tmp_pdev = to_platform_device(tmp_dev);
// if (!tmp_pdev) {
// printk(KERN_ERR "%s to_platform_device failed for leds-gpio\n",sdr_compatible_str);
// err = -ENOMEM;
// goto err_free_dev;
// }
// tmp_led_priv = platform_get_drvdata(tmp_pdev);
// if (!tmp_led_priv) {
// printk(KERN_ERR "%s platform_get_drvdata failed for leds-gpio\n",sdr_compatible_str);
// err = -ENOMEM;
// goto err_free_dev;
// }
// printk("%s openwifi_dev_probe: leds-gpio detect %d leds!\n",sdr_compatible_str, tmp_led_priv->num_leds);
// if (tmp_led_priv->num_leds!=4){
// printk(KERN_ERR "%s WARNING we expect 4 leds, but actual %d leds\n",sdr_compatible_str,tmp_led_priv->num_leds);
// err = -ENOMEM;
// goto err_free_dev;
// }
// gpiod_set_value(tmp_led_priv->leds[0].gpiod, 1);//light it
// gpiod_set_value(tmp_led_priv->leds[3].gpiod, 0);//black it
// priv->num_led = tmp_led_priv->num_leds;
// priv->led[0] = &(tmp_led_priv->leds[0].cdev);
// priv->led[1] = &(tmp_led_priv->leds[1].cdev);
// priv->led[2] = &(tmp_led_priv->leds[2].cdev);
// priv->led[3] = &(tmp_led_priv->leds[3].cdev);
// snprintf(priv->led_name[0], OPENWIFI_LED_MAX_NAME_LEN, "openwifi-%s::radio", wiphy_name(dev->wiphy));
// snprintf(priv->led_name[1], OPENWIFI_LED_MAX_NAME_LEN, "openwifi-%s::assoc", wiphy_name(dev->wiphy));
// snprintf(priv->led_name[2], OPENWIFI_LED_MAX_NAME_LEN, "openwifi-%s::tx", wiphy_name(dev->wiphy));
// snprintf(priv->led_name[3], OPENWIFI_LED_MAX_NAME_LEN, "openwifi-%s::rx", wiphy_name(dev->wiphy));
wiphy_info(dev->wiphy, "hwaddr %pm, FPGA %s\n",
priv->mac_addr, priv->rf->name);
openwifi_rfkill_init(dev);
return 0;
err_free_dev:
ieee80211_free_hw(dev);
return err;
}
static int openwifi_dev_remove(struct platform_device *pdev)
{
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
if (!dev) {
pr_info("%s openwifi_dev_remove: dev %p\n", sdr_compatible_str, (void*)dev);
return(-1);
}
sysfs_remove_bin_file(&pdev->dev.kobj, &priv->bin_iq);
sysfs_remove_group(&pdev->dev.kobj, &tx_intf_attribute_group);
sysfs_remove_group(&pdev->dev.kobj, &stat_attribute_group);
openwifi_rfkill_exit(dev);
ieee80211_unregister_hw(dev);
ieee80211_free_hw(dev);
return(0);
}
static struct platform_driver openwifi_dev_driver = {
.driver = {
.name = "sdr,sdr",
.owner = THIS_MODULE,
.of_match_table = openwifi_dev_of_ids,
},
.probe = openwifi_dev_probe,
.remove = openwifi_dev_remove,
};
module_platform_driver(openwifi_dev_driver);
================================================
FILE: driver/sdr.h
================================================
// Author: Xianjun Jiao, Michael Mehari, Wei Liu
// SPDX-FileCopyrightText: 2019 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
#ifndef OPENWIFI_SDR
#define OPENWIFI_SDR
#include "pre_def.h"
// -------------------for leds--------------------------------
struct gpio_led_data { //please always align with the leds-gpio.c in linux kernel
struct led_classdev cdev;
struct gpio_desc *gpiod;
u8 can_sleep;
u8 blinking;
gpio_blink_set_t platform_gpio_blink_set;
};
struct gpio_leds_priv { //please always align with the leds-gpio.c in linux kernel
int num_leds;
struct gpio_led_data leds[];
};
struct openwifi_rf_ops {
char *name;
// void (*init)(struct ieee80211_hw *);
// void (*stop)(struct ieee80211_hw *);
void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *);
// u8 (*calc_rssi)(u8 agc, u8 sq);
};
struct openwifi_buffer_descriptor {
// u32 num_dma_byte;
// u32 sn;
// u32 hw_queue_idx;
// u32 retry_limit;
// u32 need_ack;
u8 prio;
u16 len_mpdu;
u16 seq_no;
struct sk_buff *skb_linked;
dma_addr_t dma_mapping_addr;
// u32 reserved;
} __packed;
struct openwifi_ring {
struct openwifi_buffer_descriptor *bds;
u32 bd_wr_idx;
u32 bd_rd_idx;
int stop_flag; // -1: normal run; X>=0: stop due to queueX full
// u32 num_dma_symbol_request;
// u32 reserved;
} __packed;
struct openwifi_vif {
struct ieee80211_hw *dev;
int idx; // this vif's idx on the dev
/* beaconing */
struct delayed_work beacon_work;
bool enable_beacon;
};
union u32_byte4 {
u32 a;
u8 c[4];
};
union u16_byte2 {
u16 a;
u8 c[2];
};
#define MAX_NUM_LED 4
#define OPENWIFI_LED_MAX_NAME_LEN 32
#define NUM_TX_ANT_MASK 3
#define NUM_RX_ANT_MASK 3
// -------------sdrctl reg category-----------------
enum sdrctl_reg_cat {
SDRCTL_REG_CAT_NO_USE = 0,
SDRCTL_REG_CAT_RF,
SDRCTL_REG_CAT_RX_INTF,
SDRCTL_REG_CAT_TX_INTF,
SDRCTL_REG_CAT_RX,
SDRCTL_REG_CAT_TX,
SDRCTL_REG_CAT_XPU,
SDRCTL_REG_CAT_DRV_RX,
SDRCTL_REG_CAT_DRV_TX,
SDRCTL_REG_CAT_DRV_XPU,
};
// ------------ software and RF reg definition ------------
#define MAX_NUM_DRV_REG 8
#define DRV_TX_REG_IDX_RATE 0
#define DRV_TX_REG_IDX_RATE_HT 1
#define DRV_TX_REG_IDX_RATE_VHT 2
#define DRV_TX_REG_IDX_RATE_HE 3
#define DRV_TX_REG_IDX_ANT_CFG 4
#define DRV_TX_REG_IDX_PRINT_CFG (MAX_NUM_DRV_REG-1)
#define DRV_RX_REG_IDX_DEMOD_TH 0
#define DRV_RX_REG_IDX_ANT_CFG 4
#define DRV_RX_REG_IDX_PRINT_CFG (MAX_NUM_DRV_REG-1)
#define DRV_XPU_REG_IDX_LBT_TH 0
#define DRV_XPU_REG_IDX_GIT_REV (MAX_NUM_DRV_REG-1)
#define MAX_NUM_RF_REG 8
#define RF_TX_REG_IDX_ATT 0
#define RF_TX_REG_IDX_FREQ_MHZ 1
#define RF_RX_REG_IDX_GAIN 4
#define RF_RX_REG_IDX_FREQ_MHZ 5
// ------end of software and RF reg definition ------------
// -------------dmesg printk control flag------------------
#define DMESG_LOG_ERROR (1<<0)
#define DMESG_LOG_UNICAST (1<<1)
#define DMESG_LOG_BROADCAST (1<<2)
#define DMESG_LOG_NORMAL_QUEUE_STOP (1<<3)
#define DMESG_LOG_ANY (0xF)
// ------end of dmesg printk control flag------------------
#define MAX_NUM_VIF 4
#define LEN_PHY_CRC 4
#define LEN_MPDU_DELIM 4
#define MAX_NUM_HW_QUEUE 4 // number of queue in FPGA
#define MAX_NUM_SW_QUEUE 4 // number of queue in Linux, depends on the number we report by dev->queues in openwifi_dev_probe
#define RING_ROOM_THRESHOLD (2+MAX_NUM_SW_QUEUE) // MAX_NUM_SW_QUEUE is for the room of MAX_NUM_SW_QUEUE last packets from MAX_NUM_SW_QUEUE queue before stop
#define NUM_BIT_NUM_TX_BD 6
#define NUM_TX_BD (1<priv;
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct sk_buff *skb;
int err;
u32 tmp=-1, reg_cat, reg_addr, reg_val, reg_addr_idx, tsft_high, tsft_low;
int tmp_int;
err = nla_parse(tb, OPENWIFI_ATTR_MAX, data, len, openwifi_testmode_policy, NULL);
if (err)
return err;
if (!tb[OPENWIFI_ATTR_CMD])
return -EINVAL;
channel_conf_tmp.chandef.chan = (&channel_tmp);
switch (nla_get_u32(tb[OPENWIFI_ATTR_CMD])) {
case OPENWIFI_CMD_SET_GAP:
if (!tb[OPENWIFI_ATTR_GAP])
return -EINVAL;
tmp = nla_get_u32(tb[OPENWIFI_ATTR_GAP]);
printk("%s XPU_REG_CSMA_CFG_write %08x (Check openwifi_conf_tx() in sdr.c to understand)\n", sdr_compatible_str, tmp);
xpu_api->XPU_REG_CSMA_CFG_write(tmp); // unit us
return 0;
case OPENWIFI_CMD_GET_GAP:
skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
if (!skb)
return -ENOMEM;
tmp = xpu_api->XPU_REG_CSMA_CFG_read();
if (nla_put_u32(skb, OPENWIFI_ATTR_GAP, tmp))
goto nla_put_failure;
return cfg80211_testmode_reply(skb);
case OPENWIFI_CMD_SET_SLICE_IDX:
if (!tb[OPENWIFI_ATTR_SLICE_IDX])
return -EINVAL;
tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_IDX]);
printk("%s set openwifi slice_idx in hex: %08x\n", sdr_compatible_str, tmp);
if (tmp == MAX_NUM_HW_QUEUE) {
printk("%s set openwifi slice_idx reset all queue counter.\n", sdr_compatible_str);
xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time
xpu_api->XPU_REG_MULTI_RST_write(0<<7);
} else {
priv->slice_idx = tmp;
}
return 0;
case OPENWIFI_CMD_GET_SLICE_IDX:
skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
if (!skb)
return -ENOMEM;
tmp = priv->slice_idx;
if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_IDX, tmp))
goto nla_put_failure;
printk("%s get openwifi slice_idx in hex: %08x\n", sdr_compatible_str, tmp);
return cfg80211_testmode_reply(skb);
case OPENWIFI_CMD_SET_ADDR:
if (!tb[OPENWIFI_ATTR_ADDR])
return -EINVAL;
tmp = nla_get_u32(tb[OPENWIFI_ATTR_ADDR]);
if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {
printk("%s set openwifi slice_target_mac_addr(low32) WARNING: current slice idx %d is invalid!\n", sdr_compatible_str, priv->slice_idx);
return -EOPNOTSUPP;
} else {
printk("%s set openwifi slice_target_mac_addr(low32) in hex: %08x to slice %d\n", sdr_compatible_str, tmp, priv->slice_idx);
priv->dest_mac_addr_queue_map[priv->slice_idx] = reverse32(tmp);
}
return 0;
case OPENWIFI_CMD_GET_ADDR:
skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
if (!skb)
return -ENOMEM;
if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {
tmp = -1;
} else {
tmp = reverse32(priv->dest_mac_addr_queue_map[priv->slice_idx]);
}
if (nla_put_u32(skb, OPENWIFI_ATTR_ADDR, tmp))
goto nla_put_failure;
printk("%s get openwifi slice_target_mac_addr(low32) in hex: %08x of slice %d\n", sdr_compatible_str, tmp, priv->slice_idx);
return cfg80211_testmode_reply(skb);
case OPENWIFI_CMD_SET_SLICE_TOTAL:
if (!tb[OPENWIFI_ATTR_SLICE_TOTAL])
return -EINVAL;
tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL]);
if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {
printk("%s set SLICE_TOTAL(duration) WARNING: current slice idx %d is invalid!\n", sdr_compatible_str, priv->slice_idx);
return -EOPNOTSUPP;
} else {
printk("%s set SLICE_TOTAL(duration) %d usec to slice %d\n", sdr_compatible_str, tmp, priv->slice_idx);
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((priv->slice_idx<<20)|tmp);
}
return 0;
case OPENWIFI_CMD_GET_SLICE_TOTAL:
skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
if (!skb)
return -ENOMEM;
tmp = (xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read());
printk("%s get SLICE_TOTAL(duration) %d usec of slice %d\n", sdr_compatible_str, tmp&0xFFFFF, tmp>>20);
if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_TOTAL, tmp))
goto nla_put_failure;
return cfg80211_testmode_reply(skb);
case OPENWIFI_CMD_SET_SLICE_START:
if (!tb[OPENWIFI_ATTR_SLICE_START])
return -EINVAL;
tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START]);
if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {
printk("%s set SLICE_START(duration) WARNING: current slice idx %d is invalid!\n", sdr_compatible_str, priv->slice_idx);
return -EOPNOTSUPP;
} else {
printk("%s set SLICE_START(duration) %d usec to slice %d\n", sdr_compatible_str, tmp, priv->slice_idx);
xpu_api->XPU_REG_SLICE_COUNT_START_write((priv->slice_idx<<20)|tmp);
}
return 0;
case OPENWIFI_CMD_GET_SLICE_START:
skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
if (!skb)
return -ENOMEM;
tmp = (xpu_api->XPU_REG_SLICE_COUNT_START_read());
printk("%s get SLICE_START(duration) %d usec of slice %d\n", sdr_compatible_str, tmp&0xFFFFF, tmp>>20);
if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_START, tmp))
goto nla_put_failure;
return cfg80211_testmode_reply(skb);
case OPENWIFI_CMD_SET_SLICE_END:
if (!tb[OPENWIFI_ATTR_SLICE_END])
return -EINVAL;
tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END]);
if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {
printk("%s set SLICE_END(duration) WARNING: current slice idx %d is invalid!\n", sdr_compatible_str, priv->slice_idx);
return -EOPNOTSUPP;
} else {
printk("%s set SLICE_END(duration) %d usec to slice %d\n", sdr_compatible_str, tmp, priv->slice_idx);
xpu_api->XPU_REG_SLICE_COUNT_END_write((priv->slice_idx<<20)|tmp);
}
return 0;
case OPENWIFI_CMD_GET_SLICE_END:
skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
if (!skb)
return -ENOMEM;
tmp = (xpu_api->XPU_REG_SLICE_COUNT_END_read());
printk("%s get SLICE_END(duration) %d usec of slice %d\n", sdr_compatible_str, tmp&0xFFFFF, tmp>>20);
if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_END, tmp))
goto nla_put_failure;
return cfg80211_testmode_reply(skb);
// case OPENWIFI_CMD_SET_SLICE_TOTAL1:
// if (!tb[OPENWIFI_ATTR_SLICE_TOTAL1])
// return -EINVAL;
// tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL1]);
// printk("%s set SLICE_TOTAL1(duration) to %d usec\n", sdr_compatible_str, tmp);
// // xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_write(tmp);
// return 0;
// case OPENWIFI_CMD_GET_SLICE_TOTAL1:
// skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
// if (!skb)
// return -ENOMEM;
// // tmp = (xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_read());
// if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_TOTAL1, tmp))
// goto nla_put_failure;
// return cfg80211_testmode_reply(skb);
// case OPENWIFI_CMD_SET_SLICE_START1:
// if (!tb[OPENWIFI_ATTR_SLICE_START1])
// return -EINVAL;
// tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START1]);
// printk("%s set SLICE_START1(duration) to %d usec\n", sdr_compatible_str, tmp);
// // xpu_api->XPU_REG_SLICE_COUNT_START1_write(tmp);
// return 0;
// case OPENWIFI_CMD_GET_SLICE_START1:
// skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
// if (!skb)
// return -ENOMEM;
// // tmp = (xpu_api->XPU_REG_SLICE_COUNT_START1_read());
// if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_START1, tmp))
// goto nla_put_failure;
// return cfg80211_testmode_reply(skb);
// case OPENWIFI_CMD_SET_SLICE_END1:
// if (!tb[OPENWIFI_ATTR_SLICE_END1])
// return -EINVAL;
// tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END1]);
// printk("%s set SLICE_END1(duration) to %d usec\n", sdr_compatible_str, tmp);
// // xpu_api->XPU_REG_SLICE_COUNT_END1_write(tmp);
// return 0;
// case OPENWIFI_CMD_GET_SLICE_END1:
// skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
// if (!skb)
// return -ENOMEM;
// // tmp = (xpu_api->XPU_REG_SLICE_COUNT_END1_read());
// if (nla_put_u32(skb, OPENWIFI_ATTR_SLICE_END1, tmp))
// goto nla_put_failure;
// return cfg80211_testmode_reply(skb);
case OPENWIFI_CMD_SET_RSSI_TH:
if (!tb[OPENWIFI_ATTR_RSSI_TH])
return -EINVAL;
tmp = nla_get_u32(tb[OPENWIFI_ATTR_RSSI_TH]);
// printk("%s set RSSI_TH to %d\n", sdr_compatible_str, tmp);
// xpu_api->XPU_REG_LBT_TH_write(tmp);
// return 0;
printk("%s WARNING Please use command: sdrctl dev sdr0 set reg drv_xpu 0 reg_value! (1~2047, 0 means AUTO)!\n", sdr_compatible_str);
return -EOPNOTSUPP;
case OPENWIFI_CMD_GET_RSSI_TH:
skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
if (!skb)
return -ENOMEM;
tmp_int = rssi_half_db_to_rssi_dbm(xpu_api->XPU_REG_LBT_TH_read(), priv->rssi_correction); //rssi_dbm
tmp = (-tmp_int);
if (nla_put_u32(skb, OPENWIFI_ATTR_RSSI_TH, tmp))
goto nla_put_failure;
return cfg80211_testmode_reply(skb);
case OPENWIFI_CMD_SET_TSF:
printk("openwifi_set_tsf_1");
if ( (!tb[OPENWIFI_ATTR_HIGH_TSF]) || (!tb[OPENWIFI_ATTR_LOW_TSF]) )
return -EINVAL;
printk("openwifi_set_tsf_2");
tsft_high = nla_get_u32(tb[OPENWIFI_ATTR_HIGH_TSF]);
tsft_low = nla_get_u32(tb[OPENWIFI_ATTR_LOW_TSF]);
xpu_api->XPU_REG_TSF_LOAD_VAL_write(tsft_high,tsft_low);
printk("%s openwifi_set_tsf: %08x%08x\n", sdr_compatible_str,tsft_high,tsft_low);
return 0;
case REG_CMD_SET:
if ( (!tb[REG_ATTR_ADDR]) || (!tb[REG_ATTR_VAL]) )
return -EINVAL;
reg_addr = nla_get_u32(tb[REG_ATTR_ADDR]);
reg_val = nla_get_u32(tb[REG_ATTR_VAL]);
reg_cat = ((reg_addr>>16)&0xFFFF);
reg_addr = (reg_addr&0xFFFF);
reg_addr_idx = (reg_addr>>2);
printk("%s recv set cmd reg cat %d addr %08x val %08x idx %d\n", sdr_compatible_str, reg_cat, reg_addr, reg_val, reg_addr_idx);
if (reg_cat==SDRCTL_REG_CAT_RF) {
// printk("%s WARNING reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str);
// return -EOPNOTSUPP;
if (reg_addr_idx>=0 && reg_addr_idxrf_reg_val[reg_addr_idx]=reg_val;
if (reg_addr_idx==RF_TX_REG_IDX_ATT) {//change the tx ON att (if a RF chain is ON)
tmp = ad9361_get_tx_atten(priv->ad9361_phy, 1);
printk("%s ad9361_get_tx_atten ant0 %d\n",sdr_compatible_str, tmp);
if (tmpad9361_phy, AD9361_RADIO_ON_TX_ATT+reg_val, true, false, true);
if (err < 0) {
printk("%s WARNING ad9361_set_tx_atten ant0 %d FAIL!\n",sdr_compatible_str, AD9361_RADIO_ON_TX_ATT+reg_val);
return -EIO;
} else {
printk("%s ad9361_set_tx_atten ant0 %d OK\n",sdr_compatible_str, AD9361_RADIO_ON_TX_ATT+reg_val);
}
}
tmp = ad9361_get_tx_atten(priv->ad9361_phy, 2);
printk("%s ad9361_get_tx_atten ant1 %d\n",sdr_compatible_str, tmp);
if (tmpad9361_phy, AD9361_RADIO_ON_TX_ATT+reg_val, false, true, true);
if (err < 0) {
printk("%s WARNING ad9361_set_tx_atten ant1 %d FAIL!\n",sdr_compatible_str, AD9361_RADIO_ON_TX_ATT+reg_val);
return -EIO;
} else {
printk("%s ad9361_set_tx_atten ant1 %d OK\n",sdr_compatible_str, AD9361_RADIO_ON_TX_ATT+reg_val);
}
}
} else if (reg_addr_idx==RF_TX_REG_IDX_FREQ_MHZ || reg_addr_idx==RF_RX_REG_IDX_FREQ_MHZ) { // apply the tx and rx fo
channel_conf_tmp.chandef.chan->center_freq = reg_val;
ad9361_rf_set_channel(hw, &channel_conf_tmp);
priv->stat.restrict_freq_mhz = reg_val;
// clk_set_rate(priv->ad9361_phy->clks[TX_RFPLL], ( ((u64)1000000ull)*((u64)priv->rf_reg_val[RF_TX_REG_IDX_FREQ_MHZ]) )>>1 );
// ad9361_tx_calibration(priv, priv->rf_reg_val[RF_TX_REG_IDX_FREQ_MHZ]);
// printk("%s clk_set_rate TX_RFPLL %dMHz done\n",sdr_compatible_str, priv->rf_reg_val[RF_TX_REG_IDX_FREQ_MHZ]);
}
// else if (reg_addr_idx==RF_RX_REG_IDX_FREQ_MHZ) { // apply the rx fo
// channel_conf_tmp.chandef.chan->center_freq = reg_val;
// ad9361_rf_set_channel(hw, &channel_conf_tmp);
// // clk_set_rate(priv->ad9361_phy->clks[RX_RFPLL], ( ((u64)1000000ull)*((u64)priv->rf_reg_val[RF_RX_REG_IDX_FREQ_MHZ]) )>>1 );
// // openwifi_rf_rx_update_after_tuning(priv, priv->rf_reg_val[RF_RX_REG_IDX_FREQ_MHZ]);
// // printk("%s clk_set_rate RX_RFPLL %dMHz done\n",sdr_compatible_str, priv->rf_reg_val[RF_RX_REG_IDX_FREQ_MHZ]);
// }
} else {
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
return -EOPNOTSUPP;
}
}
else if (reg_cat==SDRCTL_REG_CAT_RX_INTF)
rx_intf_api->reg_write(reg_addr,reg_val);
else if (reg_cat==SDRCTL_REG_CAT_TX_INTF)
tx_intf_api->reg_write(reg_addr,reg_val);
else if (reg_cat==SDRCTL_REG_CAT_RX)
openofdm_rx_api->reg_write(reg_addr,reg_val);
else if (reg_cat==SDRCTL_REG_CAT_TX)
openofdm_tx_api->reg_write(reg_addr,reg_val);
else if (reg_cat==SDRCTL_REG_CAT_XPU)
xpu_api->reg_write(reg_addr,reg_val);
else if (reg_cat==SDRCTL_REG_CAT_DRV_RX) {
if (reg_addr_idx>=0 && reg_addr_idxdrv_tx_reg_val[reg_addr_idx]==0?1:2), (reg_val==0?1:2));
if (tmp) {
printk("%s WARNING openwifi_set_antenna return %d!\n", sdr_compatible_str, tmp);
return -EIO;
} else {
priv->drv_rx_reg_val[reg_addr_idx]=reg_val;
}
} else {
priv->drv_rx_reg_val[reg_addr_idx]=reg_val;
if (reg_addr_idx==DRV_RX_REG_IDX_DEMOD_TH) {
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|rssi_dbm_to_rssi_half_db((reg_val==0?OPENOFDM_RX_RSSI_DBM_TH_DEFAULT:(-reg_val)), priv->rssi_correction));
}
}
} else {
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
return -EOPNOTSUPP;
}
}
else if (reg_cat==SDRCTL_REG_CAT_DRV_TX) {
if (reg_addr_idx>=0 && reg_addr_idx=4 && (reg_val&0xF)<=11)) ) ) {
printk("%s WARNING rate override value should be 0 or 4~11!\n", sdr_compatible_str);
return -EOPNOTSUPP;
} else {
if (reg_addr_idx==DRV_TX_REG_IDX_ANT_CFG) {
tmp = openwifi_set_antenna(hw, reg_val+1, priv->drv_rx_reg_val[reg_addr_idx]+1);
if (tmp) {
printk("%s WARNING openwifi_set_antenna return %d!\n", sdr_compatible_str, tmp);
return -EIO;
} else {
priv->drv_tx_reg_val[reg_addr_idx]=reg_val;
}
} else {
priv->drv_tx_reg_val[reg_addr_idx]=reg_val;
}
}
} else {
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
return -EOPNOTSUPP;
}
}
else if (reg_cat==SDRCTL_REG_CAT_DRV_XPU) {
if (reg_addr_idx>=0 && reg_addr_idxdrv_xpu_reg_val[reg_addr_idx]=reg_val;
if (reg_addr_idx==DRV_XPU_REG_IDX_LBT_TH) {
if (reg_val) {
tmp_int = (-reg_val); // rssi_dbm
tmp = rssi_dbm_to_rssi_half_db(tmp_int, priv->rssi_correction);
xpu_api->XPU_REG_LBT_TH_write( tmp );
printk("%s override FPGA LBT threshold to %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm). rssi corr %d (%d/%dMHz)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo);
} else {
xpu_api->XPU_REG_LBT_TH_write(priv->last_auto_fpga_lbt_th);
printk("%s Restore last_auto_fpga_lbt_th %d(%ddBm) to FPGA. ad9361_rf_set_channel will take control. rssi corr %d (%d/%dMHz)\n", sdr_compatible_str, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo);
}
}
} else {
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
return -EOPNOTSUPP;
}
}
else {
printk("%s WARNING reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat);
return -EOPNOTSUPP;
}
return 0;
case REG_CMD_GET:
skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
if (!skb)
return -ENOMEM;
reg_addr = nla_get_u32(tb[REG_ATTR_ADDR]);
reg_cat = ((reg_addr>>16)&0xFFFF);
reg_addr = (reg_addr&0xFFFF);
reg_addr_idx = (reg_addr>>2);
printk("%s recv get cmd reg cat %d addr %08x idx %d\n", sdr_compatible_str, reg_cat, reg_addr, reg_addr_idx);
if (reg_cat==SDRCTL_REG_CAT_RF) {
// printk("%s WARNING reg cat 1 (rf) is not supported yet!\n", sdr_compatible_str);
// tmp = 0xFFFFFFFF;
// return -EOPNOTSUPP;
if (reg_addr_idx>=0 && reg_addr_idxrf_reg_val[reg_addr_idx];
} else {
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
return -EOPNOTSUPP;
}
}
else if (reg_cat==SDRCTL_REG_CAT_RX_INTF)
tmp = rx_intf_api->reg_read(reg_addr);
else if (reg_cat==SDRCTL_REG_CAT_TX_INTF)
tmp = tx_intf_api->reg_read(reg_addr);
else if (reg_cat==SDRCTL_REG_CAT_RX)
tmp = openofdm_rx_api->reg_read(reg_addr);
else if (reg_cat==SDRCTL_REG_CAT_TX)
tmp = openofdm_tx_api->reg_read(reg_addr);
else if (reg_cat==SDRCTL_REG_CAT_XPU)
tmp = xpu_api->reg_read(reg_addr);
else if (reg_cat==SDRCTL_REG_CAT_DRV_RX) {
if (reg_addr_idx>=0 && reg_addr_idxdrv_rx_reg_val[reg_addr_idx];
if (reg_addr_idx==DRV_RX_REG_IDX_ANT_CFG)
openwifi_get_antenna(hw, &tsft_high, &tsft_low);
} else {
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
return -EOPNOTSUPP;
}
}
else if (reg_cat==SDRCTL_REG_CAT_DRV_TX) {
if (reg_addr_idx>=0 && reg_addr_idxdrv_tx_reg_val[reg_addr_idx];
if (reg_addr_idx==DRV_TX_REG_IDX_ANT_CFG)
openwifi_get_antenna(hw, &tsft_high, &tsft_low);
} else {
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
return -EOPNOTSUPP;
}
}
else if (reg_cat==SDRCTL_REG_CAT_DRV_XPU) {
if (reg_addr_idx>=0 && reg_addr_idxXPU_REG_LBT_TH_read();//rssi_half_db
tmp_int = rssi_half_db_to_rssi_dbm(tmp, priv->rssi_correction); //rssi_dbm
printk("%s FPGA LBT threshold %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm). rssi corr %d (%d/%dMHz)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo);
}
tmp = priv->drv_xpu_reg_val[reg_addr_idx];
} else {
printk("%s WARNING reg_addr_idx %d is out of range!\n", sdr_compatible_str, reg_addr_idx);
return -EOPNOTSUPP;
}
}
else {
printk("%s WARNING reg cat %d is not supported yet!\n", sdr_compatible_str, reg_cat);
return -EOPNOTSUPP;
}
if (nla_put_u32(skb, REG_ATTR_VAL, tmp))
goto nla_put_failure;
return cfg80211_testmode_reply(skb);
default:
return -EOPNOTSUPP;
}
nla_put_failure:
dev_kfree_skb(skb);
return -ENOBUFS;
}
================================================
FILE: driver/side_ch/Makefile
================================================
# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += side_ch.o
# obj-m += axidmatest.o
all:
make -C $(KDIR) M=$(PWD) modules
# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
================================================
FILE: driver/side_ch/make_driver.sh
================================================
#!/bin/bash
# Author: Xianjun Jiao, Wei Liu
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -ne 2 ]; then
echo "You must enter exactly 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)"
exit 1
fi
OPENWIFI_DIR=$(pwd)/../../
XILINX_DIR=$1
ARCH_OPTION=$2
if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
echo "\$OPENWIFI_DIR is found!"
else
echo "\$OPENWIFI_DIR is not correct. Please check!"
exit 1
fi
if [ -d "$XILINX_DIR/Vitis" ]; then
echo "\$XILINX_DIR is found!"
else
echo "\$XILINX_DIR is not correct. Please check!"
exit 1
fi
if [ "$ARCH_OPTION" != "32" ] && [ "$ARCH_OPTION" != "64" ]; then
echo "\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!"
exit 1
else
echo "\$ARCH_OPTION is valid!"
fi
XILINX_ENV_FILE=$XILINX_DIR/Vitis/2022.2/settings64.sh
echo "Expect env file $XILINX_ENV_FILE"
source $XILINX_ENV_FILE
if [ "$ARCH_OPTION" == "64" ]; then
LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/
ARCH="arm64"
CROSS_COMPILE="aarch64-linux-gnu-"
else
LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux/
ARCH="arm"
CROSS_COMPILE="arm-linux-gnueabihf-"
fi
# check if user entered the right path to analog device linux
if [ -d "$LINUX_KERNEL_SRC_DIR" ]; then
echo " setup linux kernel path ${LINUX_KERNEL_SRC_DIR}"
else
echo "Error: path to adi linux: ${LINUX_KERNEL_SRC_DIR} not found. Can not continue."
exit 1
fi
set -x
home_dir=$(pwd)
cd $OPENWIFI_DIR/driver/side_ch
make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
cd $home_dir
================================================
FILE: driver/side_ch/side_ch.c
================================================
/*
* openwifi side channel driver
* Author: Xianjun Jiao
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "side_ch.h"
static int num_eq_init = 8; // should be 0~8
static int iq_len_init = 0; //if iq_len>0, iq capture enabled, csi disabled
module_param(num_eq_init, int, 0);
MODULE_PARM_DESC(num_eq_init, "num_eq_init. 0~8. number of equalizer output (52 each) appended to CSI");
module_param(iq_len_init, int, 0);
MODULE_PARM_DESC(iq_len_init, "iq_len_init. if iq_len_init>0, iq capture enabled, csi disabled");
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
struct dma_chan *chan_to_pl = NULL;
struct dma_chan *chan_to_ps = NULL;
u8 *side_info_buf = NULL;
dma_cookie_t chan_to_ps_cookie;
const int max_side_info_buf_size = MAX_NUM_DMA_SYMBOL*8;
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline void SIDE_CH_REG_MULTI_RST_write(u32 Data) {
reg_write(SIDE_CH_REG_MULTI_RST_ADDR, Data);
}
static inline u32 SIDE_CH_REG_CONFIG_read(void){
return reg_read(SIDE_CH_REG_CONFIG_ADDR);
}
static inline void SIDE_CH_REG_CONFIG_write(u32 value){
reg_write(SIDE_CH_REG_CONFIG_ADDR, value);
}
static inline u32 SIDE_CH_REG_NUM_DMA_SYMBOL_read(void){
return reg_read(SIDE_CH_REG_NUM_DMA_SYMBOL_ADDR);
}
static inline void SIDE_CH_REG_NUM_DMA_SYMBOL_write(u32 value){
reg_write(SIDE_CH_REG_NUM_DMA_SYMBOL_ADDR, value);
}
static inline u32 SIDE_CH_REG_IQ_CAPTURE_read(void){
return reg_read(SIDE_CH_REG_IQ_CAPTURE_ADDR);
}
static inline void SIDE_CH_REG_IQ_CAPTURE_write(u32 value){
reg_write(SIDE_CH_REG_IQ_CAPTURE_ADDR, value);
}
static inline u32 SIDE_CH_REG_NUM_EQ_read(void){
return reg_read(SIDE_CH_REG_NUM_EQ_ADDR);
}
static inline void SIDE_CH_REG_NUM_EQ_write(u32 value){
reg_write(SIDE_CH_REG_NUM_EQ_ADDR, value);
}
static inline u32 SIDE_CH_REG_FC_TARGET_read(void){
return reg_read(SIDE_CH_REG_FC_TARGET_ADDR);
}
static inline void SIDE_CH_REG_FC_TARGET_write(u32 value){
reg_write(SIDE_CH_REG_FC_TARGET_ADDR, value);
}
static inline u32 SIDE_CH_REG_ADDR1_TARGET_read(void){
return reg_read(SIDE_CH_REG_ADDR1_TARGET_ADDR);
}
static inline void SIDE_CH_REG_ADDR1_TARGET_write(u32 value){
reg_write(SIDE_CH_REG_ADDR1_TARGET_ADDR, value);
}
static inline u32 SIDE_CH_REG_ADDR2_TARGET_read(void){
return reg_read(SIDE_CH_REG_ADDR2_TARGET_ADDR);
}
static inline void SIDE_CH_REG_ADDR2_TARGET_write(u32 value){
reg_write(SIDE_CH_REG_ADDR2_TARGET_ADDR, value);
}
static inline u32 SIDE_CH_REG_IQ_TRIGGER_read(void){
return reg_read(SIDE_CH_REG_IQ_TRIGGER_ADDR);
}
static inline void SIDE_CH_REG_IQ_TRIGGER_write(u32 value){
reg_write(SIDE_CH_REG_IQ_TRIGGER_ADDR, value);
}
static inline u32 SIDE_CH_REG_RSSI_TH_read(void){
return reg_read(SIDE_CH_REG_RSSI_TH_ADDR);
}
static inline void SIDE_CH_REG_RSSI_TH_write(u32 value){
reg_write(SIDE_CH_REG_RSSI_TH_ADDR, value);
}
static inline u32 SIDE_CH_REG_GAIN_TH_read(void){
return reg_read(SIDE_CH_REG_GAIN_TH_ADDR);
}
static inline void SIDE_CH_REG_GAIN_TH_write(u32 value){
reg_write(SIDE_CH_REG_GAIN_TH_ADDR, value);
}
static inline u32 SIDE_CH_REG_PRE_TRIGGER_LEN_read(void){
return reg_read(SIDE_CH_REG_PRE_TRIGGER_LEN_ADDR);
}
static inline void SIDE_CH_REG_PRE_TRIGGER_LEN_write(u32 value){
reg_write(SIDE_CH_REG_PRE_TRIGGER_LEN_ADDR, value);
}
static inline u32 SIDE_CH_REG_IQ_LEN_read(void){
return reg_read(SIDE_CH_REG_IQ_LEN_ADDR);
}
static inline void SIDE_CH_REG_IQ_LEN_write(u32 value){
reg_write(SIDE_CH_REG_IQ_LEN_ADDR, value);
}
static inline u32 SIDE_CH_REG_M_AXIS_DATA_COUNT_read(void){
return reg_read(SIDE_CH_REG_M_AXIS_DATA_COUNT_ADDR);
}
static inline void SIDE_CH_REG_M_AXIS_DATA_COUNT_write(u32 value){
reg_write(SIDE_CH_REG_M_AXIS_DATA_COUNT_ADDR, value);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,side_ch", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static void chan_to_ps_callback(void *completion)
{
complete(completion);
}
#if 0
static void chan_to_pl_callback(void *completion)
{
complete(completion);
}
static int dma_loopback_test(int num_test, int num_dma_symbol) {
int i, err = 0;
// -----------dma loop back test-------------------------
enum dma_status status;
enum dma_ctrl_flags flags;
u8 *src_buf, *dst_buf;
// int num_dma_symbol = 16;
int test_buf_size = num_dma_symbol*8;
dma_addr_t src_buf_dma;
dma_addr_t dst_buf_dma;
struct dma_device *chan_to_pl_dev = chan_to_pl->device;
struct dma_device *chan_to_ps_dev = chan_to_ps->device;
struct scatterlist chan_to_pl_sg[1];
struct scatterlist chan_to_ps_sg[1];
dma_cookie_t chan_to_pl_cookie;
dma_cookie_t chan_to_ps_cookie;
struct completion chan_to_pl_cmp;
struct completion chan_to_ps_cmp;
struct dma_async_tx_descriptor *chan_to_pl_d = NULL;
struct dma_async_tx_descriptor *chan_to_ps_d = NULL;
unsigned long chan_to_ps_tmo = msecs_to_jiffies(300000);
unsigned long chan_to_pl_tmo = msecs_to_jiffies(30000);
int test_idx;
for (test_idx=0; test_idxdev, src_buf, test_buf_size, DMA_MEM_TO_DEV);
if (dma_mapping_error(chan_to_pl_dev->dev, src_buf_dma)) {
printk("%s dma_loopback_test WARNING chan_to_pl_dev DMA mapping error\n", side_ch_compatible_str);
goto err_src_buf_dma_mapping;
}
dst_buf_dma = dma_map_single(chan_to_ps_dev->dev, dst_buf, test_buf_size, DMA_DEV_TO_MEM);
if (dma_mapping_error(chan_to_ps_dev->dev, dst_buf_dma)) {
printk("%s dma_loopback_test WARNING chan_to_ps_dev DMA mapping error\n", side_ch_compatible_str);
goto err_dst_buf_dma_mapping;
}
sg_init_table(chan_to_ps_sg, 1);
sg_init_table(chan_to_pl_sg, 1);
sg_dma_address(&chan_to_ps_sg[0]) = dst_buf_dma;
sg_dma_address(&chan_to_pl_sg[0]) = src_buf_dma;
sg_dma_len(&chan_to_ps_sg[0]) = test_buf_size;
sg_dma_len(&chan_to_pl_sg[0]) = test_buf_size;
chan_to_ps_d = chan_to_ps_dev->device_prep_slave_sg(chan_to_ps, chan_to_ps_sg, 1, DMA_DEV_TO_MEM, flags, NULL);
chan_to_pl_d = chan_to_pl_dev->device_prep_slave_sg(chan_to_pl, chan_to_pl_sg, 1, DMA_MEM_TO_DEV, flags, NULL);
if (!chan_to_ps_d || !chan_to_pl_d) {
printk("%s dma_loopback_test WARNING !chan_to_ps_d || !chan_to_pl_d\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
}
init_completion(&chan_to_pl_cmp);
chan_to_pl_d->callback = chan_to_pl_callback;
chan_to_pl_d->callback_param = &chan_to_pl_cmp;
chan_to_pl_cookie = chan_to_pl_d->tx_submit(chan_to_pl_d);
init_completion(&chan_to_ps_cmp);
chan_to_ps_d->callback = chan_to_ps_callback;
chan_to_ps_d->callback_param = &chan_to_ps_cmp;
chan_to_ps_cookie = chan_to_ps_d->tx_submit(chan_to_ps_d);
if (dma_submit_error(chan_to_pl_cookie) || dma_submit_error(chan_to_ps_cookie)) {
printk("%s dma_loopback_test WARNING dma_submit_error\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
}
dma_async_issue_pending(chan_to_pl);
dma_async_issue_pending(chan_to_ps);
chan_to_pl_tmo = wait_for_completion_timeout(&chan_to_pl_cmp, chan_to_pl_tmo);
status = dma_async_is_tx_complete(chan_to_pl, chan_to_pl_cookie, NULL, NULL);
if (chan_to_pl_tmo == 0) {
printk("%s dma_loopback_test chan_to_pl_tmo == 0\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
} else if (status != DMA_COMPLETE) {
printk("%s dma_loopback_test chan_to_pl status != DMA_COMPLETE\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
}
chan_to_ps_tmo = wait_for_completion_timeout(&chan_to_ps_cmp, chan_to_ps_tmo);
status = dma_async_is_tx_complete(chan_to_ps, chan_to_ps_cookie, NULL, NULL);
if (chan_to_ps_tmo == 0) {
printk("%s dma_loopback_test chan_to_ps_tmo == 0\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
} else if (status != DMA_COMPLETE) {
printk("%s dma_loopback_test chan_to_ps status != DMA_COMPLETE\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
}
dma_unmap_single(chan_to_pl_dev->dev, src_buf_dma, test_buf_size, DMA_MEM_TO_DEV);
dma_unmap_single(chan_to_ps_dev->dev, dst_buf_dma, test_buf_size, DMA_DEV_TO_MEM);
// test buf verification
for (i=0; idev, dst_buf_dma, test_buf_size, DMA_DEV_TO_MEM);
err_dst_buf_dma_mapping:
dma_unmap_single(chan_to_pl_dev->dev, src_buf_dma, test_buf_size, DMA_MEM_TO_DEV);
err_src_buf_dma_mapping:
err_dst_buf:
err = -4;
kfree((void*)dst_buf);
err_src_buf:
err = -3;
kfree(src_buf);
return(err);
}
#endif
static int init_side_channel(void) {
side_info_buf = kmalloc(max_side_info_buf_size, GFP_KERNEL);
if (!side_info_buf)
return(-1);
return(0);
}
static int get_side_info(int num_eq, int iq_len) {
// int err = 0;//, i;
struct scatterlist chan_to_ps_sg[1];
enum dma_status status;
enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
int num_dma_symbol, num_dma_symbol_per_trans, side_info_buf_size;
dma_addr_t side_info_buf_dma;
struct dma_device *chan_to_ps_dev = chan_to_ps->device;
struct completion chan_to_ps_cmp;
struct dma_async_tx_descriptor *chan_to_ps_d = NULL;
unsigned long chan_to_ps_tmo = msecs_to_jiffies(100);
if (side_info_buf==NULL) {
printk("%s get_side_info WARNING side_info_buf==NULL\n", side_ch_compatible_str);
return(-1);
}
status = dma_async_is_tx_complete(chan_to_ps, chan_to_ps_cookie, NULL, NULL);
if (status!=DMA_COMPLETE) {
printk("%s get_side_info WARNING status!=DMA_COMPLETE\n", side_ch_compatible_str);
return(-1);
}
set_user_nice(current, 10);
if (iq_len>0)
num_dma_symbol_per_trans = 1+iq_len;
else
num_dma_symbol_per_trans = HEADER_LEN + CSI_LEN + num_eq*EQUALIZER_LEN;
//set number of dma symbols expected to ps
num_dma_symbol = SIDE_CH_REG_M_AXIS_DATA_COUNT_read();
// printk("%s get_side_info m axis data count %d per trans %d\n", side_ch_compatible_str, num_dma_symbol, num_dma_symbol_per_trans);
num_dma_symbol = num_dma_symbol_per_trans*(num_dma_symbol/num_dma_symbol_per_trans);
// printk("%s get_side_info actual num dma symbol %d\n", side_ch_compatible_str, num_dma_symbol);
if (num_dma_symbol == 0)
return(-2);
side_info_buf_size = num_dma_symbol*8;
side_info_buf_dma = dma_map_single(chan_to_ps_dev->dev, side_info_buf, side_info_buf_size, DMA_DEV_TO_MEM);
if (dma_mapping_error(chan_to_ps_dev->dev, side_info_buf_dma)) {
printk("%s get_side_info WARNING chan_to_ps_dev DMA mapping error\n", side_ch_compatible_str);
return(-3);
}
sg_init_table(chan_to_ps_sg, 1);
sg_dma_address(&chan_to_ps_sg[0]) = side_info_buf_dma;
sg_dma_len(&chan_to_ps_sg[0]) = side_info_buf_size;
chan_to_ps_d = chan_to_ps_dev->device_prep_slave_sg(chan_to_ps, chan_to_ps_sg, 1, DMA_DEV_TO_MEM, flags, NULL);
if (!chan_to_ps_d) {
printk("%s get_side_info WARNING !chan_to_ps_d\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
}
init_completion(&chan_to_ps_cmp);
chan_to_ps_d->callback = chan_to_ps_callback;
chan_to_ps_d->callback_param = &chan_to_ps_cmp;
chan_to_ps_cookie = chan_to_ps_d->tx_submit(chan_to_ps_d);
if (dma_submit_error(chan_to_ps_cookie)) {
printk("%s get_side_info WARNING dma_submit_error\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
}
SIDE_CH_REG_NUM_DMA_SYMBOL_write(num_dma_symbol); //dma from fpga will start automatically
dma_async_issue_pending(chan_to_ps);
chan_to_ps_tmo = wait_for_completion_timeout(&chan_to_ps_cmp, chan_to_ps_tmo);
status = dma_async_is_tx_complete(chan_to_ps, chan_to_ps_cookie, NULL, NULL);
if (chan_to_ps_tmo == 0) {
printk("%s get_side_info WARNING chan_to_ps_tmo == 0\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
} else if (status != DMA_COMPLETE) {
printk("%s get_side_info WARNING chan_to_ps status != DMA_COMPLETE\n", side_ch_compatible_str);
goto err_dst_buf_with_unmap;
}
dma_unmap_single(chan_to_ps_dev->dev, side_info_buf_dma, side_info_buf_size, DMA_DEV_TO_MEM);
return(side_info_buf_size);
err_dst_buf_with_unmap:
dma_unmap_single(chan_to_ps_dev->dev, side_info_buf_dma, side_info_buf_size, DMA_DEV_TO_MEM);
return(-100);
}
// -----------------netlink recv and send-----------------
// should align with side_ch_ctl.c in user_space
#define ACTION_INVALID 0
#define ACTION_REG_WRITE 1
#define ACTION_REG_READ 2
#define ACTION_SIDE_INFO_GET 3
#define REG_TYPE_INVALID 0
#define REG_TYPE_HARDWARE 1
#define REG_TYPE_SOFTWARE 2
// #define NETLINK_USER 31
struct sock *nl_sk = NULL;
static void side_ch_nl_recv_msg(struct sk_buff *skb) {
struct nlmsghdr *nlh;
int pid;
struct sk_buff *skb_out;
int msg_size;
int *msg=(int*)side_info_buf;
int action_flag, reg_type, reg_idx;
u32 reg_val, *cmd_buf;
int res;
// printk(KERN_INFO "Entering: %s\n", __FUNCTION__);
// msg_size=strlen(msg);
nlh=(struct nlmsghdr*)skb->data;
cmd_buf = (u32*)nlmsg_data(nlh);
// printk(KERN_INFO "Netlink received msg payload:%s\n",(char*)nlmsg_data(nlh));
action_flag = cmd_buf[0];
reg_type = cmd_buf[1];
reg_idx = cmd_buf[2];
reg_val = cmd_buf[3];
// printk("%s recv msg: len %d action_flag %d reg_type %d reg_idx %d reg_val %u\n", side_ch_compatible_str, nlmsg_len(nlh), action_flag, reg_type, reg_idx, reg_val);
pid = nlh->nlmsg_pid; /*pid of sending process */
if (action_flag==ACTION_SIDE_INFO_GET) {
res = get_side_info(num_eq_init, iq_len_init);
// printk(KERN_INFO "%s recv msg: get_side_info(%d,%d) res %d\n", side_ch_compatible_str, num_eq_init, iq_len_init, res);
if (res>0) {
msg_size = res;
// printk("%s recv msg: %d %d %d %d %d %d %d %d\n", side_ch_compatible_str, msg[0], msg[1], msg[2], msg[3], msg[4], msg[5], msg[6], msg[7]);
} else {
msg_size = 4;
msg[0] = -2;
}
} else if (action_flag==ACTION_REG_READ) {
msg_size = 4;
// if (reg_idx<0 || reg_idx>31) {
// msg[0] = -3;
// printk("%s recv msg: invalid reg_idx\n", side_ch_compatible_str);
// } else {
msg[0] = reg_read(reg_idx*4);
// }
} else if (action_flag==ACTION_REG_WRITE) {
msg_size = 4;
// if (reg_idx<0 || reg_idx>31) {
// msg[0] = -4;
// printk("%s recv msg: invalid reg_idx\n", side_ch_compatible_str);
// } else {
msg[0] = 0;
reg_write(reg_idx*4, reg_val);
// }
} else {
msg_size = 4;
msg[0] = -1;
printk("%s recv msg: invalid action_flag\n", side_ch_compatible_str);
}
skb_out = nlmsg_new(msg_size,0);
if(!skb_out)
{
printk(KERN_ERR "Failed to allocate new skb\n");
return;
}
nlh=nlmsg_put(skb_out,0,0,NLMSG_DONE,msg_size,0);
NETLINK_CB(skb_out).dst_group = 0; /* not in mcast group */
memcpy(nlmsg_data(nlh),msg,msg_size);
res=nlmsg_unicast(nl_sk,skb_out,pid);
if(res<0)
printk(KERN_INFO "Error while sending bak to user\n");
}
static int dev_probe(struct platform_device *pdev) {
struct netlink_kernel_cfg cfg = {
.input = side_ch_nl_recv_msg,
};
struct device_node *np = pdev->dev.of_node;
struct resource *io;
int err=1, i;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe: match!\n", side_ch_compatible_str);
err = 0;
}
}
if (err)
return err;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe: io start 0x%p end 0x%p name %s flags 0x%08x desc %s\n", side_ch_compatible_str, (void*)io->start, (void*)io->end, io->name, (u32)io->flags, (char*)io->desc);
printk("%s dev_probe: base_addr 0x%p\n", side_ch_compatible_str, base_addr);
printk("%s dev_probe: succeed!\n", side_ch_compatible_str);
// --------------initialize netlink--------------
//nl_sk = netlink_kernel_create(&init_net, NETLINK_USER, &cfg);
nl_sk = netlink_kernel_create(&init_net, NETLINK_USERSOCK, &cfg);
if(!nl_sk) {
printk(KERN_ALERT "%s dev_probe: Error creating socket.\n", side_ch_compatible_str);
return -10;
}
//-----------------initialize fpga----------------
printk("%s dev_probe: num_eq_init %d iq_len_init %d\n",side_ch_compatible_str, num_eq_init, iq_len_init);
// disable potential any action from side channel
SIDE_CH_REG_MULTI_RST_write(4);
// SIDE_CH_REG_CONFIG_write(0X6001); // match addr1 and addr2; bit12 FC; bit13 addr1; bit14 addr2
SIDE_CH_REG_CONFIG_write(0x7001); // the most strict condition to prevent side channel action
SIDE_CH_REG_IQ_TRIGGER_write(10); // set iq trigger to rssi, which will never happen when rssi_th is 0
SIDE_CH_REG_NUM_EQ_write(num_eq_init); // capture CSI + 8*equalizer by default
if (iq_len_init>0) {//initialize the side channel into iq capture mode
//Max UDP 65507 bytes; (65507/8)-1 = 8187
if (iq_len_init>8187) {
iq_len_init = 8187;
printk("%s dev_probe: limit iq_len_init to 8187!\n",side_ch_compatible_str);
}
SIDE_CH_REG_IQ_CAPTURE_write(1);
SIDE_CH_REG_PRE_TRIGGER_LEN_write(8190);
SIDE_CH_REG_IQ_LEN_write(iq_len_init);
SIDE_CH_REG_IQ_TRIGGER_write(0); // trigger is set to fcs ok/nok (both)
}
SIDE_CH_REG_CONFIG_write(0x0001); // allow all packets by default; bit12 FC; bit13 addr1; bit14 addr2
//rst
for (i=0;i<8;i++)
SIDE_CH_REG_MULTI_RST_write(0);
for (i=0;i<32;i++)
SIDE_CH_REG_MULTI_RST_write(0xFFFFFFFF);
for (i=0;i<8;i++)
SIDE_CH_REG_MULTI_RST_write(0);
// chan_to_pl = dma_request_slave_channel(&(pdev->dev), "rx_dma_mm2s");
// if (IS_ERR(chan_to_pl)) {
// err = PTR_ERR(chan_to_pl);
// pr_err("%s dev_probe: No channel to PL. %d\n",side_ch_compatible_str,err);
// goto free_chan_to_pl;
// }
chan_to_ps = dma_request_chan(&(pdev->dev), "tx_dma_s2mm");
if (IS_ERR(chan_to_ps) || chan_to_ps==NULL) {
err = PTR_ERR(chan_to_ps);
if (err != -EPROBE_DEFER) {
pr_err("%s dev_probe: No chan_to_ps ret %d chan_to_ps 0x%p\n",side_ch_compatible_str, err, chan_to_ps);
goto free_chan_to_ps;
}
}
printk("%s dev_probe: DMA channel setup successfully. chan_to_pl 0x%p chan_to_ps 0x%p\n",side_ch_compatible_str, chan_to_pl, chan_to_ps);
// res = dma_loopback_test(3, 512);
// printk(KERN_INFO "dma_loopback_test(3, 512) res %d\n", res);
err = init_side_channel();
printk("%s dev_probe: init_side_channel() err %d\n",side_ch_compatible_str, err);
return(err);
// err = dma_loopback_test(7, 512);
// if (err == 0)
// return(err);
// else
// dma_release_channel(chan_to_ps);
free_chan_to_ps:
err = -2;
dma_release_channel(chan_to_ps);
return err;
// free_chan_to_pl:
// err = -1;
// dma_release_channel(chan_to_pl);
// return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove: release nl_sk\n", side_ch_compatible_str);
netlink_kernel_release(nl_sk);
// pr_info("%s dev_remove: dropped chan_to_pl 0x%p\n", side_ch_compatible_str, chan_to_pl);
// if (chan_to_pl != NULL) {
// pr_info("%s dev_remove: dropped channel %s\n", side_ch_compatible_str, dma_chan_name(chan_to_pl));
// // dmaengine_terminate_all(chan_to_pl); //this also terminate sdr.ko. do not use
// dma_release_channel(chan_to_pl);
// }
pr_info("%s dev_remove: dropped chan_to_ps 0x%p\n", side_ch_compatible_str, chan_to_ps);
if (chan_to_pl != NULL) {
pr_info("%s dev_remove: dropped channel %s\n", side_ch_compatible_str, dma_chan_name(chan_to_ps));
// dmaengine_terminate_all(chan_to_ps); //this also terminate sdr.ko. do not use
dma_release_channel(chan_to_ps);
}
if (side_info_buf != NULL)
kfree(side_info_buf);
printk("%s dev_remove: base_addr 0x%p\n", side_ch_compatible_str, base_addr);
printk("%s dev_remove: succeed!\n", side_ch_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,side_ch",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,side_ch");
MODULE_LICENSE("GPL v2");
================================================
FILE: driver/side_ch/side_ch.h
================================================
// Author: Xianjun Jiao
// SPDX-FileCopyrightText: 2019 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
// ---------------------------------------side channel-------------------------------
const char *side_ch_compatible_str = "sdr,side_ch";
//align with side_ch_control.v and all related user space, remote files
#define CSI_LEN 56 // length of single CSI
#define EQUALIZER_LEN (56-4) // for non HT, four {32767,32767} will be padded to achieve 52 (non HT should have 48)
#define HEADER_LEN 2 //timestamp and frequency offset
#define MAX_NUM_DMA_SYMBOL 8192 //align with side_ch.v side_ch.h
#define SIDE_CH_REG_MULTI_RST_ADDR (0*4)
#define SIDE_CH_REG_CONFIG_ADDR (1*4)
#define SIDE_CH_REG_NUM_DMA_SYMBOL_ADDR (2*4) //low 16bit to PS; high 16bit to PL
#define SIDE_CH_REG_IQ_CAPTURE_ADDR (3*4)
#define SIDE_CH_REG_NUM_EQ_ADDR (4*4)
#define SIDE_CH_REG_FC_TARGET_ADDR (5*4)
#define SIDE_CH_REG_ADDR1_TARGET_ADDR (6*4)
#define SIDE_CH_REG_ADDR2_TARGET_ADDR (7*4)
#define SIDE_CH_REG_IQ_TRIGGER_ADDR (8*4)
#define SIDE_CH_REG_RSSI_TH_ADDR (9*4)
#define SIDE_CH_REG_GAIN_TH_ADDR (10*4)
#define SIDE_CH_REG_PRE_TRIGGER_LEN_ADDR (11*4)
#define SIDE_CH_REG_IQ_LEN_ADDR (12*4)
#define SIDE_CH_REG_M_AXIS_DATA_COUNT_ADDR (20*4)
================================================
FILE: driver/sysfs_intf.c
================================================
// Author: Xianjun Jiao, Michael Mehari, Wei Liu
// SPDX-FileCopyrightText: 2019 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
// #define TX_INTF_IQ_WRITE_TXT_FORMAT 1//while using TXT format, the txt file size should <= 4096!!!
#define TX_INTF_IQ_WRITE_BIN_FORMAT 1
#ifdef TX_INTF_IQ_WRITE_TXT_FORMAT
static int is_valid_iq_number(int c) {
if (c==32 || (c>=44 && c<=57))
return(1);
else
return(0);
}
static ssize_t openwifi_tx_intf_bin_iq_write(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
struct platform_device *pdev = to_platform_device(kobj_to_dev(kobj));
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
int ret, i, q, num_iq;
char *line;
char *ptr = buf;
printk("%s openwifi_tx_intf_bin_iq_write: count %d\n", sdr_compatible_str, (int)count);
num_iq = 0;
line = ptr;
while (1) {
ret = sscanf(line, "%d,%d\n", &i, &q);
if (ret == 0) {
printk("%s openwifi_tx_intf_bin_iq_write: sscanf ret 0\n", sdr_compatible_str);
break;
} else if (ret != 2) {
printk("%s openwifi_tx_intf_bin_iq_write: sscanf ret %d i %d q %d num_iq %d\n", sdr_compatible_str, ret, i, q, num_iq);
return -EINVAL;
}
priv->tx_intf_arbitrary_iq[num_iq] = ( (q<<16)|(i&0xFFFF) );
num_iq++;
if (num_iq == 512) {
printk("%s openwifi_tx_intf_bin_iq_write: num_iq reach 512\n", sdr_compatible_str);
break;
}
//go to the next line
while(is_valid_iq_number(ptr[0]))
ptr++;
while( (is_valid_iq_number(ptr[0])==0)&&(ptr[0]!=0) )
ptr++;
if (ptr[0] == 0) {
printk("%s openwifi_tx_intf_bin_iq_write: ptr[0] == 0\n", sdr_compatible_str);
break;
}
line = ptr;
}
priv->tx_intf_arbitrary_iq_num = num_iq;
printk("%s openwifi_tx_intf_bin_iq_write: num_iq %d\n", sdr_compatible_str, num_iq);
//print i/q
for (i=0; itx_intf_arbitrary_iq[i]&0xffff), (short)((priv->tx_intf_arbitrary_iq[i]>>16)&0xffff) );
return count;
}
#else
static ssize_t openwifi_tx_intf_bin_iq_write(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
struct platform_device *pdev = to_platform_device(kobj_to_dev(kobj));
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
int num_iq, i;
printk("%s openwifi_tx_intf_bin_iq_write: count %d\n", sdr_compatible_str, (int)count);
if ((count%4) != 0) {
printk("%s openwifi_tx_intf_bin_iq_write: count is not integer times of 4!\n", sdr_compatible_str);
return -EINVAL;
}
num_iq = count/4;
priv->tx_intf_arbitrary_iq_num = num_iq;
for (i=0; itx_intf_arbitrary_iq[i] = (*((u32*)(buf+(i*4))));
}
// printk("%s openwifi_tx_intf_bin_iq_write: num_iq %d\n", sdr_compatible_str, num_iq);
// //print i/q
// for (i=0; itx_intf_arbitrary_iq[i]&0xffff), (short)((priv->tx_intf_arbitrary_iq[i]>>16)&0xffff) );
return count;
}
#endif
static ssize_t openwifi_tx_intf_bin_iq_read(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
struct platform_device *pdev = to_platform_device(kobj_to_dev(kobj));
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
int num_iq, ret_size, i;
if (off)
return 0;
num_iq = priv->tx_intf_arbitrary_iq_num;
// printk("%s openwifi_tx_intf_bin_iq_read: num_iq %d\n", sdr_compatible_str, num_iq);
// //print i/q
// for (i=0; itx_intf_arbitrary_iq[i]&0xffff), (short)((priv->tx_intf_arbitrary_iq[i]>>16)&0xffff) );
ret_size = sprintf(buf, "%d\n", num_iq);
if (num_iq==0 || num_iq>512) {
ret_size = ret_size + sprintf(buf+ret_size, "num_iq is wrong!\n");
return ret_size;
}
//print i
for (i=0; itx_intf_arbitrary_iq[i]&0xffff) );
ret_size = ret_size + sprintf(buf+ret_size, "\n");
//print q
for (i=0; itx_intf_arbitrary_iq[i]>>16)&0xffff) );
ret_size = ret_size + sprintf(buf+ret_size, "\n");
return ret_size;
}
static ssize_t tx_intf_iq_ctl_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->tx_intf_iq_ctl);
}
static ssize_t tx_intf_iq_ctl_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
int i;
int ret = kstrtol(buf, 10, &readin);
priv->tx_intf_iq_ctl = readin;
tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_write(1); // switch to iq mode
printk("%s tx_intf_iq_ctl_store: Will send %d I/Q\n", sdr_compatible_str, priv->tx_intf_arbitrary_iq_num);
for (i=0; itx_intf_arbitrary_iq_num; i++) {
tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_write(priv->tx_intf_arbitrary_iq[i]);
}
tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_write(3); // start send
tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_write(0);
return ret ? ret : len;
}
static DEVICE_ATTR(tx_intf_iq_ctl, S_IRUGO | S_IWUSR, tx_intf_iq_ctl_show, tx_intf_iq_ctl_store);
static struct attribute *tx_intf_attributes[] = {
&dev_attr_tx_intf_iq_ctl.attr,
NULL,
};
static const struct attribute_group tx_intf_attribute_group = {
.attrs = tx_intf_attributes,
};
static ssize_t stat_enable_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.stat_enable);
}
static ssize_t stat_enable_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.stat_enable = readin;
return ret ? ret : len;
}
static ssize_t tx_prio_queue_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
u32 i, ret_size = 0;
for (i=0; istat.tx_prio_num[i],
priv->stat.tx_prio_interrupt_num[i],
priv->stat.tx_prio_stop0_fake_num[i],
priv->stat.tx_prio_stop0_real_num[i],
priv->stat.tx_prio_stop1_num[i],
priv->stat.tx_prio_wakeup_num[i],
priv->stat.tx_queue_num[i],
priv->stat.tx_queue_interrupt_num[i],
priv->stat.tx_queue_stop0_fake_num[i],
priv->stat.tx_queue_stop0_real_num[i],
priv->stat.tx_queue_stop1_num[i],
priv->stat.tx_queue_wakeup_num[i]);
}
return ret_size;
}
static ssize_t tx_prio_queue_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
u32 i;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
for (i=0; istat.tx_prio_num[i] = 0;
priv->stat.tx_prio_interrupt_num[i] = 0;
priv->stat.tx_prio_stop0_fake_num[i] = 0;
priv->stat.tx_prio_stop0_real_num[i] = 0;
priv->stat.tx_prio_stop1_num[i] = 0;
priv->stat.tx_prio_wakeup_num[i] = 0;
}
for (i=0; istat.tx_queue_num[i] = 0;
priv->stat.tx_queue_interrupt_num[i] = 0;
priv->stat.tx_queue_stop0_fake_num[i] = 0;
priv->stat.tx_queue_stop0_real_num[i] = 0;
priv->stat.tx_queue_stop1_num[i] = 0;
priv->stat.tx_queue_wakeup_num[i] = 0;
}
return ret ? ret : len;
}
static ssize_t tx_data_pkt_need_ack_num_total_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.tx_data_pkt_need_ack_num_total_fail);
}
static ssize_t tx_data_pkt_need_ack_num_total_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.tx_data_pkt_need_ack_num_total_fail = readin;
return ret ? ret : len;
}
static ssize_t tx_data_pkt_need_ack_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.tx_data_pkt_need_ack_num_total);
}
static ssize_t tx_data_pkt_need_ack_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.tx_data_pkt_need_ack_num_total = readin;
return ret ? ret : len;
}
static ssize_t tx_mgmt_pkt_need_ack_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.tx_mgmt_pkt_need_ack_num_total);
}
static ssize_t tx_mgmt_pkt_need_ack_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.tx_mgmt_pkt_need_ack_num_total = readin;
return ret ? ret : len;
}
static ssize_t tx_mgmt_pkt_need_ack_num_total_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.tx_mgmt_pkt_need_ack_num_total_fail);
}
static ssize_t tx_mgmt_pkt_need_ack_num_total_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.tx_mgmt_pkt_need_ack_num_total_fail = readin;
return ret ? ret : len;
}
static ssize_t tx_data_pkt_need_ack_num_retx_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u %u %u %u %u %u\n",
priv->stat.tx_data_pkt_need_ack_num_retx[0],
priv->stat.tx_data_pkt_need_ack_num_retx[1],
priv->stat.tx_data_pkt_need_ack_num_retx[2],
priv->stat.tx_data_pkt_need_ack_num_retx[3],
priv->stat.tx_data_pkt_need_ack_num_retx[4],
priv->stat.tx_data_pkt_need_ack_num_retx[5]);
}
static ssize_t tx_data_pkt_need_ack_num_retx_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin), i;
for (i=0; i<6; i++)
priv->stat.tx_data_pkt_need_ack_num_retx[i] = readin;
return ret ? ret : len;
}
static ssize_t tx_mgmt_pkt_need_ack_num_retx_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u %u %u\n",
priv->stat.tx_mgmt_pkt_need_ack_num_retx[0],
priv->stat.tx_mgmt_pkt_need_ack_num_retx[1],
priv->stat.tx_mgmt_pkt_need_ack_num_retx[2]);
}
static ssize_t tx_mgmt_pkt_need_ack_num_retx_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin), i;
for (i=0; i<3; i++)
priv->stat.tx_mgmt_pkt_need_ack_num_retx[i] = readin;
return ret ? ret : len;
}
static ssize_t tx_data_pkt_need_ack_num_retx_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u %u %u %u %u %u\n",
priv->stat.tx_data_pkt_need_ack_num_retx_fail[0],
priv->stat.tx_data_pkt_need_ack_num_retx_fail[1],
priv->stat.tx_data_pkt_need_ack_num_retx_fail[2],
priv->stat.tx_data_pkt_need_ack_num_retx_fail[3],
priv->stat.tx_data_pkt_need_ack_num_retx_fail[4],
priv->stat.tx_data_pkt_need_ack_num_retx_fail[5]);
}
static ssize_t tx_data_pkt_need_ack_num_retx_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin), i;
for (i=0; i<6; i++)
priv->stat.tx_data_pkt_need_ack_num_retx_fail[i] = readin;
return ret ? ret : len;
}
static ssize_t tx_mgmt_pkt_need_ack_num_retx_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u %u %u\n",
priv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[0],
priv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[1],
priv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[2]);
}
static ssize_t tx_mgmt_pkt_need_ack_num_retx_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin), i;
for (i=0; i<3; i++)
priv->stat.tx_mgmt_pkt_need_ack_num_retx_fail[i] = readin;
return ret ? ret : len;
}
static ssize_t tx_data_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
bool use_ht_rate = ((priv->stat.tx_data_pkt_mcs_realtime&0x80000000)!=0);
u32 rate_hw_value = (priv->stat.tx_data_pkt_mcs_realtime&0x7fffffff);
return sprintf(buf, "%uM\n", (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]));
}
static ssize_t tx_data_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.tx_data_pkt_mcs_realtime = readin;
return ret ? ret : len;
}
static ssize_t tx_mgmt_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
bool use_ht_rate = ((priv->stat.tx_mgmt_pkt_mcs_realtime&0x80000000)!=0);
u32 rate_hw_value = (priv->stat.tx_mgmt_pkt_mcs_realtime&0x7fffffff);
return sprintf(buf, "%uM\n", (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]));
}
static ssize_t tx_mgmt_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.tx_mgmt_pkt_mcs_realtime = readin;
return ret ? ret : len;
}
static ssize_t tx_mgmt_pkt_fail_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
bool use_ht_rate = ((priv->stat.tx_mgmt_pkt_fail_mcs_realtime&0x80000000)!=0);
u32 rate_hw_value = (priv->stat.tx_mgmt_pkt_fail_mcs_realtime&0x7fffffff);
return sprintf(buf, "%uM\n", (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]));
}
static ssize_t tx_mgmt_pkt_fail_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.tx_mgmt_pkt_fail_mcs_realtime = readin;
return ret ? ret : len;
}
static ssize_t tx_data_pkt_fail_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
bool use_ht_rate = ((priv->stat.tx_data_pkt_fail_mcs_realtime&0x80000000)!=0);
u32 rate_hw_value = (priv->stat.tx_data_pkt_fail_mcs_realtime&0x7fffffff);
return sprintf(buf, "%uM\n", (use_ht_rate == false ? wifi_rate_all[rate_hw_value] : wifi_rate_all[rate_hw_value + 12]));
}
static ssize_t tx_data_pkt_fail_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.tx_data_pkt_fail_mcs_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_target_sender_mac_addr_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%08x\n", reverse32(priv->stat.rx_target_sender_mac_addr));
}
static ssize_t rx_target_sender_mac_addr_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
u32 readin;
u32 ret = kstrtouint(buf, 16, &readin);
priv->stat.rx_target_sender_mac_addr = reverse32(readin);
return ret ? ret : len;
}
static ssize_t rx_data_ok_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_data_ok_agc_gain_value_realtime);
}
static ssize_t rx_data_ok_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_data_ok_agc_gain_value_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_mgmt_ok_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_mgmt_ok_agc_gain_value_realtime);
}
static ssize_t rx_mgmt_ok_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_mgmt_ok_agc_gain_value_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_data_fail_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_data_fail_agc_gain_value_realtime);
}
static ssize_t rx_data_fail_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_data_fail_agc_gain_value_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_mgmt_fail_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_mgmt_fail_agc_gain_value_realtime);
}
static ssize_t rx_mgmt_fail_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_mgmt_fail_agc_gain_value_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_ack_ok_agc_gain_value_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_ack_ok_agc_gain_value_realtime);
}
static ssize_t rx_ack_ok_agc_gain_value_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_ack_ok_agc_gain_value_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_monitor_all_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_monitor_all);
}
static ssize_t rx_monitor_all_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
u32 filter_flag;
priv->stat.rx_monitor_all = readin;
filter_flag = xpu_api->XPU_REG_FILTER_FLAG_read();
if (readin>0) {// set to fpga
filter_flag = (filter_flag|MONITOR_ALL);
} else {
filter_flag = (filter_flag&(~MONITOR_ALL));
}
xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag);
return ret ? ret : len;
}
static ssize_t rx_data_pkt_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_data_pkt_num_total);
}
static ssize_t rx_data_pkt_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_data_pkt_num_total = readin;
return ret ? ret : len;
}
static ssize_t rx_data_pkt_num_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_data_pkt_num_fail);
}
static ssize_t rx_data_pkt_num_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_data_pkt_num_fail = readin;
return ret ? ret : len;
}
static ssize_t rx_mgmt_pkt_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_mgmt_pkt_num_total);
}
static ssize_t rx_mgmt_pkt_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_mgmt_pkt_num_total = readin;
return ret ? ret : len;
}
static ssize_t rx_mgmt_pkt_num_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_mgmt_pkt_num_fail);
}
static ssize_t rx_mgmt_pkt_num_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_mgmt_pkt_num_fail = readin;
return ret ? ret : len;
}
static ssize_t rx_ack_pkt_num_total_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_ack_pkt_num_total);
}
static ssize_t rx_ack_pkt_num_total_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_ack_pkt_num_total = readin;
return ret ? ret : len;
}
static ssize_t rx_ack_pkt_num_fail_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.rx_ack_pkt_num_fail);
}
static ssize_t rx_ack_pkt_num_fail_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_ack_pkt_num_fail = readin;
return ret ? ret : len;
}
static ssize_t rx_data_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%uM\n", wifi_rate_table[priv->stat.rx_data_pkt_mcs_realtime]);
}
static ssize_t rx_data_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_data_pkt_mcs_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_data_pkt_fail_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%uM\n", wifi_rate_table[priv->stat.rx_data_pkt_fail_mcs_realtime]);
}
static ssize_t rx_data_pkt_fail_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_data_pkt_fail_mcs_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_mgmt_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%uM\n", wifi_rate_table[priv->stat.rx_mgmt_pkt_mcs_realtime]);
}
static ssize_t rx_mgmt_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_mgmt_pkt_mcs_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_mgmt_pkt_fail_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%uM\n", wifi_rate_table[priv->stat.rx_mgmt_pkt_fail_mcs_realtime]);
}
static ssize_t rx_mgmt_pkt_fail_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_mgmt_pkt_fail_mcs_realtime = readin;
return ret ? ret : len;
}
static ssize_t rx_ack_pkt_mcs_realtime_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%uM\n", wifi_rate_table[priv->stat.rx_ack_pkt_mcs_realtime]);
}
static ssize_t rx_ack_pkt_mcs_realtime_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.rx_ack_pkt_mcs_realtime = readin;
return ret ? ret : len;
}
static ssize_t restrict_freq_mhz_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.restrict_freq_mhz);
}
static ssize_t restrict_freq_mhz_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
static struct ieee80211_conf channel_conf_tmp;
static struct ieee80211_channel channel_tmp;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
channel_conf_tmp.chandef.chan = (&channel_tmp);
priv->stat.restrict_freq_mhz = readin;
channel_conf_tmp.chandef.chan->center_freq = priv->stat.restrict_freq_mhz;
ad9361_rf_set_channel(dev, &channel_conf_tmp);
return ret ? ret : len;
}
static ssize_t csma_cfg0_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
u32 reg_val;
reg_val = xpu_api->XPU_REG_FORCE_IDLE_MISC_read();
priv->stat.csma_cfg0 = reg_val;
return sprintf(buf, "nav_disable %d difs_disable %d eifs_disable %d eifs_by_rx_fail_disable %d eifs_by_tx_fail_disable %d cw_override %d cw override val %d wait_after_decode_top %d\n",
(reg_val>>31)&1,
(reg_val>>30)&1,
(reg_val>>29)&1,
(reg_val>>27)&1,
(reg_val>>26)&1,
(reg_val>>28)&1,
(reg_val>>16)&0xf,
(reg_val>>0)&0xff);
}
static ssize_t csma_cfg0_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
u32 disable_flag, idx_from_msb, reg_val;
u32 readin;
u32 ret = kstrtouint(buf, 16, &readin);
disable_flag = (readin&0xf);
idx_from_msb = ((readin>>4)&0xf);
reg_val = xpu_api->XPU_REG_FORCE_IDLE_MISC_read();
if (disable_flag)
reg_val = (reg_val|(1<<(31-idx_from_msb)));
else
reg_val = (reg_val&(~(1<<(31-idx_from_msb))));
xpu_api->XPU_REG_FORCE_IDLE_MISC_write(reg_val);
priv->stat.csma_cfg0 = reg_val;
return ret ? ret : len;
}
static ssize_t cw_max_min_cfg_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
u32 ret_size, reg_val;
reg_val = xpu_api->XPU_REG_CSMA_CFG_read();
ret_size = sprintf(buf, "FPGA cw max min for q3 to q0: %d %d; %d %d; %d %d; %d %d\n",
(1<<((reg_val>>28)&0xF))-1,
(1<<((reg_val>>24)&0xF))-1,
(1<<((reg_val>>20)&0xF))-1,
(1<<((reg_val>>16)&0xF))-1,
(1<<((reg_val>>12)&0xF))-1,
(1<<((reg_val>> 8)&0xF))-1,
(1<<((reg_val>> 4)&0xF))-1,
(1<<((reg_val>> 0)&0xF))-1);
ret_size = ret_size + sprintf(buf+ret_size, "FPGA cw max min for q3 to q0: %08x\n",reg_val);
if (priv->stat.cw_max_min_cfg) {
reg_val = priv->stat.cw_max_min_cfg;
ret_size = ret_size + sprintf(buf+ret_size, "SYSFS cw max min for q3 to q0: %d %d; %d %d; %d %d; %d %d\n",
(1<<((reg_val>>28)&0xF))-1,
(1<<((reg_val>>24)&0xF))-1,
(1<<((reg_val>>20)&0xF))-1,
(1<<((reg_val>>16)&0xF))-1,
(1<<((reg_val>>12)&0xF))-1,
(1<<((reg_val>> 8)&0xF))-1,
(1<<((reg_val>> 4)&0xF))-1,
(1<<((reg_val>> 0)&0xF))-1);
ret_size = ret_size + sprintf(buf+ret_size, "SYSFS cw max min for q3 to q0: %08x\n",reg_val);
}
return ret_size;
}
static ssize_t cw_max_min_cfg_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
u32 readin;
u32 ret = kstrtouint(buf, 16, &readin);
// printk("%s %d\n", buf, readin);
priv->stat.cw_max_min_cfg = readin;
if (readin)
xpu_api->XPU_REG_CSMA_CFG_write(readin);
return ret ? ret : len;
}
static ssize_t dbg_ch0_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.dbg_ch0);
}
static ssize_t dbg_ch0_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.dbg_ch0 = readin;
// xpu_api->XPU_REG_DIFS_ADVANCE_write((readin<<16)|2); //us. bit31~16 max pkt length threshold
// rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(readin<<16); //bit31~16 max pkt length threshold
// openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((readin<<16)|1); //bit1 enable soft decoding; bit31~16 max pkt length threshold
return ret ? ret : len;
}
static ssize_t dbg_ch1_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.dbg_ch1);
}
static ssize_t dbg_ch1_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.dbg_ch1 = readin;
return ret ? ret : len;
}
static ssize_t dbg_ch2_show(struct device *input_dev, struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
return sprintf(buf, "%u\n", priv->stat.dbg_ch2);
}
static ssize_t dbg_ch2_store(struct device *input_dev, struct device_attribute *attr, const char *buf, size_t len)
{
struct platform_device *pdev = to_platform_device(input_dev);
struct ieee80211_hw *dev = platform_get_drvdata(pdev);
struct openwifi_priv *priv = dev->priv;
long readin;
u32 ret = kstrtol(buf, 10, &readin);
priv->stat.dbg_ch2 = readin;
return ret ? ret : len;
}
static DEVICE_ATTR(stat_enable, S_IRUGO | S_IWUSR, stat_enable_show, stat_enable_store);
static DEVICE_ATTR(tx_prio_queue, S_IRUGO | S_IWUSR, tx_prio_queue_show, tx_prio_queue_store);
static DEVICE_ATTR(tx_data_pkt_need_ack_num_total, S_IRUGO | S_IWUSR, tx_data_pkt_need_ack_num_total_show, tx_data_pkt_need_ack_num_total_store);
static DEVICE_ATTR(tx_data_pkt_need_ack_num_total_fail, S_IRUGO | S_IWUSR, tx_data_pkt_need_ack_num_total_fail_show, tx_data_pkt_need_ack_num_total_fail_store);
static DEVICE_ATTR(tx_data_pkt_need_ack_num_retx, S_IRUGO | S_IWUSR, tx_data_pkt_need_ack_num_retx_show, tx_data_pkt_need_ack_num_retx_store);
static DEVICE_ATTR(tx_data_pkt_need_ack_num_retx_fail, S_IRUGO | S_IWUSR, tx_data_pkt_need_ack_num_retx_fail_show, tx_data_pkt_need_ack_num_retx_fail_store);
static DEVICE_ATTR(tx_data_pkt_mcs_realtime, S_IRUGO | S_IWUSR, tx_data_pkt_mcs_realtime_show, tx_data_pkt_mcs_realtime_store);
static DEVICE_ATTR(tx_data_pkt_fail_mcs_realtime, S_IRUGO | S_IWUSR, tx_data_pkt_fail_mcs_realtime_show, tx_data_pkt_fail_mcs_realtime_store);
static DEVICE_ATTR(tx_mgmt_pkt_need_ack_num_total, S_IRUGO | S_IWUSR, tx_mgmt_pkt_need_ack_num_total_show, tx_mgmt_pkt_need_ack_num_total_store);
static DEVICE_ATTR(tx_mgmt_pkt_need_ack_num_total_fail, S_IRUGO | S_IWUSR, tx_mgmt_pkt_need_ack_num_total_fail_show, tx_mgmt_pkt_need_ack_num_total_fail_store);
static DEVICE_ATTR(tx_mgmt_pkt_need_ack_num_retx, S_IRUGO | S_IWUSR, tx_mgmt_pkt_need_ack_num_retx_show, tx_mgmt_pkt_need_ack_num_retx_store);
static DEVICE_ATTR(tx_mgmt_pkt_need_ack_num_retx_fail, S_IRUGO | S_IWUSR, tx_mgmt_pkt_need_ack_num_retx_fail_show, tx_mgmt_pkt_need_ack_num_retx_fail_store);
static DEVICE_ATTR(tx_mgmt_pkt_mcs_realtime, S_IRUGO | S_IWUSR, tx_mgmt_pkt_mcs_realtime_show, tx_mgmt_pkt_mcs_realtime_store);
static DEVICE_ATTR(tx_mgmt_pkt_fail_mcs_realtime, S_IRUGO | S_IWUSR, tx_mgmt_pkt_fail_mcs_realtime_show, tx_mgmt_pkt_fail_mcs_realtime_store);
static DEVICE_ATTR(rx_target_sender_mac_addr, S_IRUGO | S_IWUSR, rx_target_sender_mac_addr_show, rx_target_sender_mac_addr_store);
static DEVICE_ATTR(rx_data_ok_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_data_ok_agc_gain_value_realtime_show, rx_data_ok_agc_gain_value_realtime_store);
static DEVICE_ATTR(rx_data_fail_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_data_fail_agc_gain_value_realtime_show, rx_data_fail_agc_gain_value_realtime_store);
static DEVICE_ATTR(rx_mgmt_ok_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_mgmt_ok_agc_gain_value_realtime_show, rx_mgmt_ok_agc_gain_value_realtime_store);
static DEVICE_ATTR(rx_mgmt_fail_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_mgmt_fail_agc_gain_value_realtime_show, rx_mgmt_fail_agc_gain_value_realtime_store);
static DEVICE_ATTR(rx_ack_ok_agc_gain_value_realtime, S_IRUGO | S_IWUSR, rx_ack_ok_agc_gain_value_realtime_show, rx_ack_ok_agc_gain_value_realtime_store);
static DEVICE_ATTR(rx_monitor_all, S_IRUGO | S_IWUSR, rx_monitor_all_show, rx_monitor_all_store);
static DEVICE_ATTR(rx_data_pkt_num_total, S_IRUGO | S_IWUSR, rx_data_pkt_num_total_show, rx_data_pkt_num_total_store);
static DEVICE_ATTR(rx_data_pkt_num_fail, S_IRUGO | S_IWUSR, rx_data_pkt_num_fail_show, rx_data_pkt_num_fail_store);
static DEVICE_ATTR(rx_mgmt_pkt_num_total, S_IRUGO | S_IWUSR, rx_mgmt_pkt_num_total_show, rx_mgmt_pkt_num_total_store);
static DEVICE_ATTR(rx_mgmt_pkt_num_fail, S_IRUGO | S_IWUSR, rx_mgmt_pkt_num_fail_show, rx_mgmt_pkt_num_fail_store);
static DEVICE_ATTR(rx_ack_pkt_num_total, S_IRUGO | S_IWUSR, rx_ack_pkt_num_total_show, rx_ack_pkt_num_total_store);
static DEVICE_ATTR(rx_ack_pkt_num_fail, S_IRUGO | S_IWUSR, rx_ack_pkt_num_fail_show, rx_ack_pkt_num_fail_store);
static DEVICE_ATTR(rx_data_pkt_mcs_realtime, S_IRUGO | S_IWUSR, rx_data_pkt_mcs_realtime_show, rx_data_pkt_mcs_realtime_store);
static DEVICE_ATTR(rx_data_pkt_fail_mcs_realtime, S_IRUGO | S_IWUSR, rx_data_pkt_fail_mcs_realtime_show, rx_data_pkt_fail_mcs_realtime_store);
static DEVICE_ATTR(rx_mgmt_pkt_mcs_realtime, S_IRUGO | S_IWUSR, rx_mgmt_pkt_mcs_realtime_show, rx_mgmt_pkt_mcs_realtime_store);
static DEVICE_ATTR(rx_mgmt_pkt_fail_mcs_realtime, S_IRUGO | S_IWUSR, rx_mgmt_pkt_fail_mcs_realtime_show, rx_mgmt_pkt_fail_mcs_realtime_store);
static DEVICE_ATTR(rx_ack_pkt_mcs_realtime, S_IRUGO | S_IWUSR, rx_ack_pkt_mcs_realtime_show, rx_ack_pkt_mcs_realtime_store);
static DEVICE_ATTR(restrict_freq_mhz, S_IRUGO | S_IWUSR, restrict_freq_mhz_show, restrict_freq_mhz_store);
static DEVICE_ATTR(csma_cfg0, S_IRUGO | S_IWUSR, csma_cfg0_show, csma_cfg0_store);
static DEVICE_ATTR(cw_max_min_cfg, S_IRUGO | S_IWUSR, cw_max_min_cfg_show, cw_max_min_cfg_store);
static DEVICE_ATTR(dbg_ch0, S_IRUGO | S_IWUSR, dbg_ch0_show, dbg_ch0_store);
static DEVICE_ATTR(dbg_ch1, S_IRUGO | S_IWUSR, dbg_ch1_show, dbg_ch1_store);
static DEVICE_ATTR(dbg_ch2, S_IRUGO | S_IWUSR, dbg_ch2_show, dbg_ch2_store);
static struct attribute *stat_attributes[] = {
&dev_attr_stat_enable.attr,
&dev_attr_tx_prio_queue.attr,
&dev_attr_tx_data_pkt_need_ack_num_total.attr,
&dev_attr_tx_data_pkt_need_ack_num_total_fail.attr,
&dev_attr_tx_data_pkt_need_ack_num_retx.attr,
&dev_attr_tx_data_pkt_need_ack_num_retx_fail.attr,
&dev_attr_tx_data_pkt_mcs_realtime.attr,
&dev_attr_tx_data_pkt_fail_mcs_realtime.attr,
&dev_attr_tx_mgmt_pkt_need_ack_num_total.attr,
&dev_attr_tx_mgmt_pkt_need_ack_num_total_fail.attr,
&dev_attr_tx_mgmt_pkt_need_ack_num_retx.attr,
&dev_attr_tx_mgmt_pkt_need_ack_num_retx_fail.attr,
&dev_attr_tx_mgmt_pkt_mcs_realtime.attr,
&dev_attr_tx_mgmt_pkt_fail_mcs_realtime.attr,
&dev_attr_rx_target_sender_mac_addr.attr,
&dev_attr_rx_data_ok_agc_gain_value_realtime.attr,
&dev_attr_rx_data_fail_agc_gain_value_realtime.attr,
&dev_attr_rx_mgmt_ok_agc_gain_value_realtime.attr,
&dev_attr_rx_mgmt_fail_agc_gain_value_realtime.attr,
&dev_attr_rx_ack_ok_agc_gain_value_realtime.attr,
&dev_attr_rx_monitor_all.attr,
&dev_attr_rx_data_pkt_num_total.attr,
&dev_attr_rx_data_pkt_num_fail.attr,
&dev_attr_rx_mgmt_pkt_num_total.attr,
&dev_attr_rx_mgmt_pkt_num_fail.attr,
&dev_attr_rx_ack_pkt_num_total.attr,
&dev_attr_rx_ack_pkt_num_fail.attr,
&dev_attr_rx_data_pkt_mcs_realtime.attr,
&dev_attr_rx_data_pkt_fail_mcs_realtime.attr,
&dev_attr_rx_mgmt_pkt_mcs_realtime.attr,
&dev_attr_rx_mgmt_pkt_fail_mcs_realtime.attr,
&dev_attr_rx_ack_pkt_mcs_realtime.attr,
&dev_attr_restrict_freq_mhz.attr,
&dev_attr_csma_cfg0.attr,
&dev_attr_cw_max_min_cfg.attr,
&dev_attr_dbg_ch0.attr,
&dev_attr_dbg_ch1.attr,
&dev_attr_dbg_ch2.attr,
NULL,
};
static const struct attribute_group stat_attribute_group = {
.attrs = stat_attributes,
};
================================================
FILE: driver/tx_intf/Makefile
================================================
# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += tx_intf.o
all:
make -C $(KDIR) M=$(PWD) modules
# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
================================================
FILE: driver/tx_intf/tx_intf.c
================================================
/*
* axi lite register access driver
* Author: Xianjun Jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline u32 TX_INTF_REG_MULTI_RST_read(void){
return reg_read(TX_INTF_REG_MULTI_RST_ADDR);
}
static inline u32 TX_INTF_REG_ARBITRARY_IQ_read(void){
return reg_read(TX_INTF_REG_ARBITRARY_IQ_ADDR);
}
static inline u32 TX_INTF_REG_WIFI_TX_MODE_read(void){
return reg_read(TX_INTF_REG_WIFI_TX_MODE_ADDR);
}
static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){
return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR);
}
static inline u32 TX_INTF_REG_CSI_FUZZER_read(void){
return reg_read(TX_INTF_REG_CSI_FUZZER_ADDR);
}
static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){
return reg_read(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR);
}
static inline u32 TX_INTF_REG_ARBITRARY_IQ_CTL_read(void){
return reg_read(TX_INTF_REG_ARBITRARY_IQ_CTL_ADDR);
}
static inline u32 TX_INTF_REG_TX_CONFIG_read(void){
return reg_read(TX_INTF_REG_TX_CONFIG_ADDR);
}
static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){
return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR);
}
static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){
return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR);
}
static inline u32 TX_INTF_REG_S_AXIS_FIFO_TH_read(void){
return reg_read(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR);
}
static inline u32 TX_INTF_REG_TX_HOLD_THRESHOLD_read(void){
return reg_read(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR);
}
static inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){
return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR);
}
static inline u32 TX_INTF_REG_AMPDU_ACTION_CONFIG_read(void){
return reg_read(TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR);
}
static inline u32 TX_INTF_REG_BB_GAIN_read(void){
return reg_read(TX_INTF_REG_BB_GAIN_ADDR);
}
static inline u32 TX_INTF_REG_ANT_SEL_read(void){
return reg_read(TX_INTF_REG_ANT_SEL_ADDR);
}
static inline u32 TX_INTF_REG_PHY_HDR_CONFIG_read(void){
return reg_read(TX_INTF_REG_PHY_HDR_CONFIG_ADDR);
}
static inline u32 TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read(void){
return reg_read(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR);
}
static inline u32 TX_INTF_REG_PKT_INFO1_read(void){
return reg_read(TX_INTF_REG_PKT_INFO1_ADDR);
}
static inline u32 TX_INTF_REG_PKT_INFO2_read(void){
return reg_read(TX_INTF_REG_PKT_INFO2_ADDR);
}
static inline u32 TX_INTF_REG_PKT_INFO3_read(void){
return reg_read(TX_INTF_REG_PKT_INFO3_ADDR);
}
static inline u32 TX_INTF_REG_PKT_INFO4_read(void){
return reg_read(TX_INTF_REG_PKT_INFO4_ADDR);
}
static inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){
return reg_read(TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR);
}
//--------------------------------------------------------
static inline void TX_INTF_REG_MULTI_RST_write(u32 value){
reg_write(TX_INTF_REG_MULTI_RST_ADDR, value);
}
static inline void TX_INTF_REG_ARBITRARY_IQ_write(u32 value){
reg_write(TX_INTF_REG_ARBITRARY_IQ_ADDR, value);
}
static inline void TX_INTF_REG_WIFI_TX_MODE_write(u32 value){
reg_write(TX_INTF_REG_WIFI_TX_MODE_ADDR, value);
}
static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){
reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value);
}
static inline void TX_INTF_REG_CSI_FUZZER_write(u32 value){
reg_write(TX_INTF_REG_CSI_FUZZER_ADDR, value);
}
static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){
reg_write(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR, value);
}
static inline void TX_INTF_REG_ARBITRARY_IQ_CTL_write(u32 value){
reg_write(TX_INTF_REG_ARBITRARY_IQ_CTL_ADDR, value);
}
static inline void TX_INTF_REG_TX_CONFIG_write(u32 value){
reg_write(TX_INTF_REG_TX_CONFIG_ADDR, value);
}
static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){
reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value);
}
static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){
reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value);
}
static inline void TX_INTF_REG_S_AXIS_FIFO_TH_write(u32 value){
reg_write(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR, value);
}
static inline void TX_INTF_REG_TX_HOLD_THRESHOLD_write(u32 value){
reg_write(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR, value);
}
static inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){
reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value);
}
static inline void TX_INTF_REG_AMPDU_ACTION_CONFIG_write(u32 value){
reg_write(TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR, value);
}
static inline void TX_INTF_REG_BB_GAIN_write(u32 value){
reg_write(TX_INTF_REG_BB_GAIN_ADDR, value);
}
static inline void TX_INTF_REG_ANT_SEL_write(u32 value){
reg_write(TX_INTF_REG_ANT_SEL_ADDR, value);
}
static inline void TX_INTF_REG_PHY_HDR_CONFIG_write(u32 value){
reg_write(TX_INTF_REG_PHY_HDR_CONFIG_ADDR, value);
}
static inline void TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write(u32 value){
reg_write(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR, value);
}
static inline void TX_INTF_REG_PKT_INFO1_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO1_ADDR,value);
}
static inline void TX_INTF_REG_PKT_INFO2_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO2_ADDR,value);
}
static inline void TX_INTF_REG_PKT_INFO3_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO3_ADDR,value);
}
static inline void TX_INTF_REG_PKT_INFO4_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO4_ADDR,value);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,tx_intf", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct tx_intf_driver_api tx_intf_driver_api_inst;
struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst;
EXPORT_SYMBOL(tx_intf_api);
static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){
int err=0, i;
u32 mixer_cfg=0, ant_sel=0;
printk("%s hw_init mode %d\n", tx_intf_compatible_str, mode);
//rst
for (i=0;i<8;i++)
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
for (i=0;i<32;i++)
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF);
for (i=0;i<8;i++)
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
if(fpga_type == LARGE_FPGA) // LARGE FPGA: MAX_NUM_DMA_SYMBOL = 8192
// tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-(210*5)); // threshold is for room to hold the last 4 packets from 4 queue before stop
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(8192-(210*2));
else if(fpga_type == SMALL_FPGA) // SMALL FPGA: MAX_NUM_DMA_SYMBOL = 4096
// tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-(210*5)); // threshold is for room to hold the last 4 packets from 4 queue before stop
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-(210*2));
switch(mode)
{
case TX_INTF_AXIS_LOOP_BACK:
printk("%s hw_init mode TX_INTF_AXIS_LOOP_BACK\n", tx_intf_compatible_str);
break;
case TX_INTF_BW_20MHZ_AT_0MHZ_ANT0:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str);
mixer_cfg = 0x2001F400;
ant_sel=1;
break;
case TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH\n", tx_intf_compatible_str);
mixer_cfg = 0x2001F400;
ant_sel=0x11;
break;
case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0\n", tx_intf_compatible_str);
mixer_cfg = 0x2001F602;
ant_sel=1;
break;
case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0\n", tx_intf_compatible_str);
mixer_cfg = 0x200202F6;
ant_sel=1;
break;
case TX_INTF_BW_20MHZ_AT_0MHZ_ANT1:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT1\n", tx_intf_compatible_str);
mixer_cfg = 0x2001F400;
ant_sel=2;
break;
case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1\n", tx_intf_compatible_str);
mixer_cfg = 0x2001F602;
ant_sel=2;
break;
case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1\n", tx_intf_compatible_str);
mixer_cfg = 0x200202F6;
ant_sel=2;
break;
case TX_INTF_BYPASS:
printk("%s hw_init mode TX_INTF_BYPASS\n", tx_intf_compatible_str);
mixer_cfg = 0x200202F6;
ant_sel=2;
break;
default:
printk("%s hw_init mode %d is wrong!\n", tx_intf_compatible_str, mode);
err=1;
}
if (mode!=TX_INTF_AXIS_LOOP_BACK) {
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0);
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(16*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed
// Remove TX_INTF_REG_TX_CONFIG_write to avoid hw_init call in openwifi_start causing inconsistency
// tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config);
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0);
tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420);
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4); //.src_sel(slv_reg14[2:0]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-tx_try_complete from xpu
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30004); //disable interrupt
// tx_intf_api->TX_INTF_REG_BB_GAIN_write(100); // value for old design with DUC (FIR + MIXER) -- obsolete due to DUC removal
// New test on new design (unified RF BB clock; No DUC)
// 5220MHz bb_gain power EVM
// 400 -6dBm -34/35
// 350 -7.2dBm -34/35/36
// 300 -8.5dBm -35/36/37 EVM
// 2437MHz bb_gain power EVM
// 400 -3.2dBm -36/37
// 350 -4.4dBm -37/38/39
// 300 -5.7dBm -39/40
// less less -40/41/42!
// According to above and more detailed test:
// Need to be 290. Otherwise some ofdm symbol's EVM jump high, when there are lots of ofdm symbols in one WiFi packet
// 2022-03-04 detailed test result:
// bb_gain 290 work for 11a/g all mcs
// bb_gain 290 work for 11n mcs 1~7 (aggr and non aggr)
// bb_gain 290 destroy 11n mcs 0 long (MTU 1500) tx pkt due to high PAPR (Peak to Average Power Ratio)!
// bb_gain 250 work for 11n mcs 0
// So, a conservative bb_gain 250 should be used
tx_intf_api->TX_INTF_REG_BB_GAIN_write(250);
// Remove TX_INTF_REG_ANT_SEL_write to avoid hw_init call in openwifi_start causing inconsistency
// tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel);
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4));
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434);
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
}
// if (mode == TX_INTF_BYPASS) {
// tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] -- bit 8 not used anymore. only bit0/1 are still reserved.
// }
printk("%s hw_init err %d\n", tx_intf_compatible_str, err);
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", tx_intf_compatible_str);
err = 0;
}
}
if (err)
return err;
tx_intf_api->hw_init=hw_init;
tx_intf_api->reg_read=reg_read;
tx_intf_api->reg_write=reg_write;
tx_intf_api->TX_INTF_REG_MULTI_RST_read=TX_INTF_REG_MULTI_RST_read;
tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_read=TX_INTF_REG_ARBITRARY_IQ_read;
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read;
tx_intf_api->TX_INTF_REG_CSI_FUZZER_read=TX_INTF_REG_CSI_FUZZER_read;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read;
tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_read=TX_INTF_REG_ARBITRARY_IQ_CTL_read;
tx_intf_api->TX_INTF_REG_TX_CONFIG_read=TX_INTF_REG_TX_CONFIG_read;
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read;
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read;
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_read=TX_INTF_REG_S_AXIS_FIFO_TH_read;
tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_read=TX_INTF_REG_TX_HOLD_THRESHOLD_read;
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read;
tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_read=TX_INTF_REG_AMPDU_ACTION_CONFIG_read;
tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read;
tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read;
tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_read=TX_INTF_REG_PHY_HDR_CONFIG_read;
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read;
tx_intf_api->TX_INTF_REG_PKT_INFO1_read=TX_INTF_REG_PKT_INFO1_read;
tx_intf_api->TX_INTF_REG_PKT_INFO2_read=TX_INTF_REG_PKT_INFO2_read;
tx_intf_api->TX_INTF_REG_PKT_INFO3_read=TX_INTF_REG_PKT_INFO3_read;
tx_intf_api->TX_INTF_REG_PKT_INFO4_read=TX_INTF_REG_PKT_INFO4_read;
tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read;
tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write;
tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_write=TX_INTF_REG_ARBITRARY_IQ_write;
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write;
tx_intf_api->TX_INTF_REG_CSI_FUZZER_write=TX_INTF_REG_CSI_FUZZER_write;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write;
tx_intf_api->TX_INTF_REG_ARBITRARY_IQ_CTL_write=TX_INTF_REG_ARBITRARY_IQ_CTL_write;
tx_intf_api->TX_INTF_REG_TX_CONFIG_write=TX_INTF_REG_TX_CONFIG_write;
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write;
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write;
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write=TX_INTF_REG_S_AXIS_FIFO_TH_write;
tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write=TX_INTF_REG_TX_HOLD_THRESHOLD_write;
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write;
tx_intf_api->TX_INTF_REG_AMPDU_ACTION_CONFIG_write=TX_INTF_REG_AMPDU_ACTION_CONFIG_write;
tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write;
tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write;
tx_intf_api->TX_INTF_REG_PHY_HDR_CONFIG_write=TX_INTF_REG_PHY_HDR_CONFIG_write;
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write;
tx_intf_api->TX_INTF_REG_PKT_INFO1_write=TX_INTF_REG_PKT_INFO1_write;
tx_intf_api->TX_INTF_REG_PKT_INFO2_write=TX_INTF_REG_PKT_INFO2_write;
tx_intf_api->TX_INTF_REG_PKT_INFO3_write=TX_INTF_REG_PKT_INFO3_write;
tx_intf_api->TX_INTF_REG_PKT_INFO4_write=TX_INTF_REG_PKT_INFO4_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr);
printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) );
printk("%s dev_probe tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api);
printk("%s dev_probe succeed!\n", tx_intf_compatible_str);
//err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8, SMALL_FPGA);
//err = hw_init(TX_INTF_BYPASS, 8, 8, SMALL_FPGA);
err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8, SMALL_FPGA); // make sure dac is connected to original ad9361 dma
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr);
printk("%s dev_remove tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) );
printk("%s dev_remove tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api);
printk("%s dev_remove succeed!\n", tx_intf_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,tx_intf",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,tx_intf");
MODULE_LICENSE("GPL v2");
================================================
FILE: driver/xilinx_dma/README.md
================================================
We don't maintain our own (modified) xilinx dma driver anymore! The original xilinx dma driver in the Linux kernel tree can be used.
===============Following are obsolete content=================
Currently used driver xilinx_dma-orig.c is based on 552d3f11e374ca0d435aa93a571507819eabdda2 of https://github.com/Xilinx/linux-xlnx )
instruction to generate our customized xilinx dma driver:
./make_xilinx_dma.sh
instruction to generate our customized xilinx dma test program:
./make_xilinx_dma_test.sh
test dma driver on board: login to zc706, then:
rm axidmatest.ko
wget ftp://192.168.10.1/driver/xilinx_dma/axidmatest.ko
rm ddc.ko
wget ftp://192.168.10.1/driver/ddc/ddc.ko
rm xilinx_dma.ko
wget ftp://192.168.10.1/driver/xilinx_dma/xilinx_dma.ko
rmmod axidmatest
rmmod ddc
rmmod xilinx_dma
insmod xilinx_dma.ko
insmod ddc.ko
insmod axidmatest.ko
dmesg -c
dmesg will show test result printed by "insmod axidmatest.ko". Like this:
root@analog:~# dmesg -c
xilinx_dmatest: dropped channel dma5chan0
xilinx_dmatest: dropped channel dma5chan1
sdr,ddc dev_remove base_addr 0xf14e0000
sdr,ddc dev_remove ddc_driver_api_inst 0xbf032284
sdr,ddc dev_remove ddc_api 0xbf032284
sdr,ddc dev_remove succeed!
xilinx-vdma 43000000.axivdma: Xilinx AXI VDMA Engine Driver Probed!!
xilinx-vdma 80400000.dma: Xilinx AXI DMA Engine Driver Probed!!
xilinx-vdma 80410000.dma: Xilinx AXI DMA Engine Driver Probed!!
sdr,ddc dev_probe match!
sdr,ddc dev_probe io start 0x83c20000 end 0x83c2ffff name /fpga-axi@0/rx_intf@83c20000 flags 0x00000200 desc 0x00000000
sdr,ddc dev_probe base_addr 0xf18e0000
sdr,ddc dev_probe ddc_driver_api_inst 0xbf0e1284
sdr,ddc dev_probe ddc_api 0xbf0e1284
sdr,ddc dev_probe reset tsf timer
sdr,ddc dev_probe tsf timer runtime read 1 33007 100015us
sdr,ddc dev_probe succeed!
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
dmatest: Started 1 threads using dma5chan0 dma5chan1
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 99 status 0 len 6448 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #0: No errors with
src_off=0x448 dst_off=0x568 len=0x1930
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 100 status 0 len 3248 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #1: No errors with
src_off=0x458 dst_off=0xf08 len=0xcb0
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 100 status 0 len 8112 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #2: No errors with
src_off=0x10 dst_off=0x20 len=0x1fb0
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 100 status 0 len 840 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #3: No errors with
src_off=0x1890 dst_off=0x1268 len=0x348
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 100 status 0 len 7816 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #4: No errors with
src_off=0x80 dst_off=0x168 len=0x1e88
dma5chan0-dma5c: terminating after 5 tests, 0 failures (status 0)
================================================
FILE: driver/xilinx_dma/make_xilinx_dma.sh
================================================
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -ne 2 ]; then
echo "You must enter exactly 2 arguments: \$XILINX_DIR \$ARCH(32 or 64)"
exit 1
fi
WORKDIR=$PWD
OPENWIFI_DIR=$(pwd)/../../
XILINX_DIR=$1
ARCH_OPTION=$2
set -x
if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
echo "\$OPENWIFI_DIR is found!"
else
echo "\$OPENWIFI_DIR is not correct. Please check!"
exit 1
fi
if [ -d "$XILINX_DIR/SDK" ]; then
echo "\$XILINX_DIR is found!"
else
echo "\$XILINX_DIR is not correct. Please check!"
exit 1
fi
if [ "$ARCH_OPTION" != "32" ] && [ "$ARCH_OPTION" != "64" ]; then
echo "\$ARCH_OPTION is not correct. Should be 32 or 64. Please check!"
exit 1
else
echo "\$ARCH_OPTION is valid!"
fi
source $XILINX_DIR/SDK/2018.3/settings64.sh
if [ "$ARCH_OPTION" == "64" ]; then
KDIR=$OPENWIFI_DIR/adi-linux-64/
export ARCH=arm64
export CROSS_COMPILE=aarch64-linux-gnu-
else
KDIR=$OPENWIFI_DIR/adi-linux/
export ARCH=arm
export CROSS_COMPILE=arm-linux-gnueabihf-
fi
SUBMODULE=xilinx_dma
cp $KDIR/drivers/dma/xilinx/xilinx_dma.c $KDIR/drivers/dma/xilinx/xilinx_dma.c.bak
cp xilinx_dma.c $KDIR/drivers/dma/xilinx -rf
cd $KDIR
make $KDIR/drivers/dma/xilinx/$SUBMODULE.ko
cp $KDIR/drivers/dma/xilinx/$SUBMODULE.ko $WORKDIR -rf
# cp $KDIR/drivers/dma/xilinx/xilinx_dma.c.bak $KDIR/drivers/dma/xilinx/xilinx_dma.c
cd $WORKDIR
ls $SUBMODULE.ko
================================================
FILE: driver/xilinx_dma/xilinx_dma.c
================================================
/*
* DMA driver for Xilinx Video DMA Engine
* SPDX-FileCopyrightText: Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved
* Based on the Freescale DMA driver
* Modified by Xianjun Jiao
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Description:
* The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
* core that provides high-bandwidth direct memory access between memory
* and AXI4-Stream type video target peripherals. The core provides efficient
* two dimensional DMA operations with independent asynchronous read (S2MM)
* and write (MM2S) channel operation. It can be configured to have either
* one channel or two channels. If configured as two channels, one is to
* transmit to the video device (MM2S) and another is to receive from the
* video device (S2MM). Initialization, status, interrupt and management
* registers are accessed through an AXI4-Lite slave interface.
*
* The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
* provides high-bandwidth one dimensional direct memory access between memory
* and AXI4-Stream target peripherals. It supports one receive and one
* transmit channel, both of them optional at synthesis time.
*
* The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
* Access (DMA) between a memory-mapped source address and a memory-mapped
* destination address.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "../dmaengine.h"
/* Register/Descriptor Offsets */
#define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000
#define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030
#define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050
#define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0
/* Control Registers */
#define XILINX_DMA_REG_DMACR 0x0000
#define XILINX_DMA_DMACR_DELAY_MAX 0xff
#define XILINX_DMA_DMACR_DELAY_SHIFT 24
#define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff
#define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16
#define XILINX_DMA_DMACR_ERR_IRQ BIT(14)
#define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13)
#define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12)
#define XILINX_DMA_DMACR_MASTER_SHIFT 8
#define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
#define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4)
#define XILINX_DMA_DMACR_GENLOCK_EN BIT(3)
#define XILINX_DMA_DMACR_RESET BIT(2)
#define XILINX_DMA_DMACR_CIRC_EN BIT(1)
#define XILINX_DMA_DMACR_RUNSTOP BIT(0)
#define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
#define XILINX_DMA_REG_DMASR 0x0004
#define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
#define XILINX_DMA_DMASR_ERR_IRQ BIT(14)
#define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13)
#define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12)
#define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11)
#define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10)
#define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9)
#define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8)
#define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7)
#define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6)
#define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5)
#define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4)
#define XILINX_DMA_DMASR_IDLE BIT(1)
#define XILINX_DMA_DMASR_HALTED BIT(0)
#define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)
#define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)
#define XILINX_DMA_REG_CURDESC 0x0008
#define XILINX_DMA_REG_TAILDESC 0x0010
#define XILINX_DMA_REG_REG_INDEX 0x0014
#define XILINX_DMA_REG_FRMSTORE 0x0018
#define XILINX_DMA_REG_THRESHOLD 0x001c
#define XILINX_DMA_REG_FRMPTR_STS 0x0024
#define XILINX_DMA_REG_PARK_PTR 0x0028
#define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8
#define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8)
#define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0
#define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0)
#define XILINX_DMA_REG_VDMA_VERSION 0x002c
/* Register Direct Mode Registers */
#define XILINX_DMA_REG_VSIZE 0x0000
#define XILINX_DMA_REG_HSIZE 0x0004
#define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008
#define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24
#define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0
#define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n))
#define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n))
#define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec
#define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0)
/* HW specific definitions */
#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x20
#define XILINX_DMA_DMAXR_ALL_IRQ_MASK \
(XILINX_DMA_DMASR_FRM_CNT_IRQ | \
XILINX_DMA_DMASR_DLY_CNT_IRQ | \
XILINX_DMA_DMASR_ERR_IRQ)
#define XILINX_DMA_DMASR_ALL_ERR_MASK \
(XILINX_DMA_DMASR_EOL_LATE_ERR | \
XILINX_DMA_DMASR_SOF_LATE_ERR | \
XILINX_DMA_DMASR_SG_DEC_ERR | \
XILINX_DMA_DMASR_SG_SLV_ERR | \
XILINX_DMA_DMASR_EOF_EARLY_ERR | \
XILINX_DMA_DMASR_SOF_EARLY_ERR | \
XILINX_DMA_DMASR_DMA_DEC_ERR | \
XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
XILINX_DMA_DMASR_DMA_INT_ERR)
/*
* Recoverable errors are DMA Internal error, SOF Early, EOF Early
* and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
* is enabled in the h/w system.
*/
#define XILINX_DMA_DMASR_ERR_RECOVER_MASK \
(XILINX_DMA_DMASR_SOF_LATE_ERR | \
XILINX_DMA_DMASR_EOF_EARLY_ERR | \
XILINX_DMA_DMASR_SOF_EARLY_ERR | \
XILINX_DMA_DMASR_DMA_INT_ERR)
/* Axi VDMA Flush on Fsync bits */
#define XILINX_DMA_FLUSH_S2MM 3
#define XILINX_DMA_FLUSH_MM2S 2
#define XILINX_DMA_FLUSH_BOTH 1
/* Delay loop counter to prevent hardware failure */
#define XILINX_DMA_LOOP_COUNT 1000000
/* AXI DMA Specific Registers/Offsets */
#define XILINX_DMA_REG_SRCDSTADDR 0x18
#define XILINX_DMA_REG_BTT 0x28
/* AXI DMA Specific Masks/Bit fields */
#define XILINX_DMA_MAX_TRANS_LEN_MIN 8
#define XILINX_DMA_MAX_TRANS_LEN_MAX 23
#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26
#define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16)
#define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
#define XILINX_DMA_CR_COALESCE_SHIFT 16
#define XILINX_DMA_BD_SOP BIT(27)
#define XILINX_DMA_BD_EOP BIT(26)
#define XILINX_DMA_COALESCE_MAX 255
#define XILINX_DMA_NUM_DESCS 255
#define XILINX_DMA_NUM_APP_WORDS 5
/* Multi-Channel DMA Descriptor offsets*/
#define XILINX_DMA_MCRX_CDESC(x) (0x40 + (x-1) * 0x20)
#define XILINX_DMA_MCRX_TDESC(x) (0x48 + (x-1) * 0x20)
/* Multi-Channel DMA Masks/Shifts */
#define XILINX_DMA_BD_HSIZE_MASK GENMASK(15, 0)
#define XILINX_DMA_BD_STRIDE_MASK GENMASK(15, 0)
#define XILINX_DMA_BD_VSIZE_MASK GENMASK(31, 19)
#define XILINX_DMA_BD_TDEST_MASK GENMASK(4, 0)
#define XILINX_DMA_BD_STRIDE_SHIFT 0
#define XILINX_DMA_BD_VSIZE_SHIFT 19
/* AXI CDMA Specific Registers/Offsets */
#define XILINX_CDMA_REG_SRCADDR 0x18
#define XILINX_CDMA_REG_DSTADDR 0x20
/* AXI CDMA Specific Masks */
#define XILINX_CDMA_CR_SGMODE BIT(3)
/**
* struct xilinx_vdma_desc_hw - Hardware Descriptor
* @next_desc: Next Descriptor Pointer @0x00
* @pad1: Reserved @0x04
* @buf_addr: Buffer address @0x08
* @buf_addr_msb: MSB of Buffer address @0x0C
* @vsize: Vertical Size @0x10
* @hsize: Horizontal Size @0x14
* @stride: Number of bytes between the first
* pixels of each horizontal line @0x18
*/
struct xilinx_vdma_desc_hw {
u32 next_desc;
u32 pad1;
u32 buf_addr;
u32 buf_addr_msb;
u32 vsize;
u32 hsize;
u32 stride;
} __aligned(64);
/**
* struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
* @next_desc: Next Descriptor Pointer @0x00
* @next_desc_msb: MSB of Next Descriptor Pointer @0x04
* @buf_addr: Buffer address @0x08
* @buf_addr_msb: MSB of Buffer address @0x0C
* @mcdma_control: Control field for mcdma @0x10
* @vsize_stride: Vsize and Stride field for mcdma @0x14
* @control: Control field @0x18
* @status: Status field @0x1C
* @app: APP Fields @0x20 - 0x30
*/
struct xilinx_axidma_desc_hw {
u32 next_desc;
u32 next_desc_msb;
u32 buf_addr;
u32 buf_addr_msb;
u32 mcdma_control;
u32 vsize_stride;
u32 control;
u32 status;
u32 app[XILINX_DMA_NUM_APP_WORDS];
} __aligned(64);
/**
* struct xilinx_cdma_desc_hw - Hardware Descriptor
* @next_desc: Next Descriptor Pointer @0x00
* @next_desc_msb: Next Descriptor Pointer MSB @0x04
* @src_addr: Source address @0x08
* @src_addr_msb: Source address MSB @0x0C
* @dest_addr: Destination address @0x10
* @dest_addr_msb: Destination address MSB @0x14
* @control: Control field @0x18
* @status: Status field @0x1C
*/
struct xilinx_cdma_desc_hw {
u32 next_desc;
u32 next_desc_msb;
u32 src_addr;
u32 src_addr_msb;
u32 dest_addr;
u32 dest_addr_msb;
u32 control;
u32 status;
} __aligned(64);
/**
* struct xilinx_vdma_tx_segment - Descriptor segment
* @hw: Hardware descriptor
* @node: Node in the descriptor segments list
* @phys: Physical address of segment
*/
struct xilinx_vdma_tx_segment {
struct xilinx_vdma_desc_hw hw;
struct list_head node;
dma_addr_t phys;
} __aligned(64);
/**
* struct xilinx_axidma_tx_segment - Descriptor segment
* @hw: Hardware descriptor
* @node: Node in the descriptor segments list
* @phys: Physical address of segment
*/
struct xilinx_axidma_tx_segment {
struct xilinx_axidma_desc_hw hw;
struct list_head node;
dma_addr_t phys;
} __aligned(64);
/**
* struct xilinx_cdma_tx_segment - Descriptor segment
* @hw: Hardware descriptor
* @node: Node in the descriptor segments list
* @phys: Physical address of segment
*/
struct xilinx_cdma_tx_segment {
struct xilinx_cdma_desc_hw hw;
struct list_head node;
dma_addr_t phys;
} __aligned(64);
/**
* struct xilinx_dma_tx_descriptor - Per Transaction structure
* @async_tx: Async transaction descriptor
* @segments: TX segments list
* @node: Node in the channel descriptors list
* @cyclic: Check for cyclic transfers.
*/
struct xilinx_dma_tx_descriptor {
struct dma_async_tx_descriptor async_tx;
struct list_head segments;
struct list_head node;
bool cyclic;
};
/**
* struct xilinx_dma_chan - Driver specific DMA channel structure
* @xdev: Driver specific device structure
* @ctrl_offset: Control registers offset
* @desc_offset: TX descriptor registers offset
* @lock: Descriptor operation lock
* @pending_list: Descriptors waiting
* @active_list: Descriptors ready to submit
* @done_list: Complete descriptors
* @free_seg_list: Free descriptors
* @common: DMA common channel
* @desc_pool: Descriptors pool
* @dev: The dma device
* @irq: Channel IRQ
* @id: Channel ID
* @direction: Transfer direction
* @num_frms: Number of frames
* @has_sg: Support scatter transfers
* @cyclic: Check for cyclic transfers.
* @genlock: Support genlock mode
* @err: Channel has errors
* @idle: Check for channel idle
* @tasklet: Cleanup work after irq
* @config: Device configuration info
* @flush_on_fsync: Flush on Frame sync
* @desc_pendingcount: Descriptor pending count
* @ext_addr: Indicates 64 bit addressing is supported by dma channel
* @desc_submitcount: Descriptor h/w submitted count
* @residue: Residue for AXI DMA
* @seg_v: Statically allocated segments base
* @seg_p: Physical allocated segments base
* @cyclic_seg_v: Statically allocated segment base for cyclic transfers
* @cyclic_seg_p: Physical allocated segments base for cyclic dma
* @start_transfer: Differentiate b/w DMA IP's transfer
* @stop_transfer: Differentiate b/w DMA IP's quiesce
* @tdest: TDEST value for mcdma
* @has_vflip: S2MM vertical flip
*/
struct xilinx_dma_chan {
struct xilinx_dma_device *xdev;
u32 ctrl_offset;
u32 desc_offset;
spinlock_t lock;
struct list_head pending_list;
struct list_head active_list;
struct list_head done_list;
struct list_head free_seg_list;
struct dma_chan common;
struct dma_pool *desc_pool;
struct device *dev;
int irq;
int id;
enum dma_transfer_direction direction;
int num_frms;
bool has_sg;
bool cyclic;
bool genlock;
bool err;
bool idle;
struct tasklet_struct tasklet;
struct xilinx_vdma_config config;
bool flush_on_fsync;
u32 desc_pendingcount;
bool ext_addr;
u32 desc_submitcount;
u32 residue;
struct xilinx_axidma_tx_segment *seg_v;
dma_addr_t seg_p;
struct xilinx_axidma_tx_segment *cyclic_seg_v;
dma_addr_t cyclic_seg_p;
void (*start_transfer)(struct xilinx_dma_chan *chan);
int (*stop_transfer)(struct xilinx_dma_chan *chan);
u16 tdest;
bool has_vflip;
u32 buf_idx; // each irq this value increase 1. in cyclic mode, we use residue return this idx via device_tx_status/xilinx_dma_tx_status
};
/**
* enum xdma_ip_type - DMA IP type.
*
* @XDMA_TYPE_AXIDMA: Axi dma ip.
* @XDMA_TYPE_CDMA: Axi cdma ip.
* @XDMA_TYPE_VDMA: Axi vdma ip.
*
*/
enum xdma_ip_type {
XDMA_TYPE_AXIDMA = 0,
XDMA_TYPE_CDMA,
XDMA_TYPE_VDMA,
};
struct xilinx_dma_config {
enum xdma_ip_type dmatype;
int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
struct clk **tx_clk, struct clk **txs_clk,
struct clk **rx_clk, struct clk **rxs_clk);
};
/**
* struct xilinx_dma_device - DMA device structure
* @regs: I/O mapped base address
* @dev: Device Structure
* @common: DMA device structure
* @chan: Driver specific DMA channel
* @has_sg: Specifies whether Scatter-Gather is present or not
* @mcdma: Specifies whether Multi-Channel is present or not
* @flush_on_fsync: Flush on frame sync
* @ext_addr: Indicates 64 bit addressing is supported by dma device
* @pdev: Platform device structure pointer
* @dma_config: DMA config structure
* @axi_clk: DMA Axi4-lite interface clock
* @tx_clk: DMA mm2s clock
* @txs_clk: DMA mm2s stream clock
* @rx_clk: DMA s2mm clock
* @rxs_clk: DMA s2mm stream clock
* @nr_channels: Number of channels DMA device supports
* @chan_id: DMA channel identifier
* @max_buffer_len: Max buffer length
*/
struct xilinx_dma_device {
void __iomem *regs;
struct device *dev;
struct dma_device common;
struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE];
bool has_sg;
bool mcdma;
u32 flush_on_fsync;
bool ext_addr;
struct platform_device *pdev;
const struct xilinx_dma_config *dma_config;
struct clk *axi_clk;
struct clk *tx_clk;
struct clk *txs_clk;
struct clk *rx_clk;
struct clk *rxs_clk;
u32 nr_channels;
u32 chan_id;
u32 max_buffer_len;
};
/* Macros */
#define to_xilinx_chan(chan) \
container_of(chan, struct xilinx_dma_chan, common)
#define to_dma_tx_descriptor(tx) \
container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
#define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \
cond, delay_us, timeout_us)
/* IO accessors */
static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
{
return ioread32(chan->xdev->regs + reg);
}
static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
{
iowrite32(value, chan->xdev->regs + reg);
}
static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
u32 value)
{
dma_write(chan, chan->desc_offset + reg, value);
}
static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
{
return dma_read(chan, chan->ctrl_offset + reg);
}
static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
u32 value)
{
dma_write(chan, chan->ctrl_offset + reg, value);
}
static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
u32 clr)
{
dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
}
static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
u32 set)
{
dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
}
/**
* vdma_desc_write_64 - 64-bit descriptor write
* @chan: Driver specific VDMA channel
* @reg: Register to write
* @value_lsb: lower address of the descriptor.
* @value_msb: upper address of the descriptor.
*
* Since vdma driver is trying to write to a register offset which is not a
* multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
* instead of a single 64 bit register write.
*/
static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
u32 value_lsb, u32 value_msb)
{
/* Write the lsb 32 bits*/
writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
/* Write the msb 32 bits */
writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
}
static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
{
lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
}
static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
dma_addr_t addr)
{
if (chan->ext_addr)
dma_writeq(chan, reg, addr);
else
dma_ctrl_write(chan, reg, addr);
}
static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
struct xilinx_axidma_desc_hw *hw,
dma_addr_t buf_addr, size_t sg_used,
size_t period_len)
{
if (chan->ext_addr) {
hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
period_len);
} else {
hw->buf_addr = buf_addr + sg_used + period_len;
}
}
/* -----------------------------------------------------------------------------
* Descriptors and segments alloc and free
*/
/**
* xilinx_vdma_alloc_tx_segment - Allocate transaction segment
* @chan: Driver specific DMA channel
*
* Return: The allocated segment on success and NULL on failure.
*/
static struct xilinx_vdma_tx_segment *
xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
{
struct xilinx_vdma_tx_segment *segment;
dma_addr_t phys;
segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
if (!segment)
return NULL;
segment->phys = phys;
return segment;
}
/**
* xilinx_cdma_alloc_tx_segment - Allocate transaction segment
* @chan: Driver specific DMA channel
*
* Return: The allocated segment on success and NULL on failure.
*/
static struct xilinx_cdma_tx_segment *
xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
{
struct xilinx_cdma_tx_segment *segment;
dma_addr_t phys;
segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
if (!segment)
return NULL;
segment->phys = phys;
return segment;
}
/**
* xilinx_axidma_alloc_tx_segment - Allocate transaction segment
* @chan: Driver specific DMA channel
*
* Return: The allocated segment on success and NULL on failure.
*/
static struct xilinx_axidma_tx_segment *
xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
{
struct xilinx_axidma_tx_segment *segment = NULL;
unsigned long flags;
spin_lock_irqsave(&chan->lock, flags);
if (!list_empty(&chan->free_seg_list)) {
segment = list_first_entry(&chan->free_seg_list,
struct xilinx_axidma_tx_segment,
node);
list_del(&segment->node);
}
spin_unlock_irqrestore(&chan->lock, flags);
return segment;
}
static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
{
u32 next_desc = hw->next_desc;
u32 next_desc_msb = hw->next_desc_msb;
memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
hw->next_desc = next_desc;
hw->next_desc_msb = next_desc_msb;
}
/**
* xilinx_dma_free_tx_segment - Free transaction segment
* @chan: Driver specific DMA channel
* @segment: DMA transaction segment
*/
static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
struct xilinx_axidma_tx_segment *segment)
{
xilinx_dma_clean_hw_desc(&segment->hw);
list_add_tail(&segment->node, &chan->free_seg_list);
}
/**
* xilinx_cdma_free_tx_segment - Free transaction segment
* @chan: Driver specific DMA channel
* @segment: DMA transaction segment
*/
static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
struct xilinx_cdma_tx_segment *segment)
{
dma_pool_free(chan->desc_pool, segment, segment->phys);
}
/**
* xilinx_vdma_free_tx_segment - Free transaction segment
* @chan: Driver specific DMA channel
* @segment: DMA transaction segment
*/
static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
struct xilinx_vdma_tx_segment *segment)
{
dma_pool_free(chan->desc_pool, segment, segment->phys);
}
/**
* xilinx_dma_tx_descriptor - Allocate transaction descriptor
* @chan: Driver specific DMA channel
*
* Return: The allocated descriptor on success and NULL on failure.
*/
static struct xilinx_dma_tx_descriptor *
xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
{
struct xilinx_dma_tx_descriptor *desc;
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
if (!desc)
return NULL;
INIT_LIST_HEAD(&desc->segments);
return desc;
}
/**
* xilinx_dma_free_tx_descriptor - Free transaction descriptor
* @chan: Driver specific DMA channel
* @desc: DMA transaction descriptor
*/
static void
xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
struct xilinx_dma_tx_descriptor *desc)
{
struct xilinx_vdma_tx_segment *segment, *next;
struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
if (!desc)
return;
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
list_for_each_entry_safe(segment, next, &desc->segments, node) {
list_del(&segment->node);
xilinx_vdma_free_tx_segment(chan, segment);
}
} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
list_for_each_entry_safe(cdma_segment, cdma_next,
&desc->segments, node) {
list_del(&cdma_segment->node);
xilinx_cdma_free_tx_segment(chan, cdma_segment);
}
} else {
list_for_each_entry_safe(axidma_segment, axidma_next,
&desc->segments, node) {
list_del(&axidma_segment->node);
xilinx_dma_free_tx_segment(chan, axidma_segment);
}
}
kfree(desc);
}
/* Required functions */
/**
* xilinx_dma_free_desc_list - Free descriptors list
* @chan: Driver specific DMA channel
* @list: List to parse and delete the descriptor
*/
static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
struct list_head *list)
{
struct xilinx_dma_tx_descriptor *desc, *next;
list_for_each_entry_safe(desc, next, list, node) {
list_del(&desc->node);
xilinx_dma_free_tx_descriptor(chan, desc);
}
}
/**
* xilinx_dma_free_descriptors - Free channel descriptors
* @chan: Driver specific DMA channel
*/
static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
{
unsigned long flags;
spin_lock_irqsave(&chan->lock, flags);
xilinx_dma_free_desc_list(chan, &chan->pending_list);
xilinx_dma_free_desc_list(chan, &chan->done_list);
xilinx_dma_free_desc_list(chan, &chan->active_list);
spin_unlock_irqrestore(&chan->lock, flags);
}
/**
* xilinx_dma_free_chan_resources - Free channel resources
* @dchan: DMA channel
*/
static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
unsigned long flags;
dev_dbg(chan->dev, "Free all channel resources.\n");
xilinx_dma_free_descriptors(chan);
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
spin_lock_irqsave(&chan->lock, flags);
INIT_LIST_HEAD(&chan->free_seg_list);
spin_unlock_irqrestore(&chan->lock, flags);
/* Free memory that is allocated for BD */
dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
XILINX_DMA_NUM_DESCS, chan->seg_v,
chan->seg_p);
/* Free Memory that is allocated for cyclic DMA Mode */
dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
chan->cyclic_seg_v, chan->cyclic_seg_p);
}
if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) {
dma_pool_destroy(chan->desc_pool);
chan->desc_pool = NULL;
}
}
/**
* xilinx_dma_chan_handle_cyclic - Cyclic dma callback
* @chan: Driver specific dma channel
* @desc: dma transaction descriptor
* @flags: flags for spin lock
*/
static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
struct xilinx_dma_tx_descriptor *desc,
unsigned long *flags)
{
dma_async_tx_callback callback;
void *callback_param;
callback = desc->async_tx.callback;
callback_param = desc->async_tx.callback_param;
if (callback) {
spin_unlock_irqrestore(&chan->lock, *flags);
callback(callback_param);
spin_lock_irqsave(&chan->lock, *flags);
}
}
/**
* xilinx_dma_chan_desc_cleanup - Clean channel descriptors
* @chan: Driver specific DMA channel
*/
static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
{
struct xilinx_dma_tx_descriptor *desc, *next;
unsigned long flags;
spin_lock_irqsave(&chan->lock, flags);
list_for_each_entry_safe(desc, next, &chan->done_list, node) {
struct dmaengine_desc_callback cb;
if (desc->cyclic) {
xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
break;
}
/* Remove from the list of running transactions */
list_del(&desc->node);
/* Run the link descriptor callback function */
dmaengine_desc_get_callback(&desc->async_tx, &cb);
if (dmaengine_desc_callback_valid(&cb)) {
spin_unlock_irqrestore(&chan->lock, flags);
dmaengine_desc_callback_invoke(&cb, NULL);
spin_lock_irqsave(&chan->lock, flags);
}
/* Run any dependencies, then free the descriptor */
dma_run_dependencies(&desc->async_tx);
xilinx_dma_free_tx_descriptor(chan, desc);
}
spin_unlock_irqrestore(&chan->lock, flags);
}
/**
* xilinx_dma_do_tasklet - Schedule completion tasklet
* @data: Pointer to the Xilinx DMA channel structure
*/
static void xilinx_dma_do_tasklet(unsigned long data)
{
struct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data;
xilinx_dma_chan_desc_cleanup(chan);
}
/**
* xilinx_dma_alloc_chan_resources - Allocate channel resources
* @dchan: DMA channel
*
* Return: '0' on success and failure value on error
*/
static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
int i;
/* Has this channel already been allocated? */
if (chan->desc_pool)
return 0;
/*
* We need the descriptor to be aligned to 64bytes
* for meeting Xilinx VDMA specification requirement.
*/
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
/* Allocate the buffer descriptors. */
chan->seg_v = dma_zalloc_coherent(chan->dev,
sizeof(*chan->seg_v) *
XILINX_DMA_NUM_DESCS,
&chan->seg_p, GFP_KERNEL);
if (!chan->seg_v) {
dev_err(chan->dev,
"unable to allocate channel %d descriptors\n",
chan->id);
return -ENOMEM;
}
/*
* For cyclic DMA mode we need to program the tail Descriptor
* register with a value which is not a part of the BD chain
* so allocating a desc segment during channel allocation for
* programming tail descriptor.
*/
chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
sizeof(*chan->cyclic_seg_v),
&chan->cyclic_seg_p, GFP_KERNEL);
if (!chan->cyclic_seg_v) {
dev_err(chan->dev,
"unable to allocate desc segment for cyclic DMA\n");
dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
XILINX_DMA_NUM_DESCS, chan->seg_v,
chan->seg_p);
return -ENOMEM;
}
chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
chan->seg_v[i].hw.next_desc =
lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
((i + 1) % XILINX_DMA_NUM_DESCS));
chan->seg_v[i].hw.next_desc_msb =
upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
((i + 1) % XILINX_DMA_NUM_DESCS));
chan->seg_v[i].phys = chan->seg_p +
sizeof(*chan->seg_v) * i;
list_add_tail(&chan->seg_v[i].node,
&chan->free_seg_list);
}
} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
chan->dev,
sizeof(struct xilinx_cdma_tx_segment),
__alignof__(struct xilinx_cdma_tx_segment),
0);
} else {
chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
chan->dev,
sizeof(struct xilinx_vdma_tx_segment),
__alignof__(struct xilinx_vdma_tx_segment),
0);
}
if (!chan->desc_pool &&
(chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA)) {
dev_err(chan->dev,
"unable to allocate channel %d descriptor pool\n",
chan->id);
return -ENOMEM;
}
dma_cookie_init(dchan);
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
/* For AXI DMA resetting once channel will reset the
* other channel as well so enable the interrupts here.
*/
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
XILINX_DMA_DMAXR_ALL_IRQ_MASK);
}
if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
XILINX_CDMA_CR_SGMODE);
return 0;
}
/**
* xilinx_dma_tx_status - Get DMA transaction status
* @dchan: DMA channel
* @cookie: Transaction identifier
* @txstate: Transaction state
*
* Return: DMA transaction status
*/
static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_tx_descriptor *desc;
struct xilinx_axidma_tx_segment *segment;
struct xilinx_axidma_desc_hw *hw;
enum dma_status ret;
unsigned long flags;
u32 residue = 0;
ret = dma_cookie_status(dchan, cookie, txstate);
if (ret == DMA_COMPLETE || !txstate)
return ret;
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
spin_lock_irqsave(&chan->lock, flags);
desc = list_last_entry(&chan->active_list,
struct xilinx_dma_tx_descriptor, node);
if (chan->has_sg) {
list_for_each_entry(segment, &desc->segments, node) {
hw = &segment->hw;
residue += (hw->control - hw->status) &
chan->xdev->max_buffer_len;
}
}
spin_unlock_irqrestore(&chan->lock, flags);
chan->residue = residue;
if (chan->cyclic)
dma_set_residue(txstate, chan->buf_idx);
else
dma_set_residue(txstate, chan->residue);
}
return ret;
}
/**
* xilinx_dma_stop_transfer - Halt DMA channel
* @chan: Driver specific DMA channel
*
* Return: '0' on success and failure value on error
*/
static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
{
u32 val;
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
/* Wait for the hardware to halt */
return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
val & XILINX_DMA_DMASR_HALTED, 0,
XILINX_DMA_LOOP_COUNT);
}
/**
* xilinx_cdma_stop_transfer - Wait for the current transfer to complete
* @chan: Driver specific DMA channel
*
* Return: '0' on success and failure value on error
*/
static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
{
u32 val;
return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
val & XILINX_DMA_DMASR_IDLE, 0,
XILINX_DMA_LOOP_COUNT);
}
/**
* xilinx_dma_start - Start DMA channel
* @chan: Driver specific DMA channel
*/
static void xilinx_dma_start(struct xilinx_dma_chan *chan)
{
int err;
u32 val;
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
/* Wait for the hardware to start */
err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
!(val & XILINX_DMA_DMASR_HALTED), 0,
XILINX_DMA_LOOP_COUNT);
if (err) {
dev_err(chan->dev, "Cannot start channel %p: %x\n",
chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
chan->err = true;
}
}
/**
* xilinx_vdma_start_transfer - Starts VDMA transfer
* @chan: Driver specific channel struct pointer
*/
static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
{
struct xilinx_vdma_config *config = &chan->config;
struct xilinx_dma_tx_descriptor *desc, *tail_desc;
u32 reg, j;
struct xilinx_vdma_tx_segment *tail_segment;
/* This function was invoked with lock held */
if (chan->err)
return;
if (!chan->idle)
return;
if (list_empty(&chan->pending_list))
return;
desc = list_first_entry(&chan->pending_list,
struct xilinx_dma_tx_descriptor, node);
tail_desc = list_last_entry(&chan->pending_list,
struct xilinx_dma_tx_descriptor, node);
tail_segment = list_last_entry(&tail_desc->segments,
struct xilinx_vdma_tx_segment, node);
/*
* If hardware is idle, then all descriptors on the running lists are
* done, start new transfers
*/
if (chan->has_sg)
dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
desc->async_tx.phys);
/* Configure the hardware using info in the config structure */
if (chan->has_vflip) {
reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP;
reg |= config->vflip_en;
dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,
reg);
}
reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
if (config->frm_cnt_en)
reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
else
reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
/*
* With SG, start with circular mode, so that BDs can be fetched.
* In direct register mode, if not parking, enable circular mode
*/
if (chan->has_sg || !config->park)
reg |= XILINX_DMA_DMACR_CIRC_EN;
if (config->park)
reg &= ~XILINX_DMA_DMACR_CIRC_EN;
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
j = chan->desc_submitcount;
reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);
if (chan->direction == DMA_MEM_TO_DEV) {
reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK;
reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT;
} else {
reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK;
reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT;
}
dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);
/* Start the hardware */
xilinx_dma_start(chan);
if (chan->err)
return;
/* Start the transfer */
if (chan->has_sg) {
dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
tail_segment->phys);
list_splice_tail_init(&chan->pending_list, &chan->active_list);
chan->desc_pendingcount = 0;
} else {
struct xilinx_vdma_tx_segment *segment, *last = NULL;
int i = 0;
if (chan->desc_submitcount < chan->num_frms)
i = chan->desc_submitcount;
list_for_each_entry(segment, &desc->segments, node) {
if (chan->ext_addr)
vdma_desc_write_64(chan,
XILINX_VDMA_REG_START_ADDRESS_64(i++),
segment->hw.buf_addr,
segment->hw.buf_addr_msb);
else
vdma_desc_write(chan,
XILINX_VDMA_REG_START_ADDRESS(i++),
segment->hw.buf_addr);
last = segment;
}
if (!last)
return;
/* HW expects these parameters to be same for one transaction */
vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
last->hw.stride);
vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
chan->desc_submitcount++;
chan->desc_pendingcount--;
list_del(&desc->node);
list_add_tail(&desc->node, &chan->active_list);
if (chan->desc_submitcount == chan->num_frms)
chan->desc_submitcount = 0;
}
chan->idle = false;
}
/**
* xilinx_cdma_start_transfer - Starts cdma transfer
* @chan: Driver specific channel struct pointer
*/
static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
{
struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
struct xilinx_cdma_tx_segment *tail_segment;
u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
if (chan->err)
return;
if (!chan->idle)
return;
if (list_empty(&chan->pending_list))
return;
head_desc = list_first_entry(&chan->pending_list,
struct xilinx_dma_tx_descriptor, node);
tail_desc = list_last_entry(&chan->pending_list,
struct xilinx_dma_tx_descriptor, node);
tail_segment = list_last_entry(&tail_desc->segments,
struct xilinx_cdma_tx_segment, node);
if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
ctrl_reg |= chan->desc_pendingcount <<
XILINX_DMA_CR_COALESCE_SHIFT;
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
}
if (chan->has_sg) {
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
XILINX_CDMA_CR_SGMODE);
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
XILINX_CDMA_CR_SGMODE);
xilinx_write(chan, XILINX_DMA_REG_CURDESC,
head_desc->async_tx.phys);
/* Update tail ptr register which will start the transfer */
xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
tail_segment->phys);
} else {
/* In simple mode */
struct xilinx_cdma_tx_segment *segment;
struct xilinx_cdma_desc_hw *hw;
segment = list_first_entry(&head_desc->segments,
struct xilinx_cdma_tx_segment,
node);
hw = &segment->hw;
xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, (dma_addr_t)
((u64)hw->src_addr_msb << 32 | hw->src_addr));
xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, (dma_addr_t)
((u64)hw->dest_addr_msb << 32 | hw->dest_addr));
/* Start the transfer */
dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
hw->control & chan->xdev->max_buffer_len);
}
list_splice_tail_init(&chan->pending_list, &chan->active_list);
chan->desc_pendingcount = 0;
chan->idle = false;
}
/**
* xilinx_dma_start_transfer - Starts DMA transfer
* @chan: Driver specific channel struct pointer
*/
static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
{
struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
struct xilinx_axidma_tx_segment *tail_segment;
u32 reg;
if (chan->err)
return;
if (!chan->idle)
return;
if (list_empty(&chan->pending_list))
return;
head_desc = list_first_entry(&chan->pending_list,
struct xilinx_dma_tx_descriptor, node);
tail_desc = list_last_entry(&chan->pending_list,
struct xilinx_dma_tx_descriptor, node);
tail_segment = list_last_entry(&tail_desc->segments,
struct xilinx_axidma_tx_segment, node);
reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
reg &= ~XILINX_DMA_CR_COALESCE_MAX;
reg |= chan->desc_pendingcount <<
XILINX_DMA_CR_COALESCE_SHIFT;
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
}
if (chan->has_sg && !chan->xdev->mcdma)
xilinx_write(chan, XILINX_DMA_REG_CURDESC,
head_desc->async_tx.phys);
if (chan->has_sg && chan->xdev->mcdma) {
if (chan->direction == DMA_MEM_TO_DEV) {
dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
head_desc->async_tx.phys);
} else {
if (!chan->tdest) {
dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
head_desc->async_tx.phys);
} else {
dma_ctrl_write(chan,
XILINX_DMA_MCRX_CDESC(chan->tdest),
head_desc->async_tx.phys);
}
}
}
xilinx_dma_start(chan);
if (chan->err)
return;
/* Start the transfer */
if (chan->has_sg && !chan->xdev->mcdma) {
if (chan->cyclic)
xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
chan->cyclic_seg_v->phys);
else
xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
tail_segment->phys);
} else if (chan->has_sg && chan->xdev->mcdma) {
if (chan->direction == DMA_MEM_TO_DEV) {
dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
tail_segment->phys);
} else {
if (!chan->tdest) {
dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
tail_segment->phys);
} else {
dma_ctrl_write(chan,
XILINX_DMA_MCRX_TDESC(chan->tdest),
tail_segment->phys);
}
}
} else {
struct xilinx_axidma_tx_segment *segment;
struct xilinx_axidma_desc_hw *hw;
segment = list_first_entry(&head_desc->segments,
struct xilinx_axidma_tx_segment,
node);
hw = &segment->hw;
xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);
/* Start the transfer */
dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
hw->control & chan->xdev->max_buffer_len);
}
list_splice_tail_init(&chan->pending_list, &chan->active_list);
chan->desc_pendingcount = 0;
chan->idle = false;
}
/**
* xilinx_dma_issue_pending - Issue pending transactions
* @dchan: DMA channel
*/
static void xilinx_dma_issue_pending(struct dma_chan *dchan)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
unsigned long flags;
spin_lock_irqsave(&chan->lock, flags);
chan->start_transfer(chan);
spin_unlock_irqrestore(&chan->lock, flags);
}
/**
* xilinx_dma_complete_descriptor - Mark the active descriptor as complete
* @chan : xilinx DMA channel
*
* CONTEXT: hardirq
*/
static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
{
struct xilinx_dma_tx_descriptor *desc, *next;
/* This function was invoked with lock held */
if (list_empty(&chan->active_list))
return;
list_for_each_entry_safe(desc, next, &chan->active_list, node) {
list_del(&desc->node);
if (!desc->cyclic)
dma_cookie_complete(&desc->async_tx);
list_add_tail(&desc->node, &chan->done_list);
}
}
/**
* xilinx_dma_reset - Reset DMA channel
* @chan: Driver specific DMA channel
*
* Return: '0' on success and failure value on error
*/
static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
{
int err;
u32 tmp;
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
/* Wait for the hardware to finish reset */
err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
!(tmp & XILINX_DMA_DMACR_RESET), 0,
XILINX_DMA_LOOP_COUNT);
if (err) {
dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
return -ETIMEDOUT;
}
chan->err = false;
chan->idle = true;
chan->desc_submitcount = 0;
return err;
}
/**
* xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
* @chan: Driver specific DMA channel
*
* Return: '0' on success and failure value on error
*/
static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
{
int err;
/* Reset VDMA */
err = xilinx_dma_reset(chan);
if (err)
return err;
/* Enable interrupts */
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
XILINX_DMA_DMAXR_ALL_IRQ_MASK);
return 0;
}
/**
* xilinx_dma_irq_handler - DMA Interrupt handler
* @irq: IRQ number
* @data: Pointer to the Xilinx DMA channel structure
*
* Return: IRQ_HANDLED/IRQ_NONE
*/
static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
{
struct xilinx_dma_chan *chan = data;
u32 status;
/* Read the status and ack the interrupts. */
status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
return IRQ_NONE;
dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
if (status & XILINX_DMA_DMASR_ERR_IRQ) {
/*
* An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
* error is recoverable, ignore it. Otherwise flag the error.
*
* Only recoverable errors can be cleared in the DMASR register,
* make sure not to write to other error bits to 1.
*/
u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
if (!chan->flush_on_fsync ||
(errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
dev_err(chan->dev,
"Channel %p has errors %x, cdr %x tdr %x\n",
chan, errors,
dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
chan->err = true;
}
}
if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
/*
* Device takes too long to do the transfer when user requires
* responsiveness.
*/
dev_dbg(chan->dev, "Inter-packet latency too long\n");
}
if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
spin_lock(&chan->lock);
xilinx_dma_complete_descriptor(chan);
chan->idle = true;
chan->start_transfer(chan);
chan->buf_idx++;
spin_unlock(&chan->lock);
}
tasklet_schedule(&chan->tasklet);
return IRQ_HANDLED;
}
/**
* append_desc_queue - Queuing descriptor
* @chan: Driver specific dma channel
* @desc: dma transaction descriptor
*/
static void append_desc_queue(struct xilinx_dma_chan *chan,
struct xilinx_dma_tx_descriptor *desc)
{
struct xilinx_vdma_tx_segment *tail_segment;
struct xilinx_dma_tx_descriptor *tail_desc;
struct xilinx_axidma_tx_segment *axidma_tail_segment;
struct xilinx_cdma_tx_segment *cdma_tail_segment;
if (list_empty(&chan->pending_list))
goto append;
/*
* Add the hardware descriptor to the chain of hardware descriptors
* that already exists in memory.
*/
tail_desc = list_last_entry(&chan->pending_list,
struct xilinx_dma_tx_descriptor, node);
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
tail_segment = list_last_entry(&tail_desc->segments,
struct xilinx_vdma_tx_segment,
node);
tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
cdma_tail_segment = list_last_entry(&tail_desc->segments,
struct xilinx_cdma_tx_segment,
node);
cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
} else {
axidma_tail_segment = list_last_entry(&tail_desc->segments,
struct xilinx_axidma_tx_segment,
node);
axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
}
/*
* Add the software descriptor and all children to the list
* of pending transactions
*/
append:
list_add_tail(&desc->node, &chan->pending_list);
chan->desc_pendingcount++;
if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
&& unlikely(chan->desc_pendingcount > chan->num_frms)) {
dev_dbg(chan->dev, "desc pendingcount is too high\n");
chan->desc_pendingcount = chan->num_frms;
}
}
/**
* xilinx_dma_tx_submit - Submit DMA transaction
* @tx: Async transaction descriptor
*
* Return: cookie value on success and failure value on error
*/
static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
{
struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
dma_cookie_t cookie;
unsigned long flags;
int err;
if (chan->cyclic) {
xilinx_dma_free_tx_descriptor(chan, desc);
return -EBUSY;
}
if (chan->err) {
/*
* If reset fails, need to hard reset the system.
* Channel is no longer functional
*/
err = xilinx_dma_chan_reset(chan);
if (err < 0)
return err;
}
spin_lock_irqsave(&chan->lock, flags);
cookie = dma_cookie_assign(tx);
/* Put this transaction onto the tail of the pending queue */
append_desc_queue(chan, desc);
if (desc->cyclic)
chan->cyclic = true;
spin_unlock_irqrestore(&chan->lock, flags);
return cookie;
}
/**
* xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
* DMA_SLAVE transaction
* @dchan: DMA channel
* @xt: Interleaved template pointer
* @flags: transfer ack flags
*
* Return: Async transaction descriptor on success and NULL on failure
*/
static struct dma_async_tx_descriptor *
xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
struct dma_interleaved_template *xt,
unsigned long flags)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_tx_descriptor *desc;
struct xilinx_vdma_tx_segment *segment;
struct xilinx_vdma_desc_hw *hw;
if (!is_slave_direction(xt->dir))
return NULL;
if (!xt->numf || !xt->sgl[0].size)
return NULL;
if (xt->frame_size != 1)
return NULL;
/* Allocate a transaction descriptor. */
desc = xilinx_dma_alloc_tx_descriptor(chan);
if (!desc)
return NULL;
dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
desc->async_tx.tx_submit = xilinx_dma_tx_submit;
async_tx_ack(&desc->async_tx);
/* Allocate the link descriptor from DMA pool */
segment = xilinx_vdma_alloc_tx_segment(chan);
if (!segment)
goto error;
/* Fill in the hardware descriptor */
hw = &segment->hw;
hw->vsize = xt->numf;
hw->hsize = xt->sgl[0].size;
hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
hw->stride |= chan->config.frm_dly <<
XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
if (xt->dir != DMA_MEM_TO_DEV) {
if (chan->ext_addr) {
hw->buf_addr = lower_32_bits(xt->dst_start);
hw->buf_addr_msb = upper_32_bits(xt->dst_start);
} else {
hw->buf_addr = xt->dst_start;
}
} else {
if (chan->ext_addr) {
hw->buf_addr = lower_32_bits(xt->src_start);
hw->buf_addr_msb = upper_32_bits(xt->src_start);
} else {
hw->buf_addr = xt->src_start;
}
}
/* Insert the segment into the descriptor segments list. */
list_add_tail(&segment->node, &desc->segments);
/* Link the last hardware descriptor with the first. */
segment = list_first_entry(&desc->segments,
struct xilinx_vdma_tx_segment, node);
desc->async_tx.phys = segment->phys;
return &desc->async_tx;
error:
xilinx_dma_free_tx_descriptor(chan, desc);
return NULL;
}
/**
* xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
* @dchan: DMA channel
* @dma_dst: destination address
* @dma_src: source address
* @len: transfer length
* @flags: transfer ack flags
*
* Return: Async transaction descriptor on success and NULL on failure
*/
static struct dma_async_tx_descriptor *
xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
dma_addr_t dma_src, size_t len, unsigned long flags)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_tx_descriptor *desc;
struct xilinx_cdma_tx_segment *segment;
struct xilinx_cdma_desc_hw *hw;
if (!len || len > chan->xdev->max_buffer_len)
return NULL;
desc = xilinx_dma_alloc_tx_descriptor(chan);
if (!desc)
return NULL;
dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
desc->async_tx.tx_submit = xilinx_dma_tx_submit;
/* Allocate the link descriptor from DMA pool */
segment = xilinx_cdma_alloc_tx_segment(chan);
if (!segment)
goto error;
hw = &segment->hw;
hw->control = len;
hw->src_addr = dma_src;
hw->dest_addr = dma_dst;
if (chan->ext_addr) {
hw->src_addr_msb = upper_32_bits(dma_src);
hw->dest_addr_msb = upper_32_bits(dma_dst);
}
/* Insert the segment into the descriptor segments list. */
list_add_tail(&segment->node, &desc->segments);
desc->async_tx.phys = segment->phys;
hw->next_desc = segment->phys;
return &desc->async_tx;
error:
xilinx_dma_free_tx_descriptor(chan, desc);
return NULL;
}
/**
* xilinx_cdma_prep_sg - prepare descriptors for a memory sg transaction
* @dchan: DMA channel
* @dst_sg: Destination scatter list
* @dst_sg_len: Number of entries in destination scatter list
* @src_sg: Source scatter list
* @src_sg_len: Number of entries in source scatter list
* @flags: transfer ack flags
*
* Return: Async transaction descriptor on success and NULL on failure
*/
static struct dma_async_tx_descriptor *xilinx_cdma_prep_sg(
struct dma_chan *dchan, struct scatterlist *dst_sg,
unsigned int dst_sg_len, struct scatterlist *src_sg,
unsigned int src_sg_len, unsigned long flags)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_tx_descriptor *desc;
struct xilinx_cdma_tx_segment *segment, *prev = NULL;
struct xilinx_cdma_desc_hw *hw;
size_t len, dst_avail, src_avail;
dma_addr_t dma_dst, dma_src;
if (unlikely(dst_sg_len == 0 || src_sg_len == 0))
return NULL;
if (unlikely(dst_sg == NULL || src_sg == NULL))
return NULL;
desc = xilinx_dma_alloc_tx_descriptor(chan);
if (!desc)
return NULL;
dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
desc->async_tx.tx_submit = xilinx_dma_tx_submit;
dst_avail = sg_dma_len(dst_sg);
src_avail = sg_dma_len(src_sg);
/*
* loop until there is either no more source or no more destination
* scatterlist entry
*/
while (true) {
len = min_t(size_t, src_avail, dst_avail);
len = min_t(size_t, len, chan->xdev->max_buffer_len);
if (len == 0)
goto fetch;
/* Allocate the link descriptor from DMA pool */
segment = xilinx_cdma_alloc_tx_segment(chan);
if (!segment)
goto error;
dma_dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) -
dst_avail;
dma_src = sg_dma_address(src_sg) + sg_dma_len(src_sg) -
src_avail;
hw = &segment->hw;
hw->control = len;
hw->src_addr = dma_src;
hw->dest_addr = dma_dst;
if (chan->ext_addr) {
hw->src_addr_msb = upper_32_bits(dma_src);
hw->dest_addr_msb = upper_32_bits(dma_dst);
}
if (prev)
prev->hw.next_desc = segment->phys;
prev = segment;
dst_avail -= len;
src_avail -= len;
list_add_tail(&segment->node, &desc->segments);
fetch:
/* Fetch the next dst scatterlist entry */
if (dst_avail == 0) {
if (dst_sg_len == 0)
break;
dst_sg = sg_next(dst_sg);
if (dst_sg == NULL)
break;
dst_sg_len--;
dst_avail = sg_dma_len(dst_sg);
}
/* Fetch the next src scatterlist entry */
if (src_avail == 0) {
if (src_sg_len == 0)
break;
src_sg = sg_next(src_sg);
if (src_sg == NULL)
break;
src_sg_len--;
src_avail = sg_dma_len(src_sg);
}
}
/* Link the last hardware descriptor with the first. */
segment = list_first_entry(&desc->segments,
struct xilinx_cdma_tx_segment, node);
desc->async_tx.phys = segment->phys;
prev->hw.next_desc = segment->phys;
return &desc->async_tx;
error:
xilinx_dma_free_tx_descriptor(chan, desc);
return NULL;
}
/**
* xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
* @dchan: DMA channel
* @sgl: scatterlist to transfer to/from
* @sg_len: number of entries in @scatterlist
* @direction: DMA direction
* @flags: transfer ack flags
* @context: APP words of the descriptor
*
* Return: Async transaction descriptor on success and NULL on failure
*/
static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
enum dma_transfer_direction direction, unsigned long flags,
void *context)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_tx_descriptor *desc;
struct xilinx_axidma_tx_segment *segment = NULL;
u32 *app_w = (u32 *)context;
struct scatterlist *sg;
size_t copy;
size_t sg_used;
unsigned int i;
if (!is_slave_direction(direction))
return NULL;
/* Allocate a transaction descriptor. */
desc = xilinx_dma_alloc_tx_descriptor(chan);
if (!desc)
return NULL;
dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
desc->async_tx.tx_submit = xilinx_dma_tx_submit;
/* Build transactions using information in the scatter gather list */
for_each_sg(sgl, sg, sg_len, i) {
sg_used = 0;
/* Loop until the entire scatterlist entry is used */
while (sg_used < sg_dma_len(sg)) {
struct xilinx_axidma_desc_hw *hw;
/* Get a free segment */
segment = xilinx_axidma_alloc_tx_segment(chan);
if (!segment)
goto error;
/*
* Calculate the maximum number of bytes to transfer,
* making sure it is less than the hw limit
*/
copy = min_t(size_t, sg_dma_len(sg) - sg_used,
chan->xdev->max_buffer_len);
hw = &segment->hw;
/* Fill in the descriptor */
xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
sg_used, 0);
hw->control = copy;
if (chan->direction == DMA_MEM_TO_DEV) {
if (app_w)
memcpy(hw->app, app_w, sizeof(u32) *
XILINX_DMA_NUM_APP_WORDS);
}
sg_used += copy;
/*
* Insert the segment into the descriptor segments
* list.
*/
list_add_tail(&segment->node, &desc->segments);
}
}
segment = list_first_entry(&desc->segments,
struct xilinx_axidma_tx_segment, node);
desc->async_tx.phys = segment->phys;
/* For the last DMA_MEM_TO_DEV transfer, set EOP */
if (chan->direction == DMA_MEM_TO_DEV) {
segment->hw.control |= XILINX_DMA_BD_SOP;
segment = list_last_entry(&desc->segments,
struct xilinx_axidma_tx_segment,
node);
segment->hw.control |= XILINX_DMA_BD_EOP;
}
return &desc->async_tx;
error:
xilinx_dma_free_tx_descriptor(chan, desc);
return NULL;
}
/**
* xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
* @dchan: DMA channel
* @buf_addr: Physical address of the buffer
* @buf_len: Total length of the cyclic buffers
* @period_len: length of individual cyclic buffer
* @direction: DMA direction
* @flags: transfer ack flags
*
* Return: Async transaction descriptor on success and NULL on failure
*/
static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
size_t period_len, enum dma_transfer_direction direction,
unsigned long flags)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_tx_descriptor *desc;
struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
size_t copy, sg_used;
unsigned int num_periods;
int i;
u32 reg;
if (!period_len)
return NULL;
num_periods = buf_len / period_len;
if (!num_periods)
return NULL;
if (!is_slave_direction(direction))
return NULL;
/* Allocate a transaction descriptor. */
desc = xilinx_dma_alloc_tx_descriptor(chan);
if (!desc)
return NULL;
chan->direction = direction;
dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
desc->async_tx.tx_submit = xilinx_dma_tx_submit;
chan->buf_idx = 0;
for (i = 0; i < num_periods; ++i) {
sg_used = 0;
while (sg_used < period_len) {
struct xilinx_axidma_desc_hw *hw;
/* Get a free segment */
segment = xilinx_axidma_alloc_tx_segment(chan);
if (!segment)
goto error;
/*
* Calculate the maximum number of bytes to transfer,
* making sure it is less than the hw limit
*/
copy = min_t(size_t, period_len - sg_used,
chan->xdev->max_buffer_len);
hw = &segment->hw;
xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
period_len * i);
hw->control = copy;
if (prev)
prev->hw.next_desc = segment->phys;
prev = segment;
sg_used += copy;
/*
* Insert the segment into the descriptor segments
* list.
*/
list_add_tail(&segment->node, &desc->segments);
}
}
head_segment = list_first_entry(&desc->segments,
struct xilinx_axidma_tx_segment, node);
desc->async_tx.phys = head_segment->phys;
desc->cyclic = true;
reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
segment = list_last_entry(&desc->segments,
struct xilinx_axidma_tx_segment,
node);
segment->hw.next_desc = (u32) head_segment->phys;
/* For the last DMA_MEM_TO_DEV transfer, set EOP */
if (direction == DMA_MEM_TO_DEV) {
head_segment->hw.control |= XILINX_DMA_BD_SOP;
segment->hw.control |= XILINX_DMA_BD_EOP;
}
return &desc->async_tx;
error:
xilinx_dma_free_tx_descriptor(chan, desc);
return NULL;
}
/**
* xilinx_dma_prep_interleaved - prepare a descriptor for a
* DMA_SLAVE transaction
* @dchan: DMA channel
* @xt: Interleaved template pointer
* @flags: transfer ack flags
*
* Return: Async transaction descriptor on success and NULL on failure
*/
static struct dma_async_tx_descriptor *
xilinx_dma_prep_interleaved(struct dma_chan *dchan,
struct dma_interleaved_template *xt,
unsigned long flags)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_tx_descriptor *desc;
struct xilinx_axidma_tx_segment *segment;
struct xilinx_axidma_desc_hw *hw;
if (!is_slave_direction(xt->dir))
return NULL;
if (!xt->numf || !xt->sgl[0].size)
return NULL;
if (xt->frame_size != 1)
return NULL;
/* Allocate a transaction descriptor. */
desc = xilinx_dma_alloc_tx_descriptor(chan);
if (!desc)
return NULL;
chan->direction = xt->dir;
dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
desc->async_tx.tx_submit = xilinx_dma_tx_submit;
/* Get a free segment */
segment = xilinx_axidma_alloc_tx_segment(chan);
if (!segment)
goto error;
hw = &segment->hw;
/* Fill in the descriptor */
if (xt->dir != DMA_MEM_TO_DEV)
hw->buf_addr = xt->dst_start;
else
hw->buf_addr = xt->src_start;
hw->mcdma_control = chan->tdest & XILINX_DMA_BD_TDEST_MASK;
hw->vsize_stride = (xt->numf << XILINX_DMA_BD_VSIZE_SHIFT) &
XILINX_DMA_BD_VSIZE_MASK;
hw->vsize_stride |= (xt->sgl[0].icg + xt->sgl[0].size) &
XILINX_DMA_BD_STRIDE_MASK;
hw->control = xt->sgl[0].size & XILINX_DMA_BD_HSIZE_MASK;
/*
* Insert the segment into the descriptor segments
* list.
*/
list_add_tail(&segment->node, &desc->segments);
segment = list_first_entry(&desc->segments,
struct xilinx_axidma_tx_segment, node);
desc->async_tx.phys = segment->phys;
/* For the last DMA_MEM_TO_DEV transfer, set EOP */
if (xt->dir == DMA_MEM_TO_DEV) {
segment->hw.control |= XILINX_DMA_BD_SOP;
segment = list_last_entry(&desc->segments,
struct xilinx_axidma_tx_segment,
node);
segment->hw.control |= XILINX_DMA_BD_EOP;
}
return &desc->async_tx;
error:
xilinx_dma_free_tx_descriptor(chan, desc);
return NULL;
}
/**
* xilinx_dma_terminate_all - Halt the channel and free descriptors
* @dchan: Driver specific DMA Channel pointer
*
* Return: '0' always.
*/
static int xilinx_dma_terminate_all(struct dma_chan *dchan)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
u32 reg;
int err;
if (!chan->cyclic) {
err = chan->stop_transfer(chan);
if (err) {
dev_err(chan->dev, "Cannot stop channel %p: %x\n",
chan, dma_ctrl_read(chan,
XILINX_DMA_REG_DMASR));
chan->err = true;
}
}
xilinx_dma_chan_reset(chan);
/* Remove and free all of the descriptors in the lists */
xilinx_dma_free_descriptors(chan);
chan->idle = true;
if (chan->cyclic) {
reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
chan->cyclic = false;
}
if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
XILINX_CDMA_CR_SGMODE);
return 0;
}
/**
* xilinx_dma_channel_set_config - Configure VDMA channel
* Run-time configuration for Axi VDMA, supports:
* . halt the channel
* . configure interrupt coalescing and inter-packet delay threshold
* . start/stop parking
* . enable genlock
*
* @dchan: DMA channel
* @cfg: VDMA device configuration pointer
*
* Return: '0' on success and failure value on error
*/
int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
struct xilinx_vdma_config *cfg)
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
u32 dmacr;
if (cfg->reset)
return xilinx_dma_chan_reset(chan);
dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
chan->config.frm_dly = cfg->frm_dly;
chan->config.park = cfg->park;
/* genlock settings */
chan->config.gen_lock = cfg->gen_lock;
chan->config.master = cfg->master;
if (cfg->gen_lock && chan->genlock) {
dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
}
chan->config.frm_cnt_en = cfg->frm_cnt_en;
chan->config.vflip_en = cfg->vflip_en;
if (cfg->park)
chan->config.park_frm = cfg->park_frm;
else
chan->config.park_frm = -1;
chan->config.coalesc = cfg->coalesc;
chan->config.delay = cfg->delay;
if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
chan->config.coalesc = cfg->coalesc;
}
if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
chan->config.delay = cfg->delay;
}
/* FSync Source selection */
dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
return 0;
}
EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
/* -----------------------------------------------------------------------------
* Probe and remove
*/
/**
* xilinx_dma_chan_remove - Per Channel remove function
* @chan: Driver specific DMA channel
*/
static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
{
/* Disable all interrupts */
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
XILINX_DMA_DMAXR_ALL_IRQ_MASK);
if (chan->irq > 0)
free_irq(chan->irq, chan);
tasklet_kill(&chan->tasklet);
list_del(&chan->common.device_node);
}
static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
struct clk **tx_clk, struct clk **rx_clk,
struct clk **sg_clk, struct clk **tmp_clk)
{
int err;
*tmp_clk = NULL;
*axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
if (IS_ERR(*axi_clk)) {
err = PTR_ERR(*axi_clk);
dev_err(&pdev->dev, "failed to get axi_aclk (%d)\n", err);
return err;
}
*tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
if (IS_ERR(*tx_clk))
*tx_clk = NULL;
*rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
if (IS_ERR(*rx_clk))
*rx_clk = NULL;
*sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
if (IS_ERR(*sg_clk))
*sg_clk = NULL;
err = clk_prepare_enable(*axi_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
return err;
}
err = clk_prepare_enable(*tx_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
goto err_disable_axiclk;
}
err = clk_prepare_enable(*rx_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
goto err_disable_txclk;
}
err = clk_prepare_enable(*sg_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err);
goto err_disable_rxclk;
}
return 0;
err_disable_rxclk:
clk_disable_unprepare(*rx_clk);
err_disable_txclk:
clk_disable_unprepare(*tx_clk);
err_disable_axiclk:
clk_disable_unprepare(*axi_clk);
return err;
}
static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
struct clk **dev_clk, struct clk **tmp_clk,
struct clk **tmp1_clk, struct clk **tmp2_clk)
{
int err;
*tmp_clk = NULL;
*tmp1_clk = NULL;
*tmp2_clk = NULL;
*axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
if (IS_ERR(*axi_clk)) {
err = PTR_ERR(*axi_clk);
dev_err(&pdev->dev, "failed to get axi_clk (%d)\n", err);
return err;
}
*dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
if (IS_ERR(*dev_clk)) {
err = PTR_ERR(*dev_clk);
dev_err(&pdev->dev, "failed to get dev_clk (%d)\n", err);
return err;
}
err = clk_prepare_enable(*axi_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
return err;
}
err = clk_prepare_enable(*dev_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err);
goto err_disable_axiclk;
}
return 0;
err_disable_axiclk:
clk_disable_unprepare(*axi_clk);
return err;
}
static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
struct clk **tx_clk, struct clk **txs_clk,
struct clk **rx_clk, struct clk **rxs_clk)
{
int err;
*axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
if (IS_ERR(*axi_clk)) {
err = PTR_ERR(*axi_clk);
dev_err(&pdev->dev, "failed to get axi_aclk (%d)\n", err);
return err;
}
*tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
if (IS_ERR(*tx_clk))
*tx_clk = NULL;
*txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
if (IS_ERR(*txs_clk))
*txs_clk = NULL;
*rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
if (IS_ERR(*rx_clk))
*rx_clk = NULL;
*rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
if (IS_ERR(*rxs_clk))
*rxs_clk = NULL;
err = clk_prepare_enable(*axi_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
return err;
}
err = clk_prepare_enable(*tx_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
goto err_disable_axiclk;
}
err = clk_prepare_enable(*txs_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err);
goto err_disable_txclk;
}
err = clk_prepare_enable(*rx_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
goto err_disable_txsclk;
}
err = clk_prepare_enable(*rxs_clk);
if (err) {
dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err);
goto err_disable_rxclk;
}
return 0;
err_disable_rxclk:
clk_disable_unprepare(*rx_clk);
err_disable_txsclk:
clk_disable_unprepare(*txs_clk);
err_disable_txclk:
clk_disable_unprepare(*tx_clk);
err_disable_axiclk:
clk_disable_unprepare(*axi_clk);
return err;
}
static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
{
clk_disable_unprepare(xdev->rxs_clk);
clk_disable_unprepare(xdev->rx_clk);
clk_disable_unprepare(xdev->txs_clk);
clk_disable_unprepare(xdev->tx_clk);
clk_disable_unprepare(xdev->axi_clk);
}
/**
* xilinx_dma_chan_probe - Per Channel Probing
* It get channel features from the device tree entry and
* initialize special channel handling routines
*
* @xdev: Driver specific device structure
* @node: Device node
* @chan_id: DMA Channel id
*
* Return: '0' on success and failure value on error
*/
static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
struct device_node *node, int chan_id)
{
struct xilinx_dma_chan *chan;
bool has_dre = false;
u32 value, width;
int err;
/* Allocate and initialize the channel structure */
chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
if (!chan)
return -ENOMEM;
chan->dev = xdev->dev;
chan->xdev = xdev;
chan->has_sg = xdev->has_sg;
chan->desc_pendingcount = 0x0;
chan->ext_addr = xdev->ext_addr;
/* This variable ensures that descriptors are not
* Submitted when dma engine is in progress. This variable is
* Added to avoid polling for a bit in the status register to
* Know dma state in the driver hot path.
*/
chan->idle = true;
spin_lock_init(&chan->lock);
INIT_LIST_HEAD(&chan->pending_list);
INIT_LIST_HEAD(&chan->done_list);
INIT_LIST_HEAD(&chan->active_list);
INIT_LIST_HEAD(&chan->free_seg_list);
/* Retrieve the channel properties from the device tree */
has_dre = of_property_read_bool(node, "xlnx,include-dre");
chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
err = of_property_read_u32(node, "xlnx,datawidth", &value);
if (err) {
dev_err(xdev->dev, "missing xlnx,datawidth property\n");
return err;
}
width = value >> 3; /* Convert bits to bytes */
/* If data width is greater than 8 bytes, DRE is not in hw */
if (width > 8)
has_dre = false;
if (!has_dre)
xdev->common.copy_align = fls(width - 1);
if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
chan->direction = DMA_MEM_TO_DEV;
chan->id = chan_id;
chan->tdest = chan_id;
xdev->common.directions = BIT(DMA_MEM_TO_DEV);
chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
chan->config.park = 1;
if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
chan->flush_on_fsync = true;
}
} else if (of_device_is_compatible(node,
"xlnx,axi-vdma-s2mm-channel") ||
of_device_is_compatible(node,
"xlnx,axi-dma-s2mm-channel")) {
chan->direction = DMA_DEV_TO_MEM;
chan->id = chan_id;
chan->tdest = chan_id - xdev->nr_channels;
xdev->common.directions |= BIT(DMA_DEV_TO_MEM);
chan->has_vflip = of_property_read_bool(node,
"xlnx,enable-vert-flip");
if (chan->has_vflip) {
chan->config.vflip_en = dma_read(chan,
XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) &
XILINX_VDMA_ENABLE_VERTICAL_FLIP;
}
chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
chan->config.park = 1;
if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
chan->flush_on_fsync = true;
}
} else {
dev_err(xdev->dev, "Invalid channel compatible node\n");
return -EINVAL;
}
/* Request the interrupt */
chan->irq = irq_of_parse_and_map(node, 0);
err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED,
"xilinx-dma-controller", chan);
if (err) {
dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
return err;
}
if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
chan->start_transfer = xilinx_dma_start_transfer;
chan->stop_transfer = xilinx_dma_stop_transfer;
} else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
chan->start_transfer = xilinx_cdma_start_transfer;
chan->stop_transfer = xilinx_cdma_stop_transfer;
} else {
chan->start_transfer = xilinx_vdma_start_transfer;
chan->stop_transfer = xilinx_dma_stop_transfer;
}
/* Initialize the tasklet */
tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet,
(unsigned long)chan);
/*
* Initialize the DMA channel and add it to the DMA engine channels
* list.
*/
chan->common.device = &xdev->common;
list_add_tail(&chan->common.device_node, &xdev->common.channels);
xdev->chan[chan->id] = chan;
/* Reset the channel */
err = xilinx_dma_chan_reset(chan);
if (err < 0) {
dev_err(xdev->dev, "Reset channel failed\n");
return err;
}
return 0;
}
/**
* xilinx_dma_child_probe - Per child node probe
* It get number of dma-channels per child node from
* device-tree and initializes all the channels.
*
* @xdev: Driver specific device structure
* @node: Device node
*
* Return: 0 always.
*/
static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
struct device_node *node)
{
int ret, i, nr_channels = 1;
ret = of_property_read_u32(node, "dma-channels", &nr_channels);
if ((ret < 0) && xdev->mcdma)
dev_warn(xdev->dev, "missing dma-channels property\n");
for (i = 0; i < nr_channels; i++)
xilinx_dma_chan_probe(xdev, node, xdev->chan_id++);
xdev->nr_channels += nr_channels;
return 0;
}
/**
* of_dma_xilinx_xlate - Translation function
* @dma_spec: Pointer to DMA specifier as found in the device tree
* @ofdma: Pointer to DMA controller data
*
* Return: DMA channel pointer on success and NULL on error
*/
static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
struct of_dma *ofdma)
{
struct xilinx_dma_device *xdev = ofdma->of_dma_data;
int chan_id = dma_spec->args[0];
if (chan_id >= xdev->nr_channels || !xdev->chan[chan_id])
return NULL;
return dma_get_slave_channel(&xdev->chan[chan_id]->common);
}
static const struct xilinx_dma_config axidma_config = {
.dmatype = XDMA_TYPE_AXIDMA,
.clk_init = axidma_clk_init,
};
static const struct xilinx_dma_config axicdma_config = {
.dmatype = XDMA_TYPE_CDMA,
.clk_init = axicdma_clk_init,
};
static const struct xilinx_dma_config axivdma_config = {
.dmatype = XDMA_TYPE_VDMA,
.clk_init = axivdma_clk_init,
};
static const struct of_device_id xilinx_dma_of_ids[] = {
{ .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
{ .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
{ .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
{}
};
MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
/**
* xilinx_dma_probe - Driver probe function
* @pdev: Pointer to the platform_device structure
*
* Return: '0' on success and failure value on error
*/
static int xilinx_dma_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
struct clk **, struct clk **, struct clk **)
= axivdma_clk_init;
struct device_node *node = pdev->dev.of_node;
struct xilinx_dma_device *xdev;
struct device_node *child, *np = pdev->dev.of_node;
struct resource *io;
u32 num_frames, addr_width, len_width;
int i, err;
/* Allocate and initialize the DMA engine structure */
xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
if (!xdev)
return -ENOMEM;
xdev->dev = &pdev->dev;
if (np) {
const struct of_device_id *match;
match = of_match_node(xilinx_dma_of_ids, np);
if (match && match->data) {
xdev->dma_config = match->data;
clk_init = xdev->dma_config->clk_init;
}
}
err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
&xdev->rx_clk, &xdev->rxs_clk);
if (err)
return err;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
xdev->regs = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(xdev->regs))
return PTR_ERR(xdev->regs);
/* Retrieve the DMA engine properties from the device tree */
xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg");
xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
if (!of_property_read_u32(node, "xlnx,sg-length-width",
&len_width)) {
if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
dev_warn(xdev->dev,
"invalid xlnx,sg-length-width property value using default width\n");
} else {
if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
xdev->max_buffer_len = GENMASK(len_width - 1, 0);
}
}
}
if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
err = of_property_read_u32(node, "xlnx,num-fstores",
&num_frames);
if (err < 0) {
dev_err(xdev->dev,
"missing xlnx,num-fstores property\n");
return err;
}
err = of_property_read_u32(node, "xlnx,flush-fsync",
&xdev->flush_on_fsync);
if (err < 0)
dev_warn(xdev->dev,
"missing xlnx,flush-fsync property\n");
}
err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
if (err < 0)
dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
if (addr_width > 32)
xdev->ext_addr = true;
else
xdev->ext_addr = false;
/* Set the dma mask bits */
dma_set_mask(xdev->dev, DMA_BIT_MASK(addr_width));
/* Initialize the DMA engine */
xdev->common.dev = &pdev->dev;
INIT_LIST_HEAD(&xdev->common.channels);
if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
}
xdev->common.dst_addr_widths = BIT(addr_width / 8);
xdev->common.src_addr_widths = BIT(addr_width / 8);
xdev->common.device_alloc_chan_resources =
xilinx_dma_alloc_chan_resources;
xdev->common.device_free_chan_resources =
xilinx_dma_free_chan_resources;
xdev->common.device_terminate_all = xilinx_dma_terminate_all;
xdev->common.device_tx_status = xilinx_dma_tx_status;
xdev->common.device_issue_pending = xilinx_dma_issue_pending;
if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
xdev->common.device_prep_dma_cyclic =
xilinx_dma_prep_dma_cyclic;
xdev->common.device_prep_interleaved_dma =
xilinx_dma_prep_interleaved;
/* Residue calculation is supported by only AXI DMA */
xdev->common.residue_granularity =
DMA_RESIDUE_GRANULARITY_SEGMENT;
} else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
dma_cap_set(DMA_SG, xdev->common.cap_mask);
xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
xdev->common.device_prep_dma_sg = xilinx_cdma_prep_sg;
} else {
xdev->common.device_prep_interleaved_dma =
xilinx_vdma_dma_prep_interleaved;
}
platform_set_drvdata(pdev, xdev);
/* Initialize the channels */
for_each_child_of_node(node, child) {
err = xilinx_dma_child_probe(xdev, child);
if (err < 0)
goto disable_clks;
}
if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
for (i = 0; i < xdev->nr_channels; i++)
if (xdev->chan[i])
xdev->chan[i]->num_frms = num_frames;
}
/* Register the DMA engine with the core */
dma_async_device_register(&xdev->common);
err = of_dma_controller_register(node, of_dma_xilinx_xlate,
xdev);
if (err < 0) {
dev_err(&pdev->dev, "Unable to register DMA to DT\n");
dma_async_device_unregister(&xdev->common);
goto error;
}
if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n");
else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n");
else
dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
return 0;
disable_clks:
xdma_disable_allclks(xdev);
error:
for (i = 0; i < xdev->nr_channels; i++)
if (xdev->chan[i])
xilinx_dma_chan_remove(xdev->chan[i]);
return err;
}
/**
* xilinx_dma_remove - Driver remove function
* @pdev: Pointer to the platform_device structure
*
* Return: Always '0'
*/
static int xilinx_dma_remove(struct platform_device *pdev)
{
struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
int i;
of_dma_controller_free(pdev->dev.of_node);
dma_async_device_unregister(&xdev->common);
for (i = 0; i < xdev->nr_channels; i++)
if (xdev->chan[i])
xilinx_dma_chan_remove(xdev->chan[i]);
xdma_disable_allclks(xdev);
return 0;
}
static struct platform_driver xilinx_vdma_driver = {
.driver = {
.name = "xilinx-vdma",
.of_match_table = xilinx_dma_of_ids,
},
.probe = xilinx_dma_probe,
.remove = xilinx_dma_remove,
};
module_platform_driver(xilinx_vdma_driver);
MODULE_AUTHOR("Xilinx, Inc. and Xianjun Jiao");
MODULE_DESCRIPTION("Xilinx VDMA driver");
MODULE_LICENSE("GPL v2");
================================================
FILE: driver/xpu/Makefile
================================================
# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += xpu.o
all:
make -C $(KDIR) M=$(PWD) modules
# ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order
================================================
FILE: driver/xpu/xpu.c
================================================
/*
* axi lite register access driver
* Author: Xianjun Jiao, Michael Mehari, Wei Liu
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline void XPU_REG_MULTI_RST_write(u32 Data) {
reg_write(XPU_REG_MULTI_RST_ADDR, Data);
}
static inline u32 XPU_REG_MULTI_RST_read(void){
return reg_read(XPU_REG_MULTI_RST_ADDR);
}
static inline void XPU_REG_SRC_SEL_write(u32 Data) {
reg_write(XPU_REG_SRC_SEL_ADDR, Data);
}
static inline u32 XPU_REG_SRC_SEL_read(void){
return reg_read(XPU_REG_SRC_SEL_ADDR);
}
static inline void XPU_REG_RECV_ACK_COUNT_TOP0_write(u32 Data) {
reg_write(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR, Data);
}
static inline u32 XPU_REG_RECV_ACK_COUNT_TOP0_read(void){
return reg_read(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR);
}
static inline void XPU_REG_RECV_ACK_COUNT_TOP1_write(u32 Data) {
reg_write(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR, Data);
}
static inline u32 XPU_REG_RECV_ACK_COUNT_TOP1_read(void){
return reg_read(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR);
}
static inline void XPU_REG_SEND_ACK_WAIT_TOP_write(u32 Data) {
reg_write(XPU_REG_SEND_ACK_WAIT_TOP_ADDR, Data);
}
static inline u32 XPU_REG_SEND_ACK_WAIT_TOP_read(void){
return reg_read(XPU_REG_SEND_ACK_WAIT_TOP_ADDR);
}
static inline void XPU_REG_FILTER_FLAG_write(u32 Data) {
reg_write(XPU_REG_FILTER_FLAG_ADDR, Data);
}
static inline u32 XPU_REG_FILTER_FLAG_read(void){
return reg_read(XPU_REG_FILTER_FLAG_ADDR);
}
static inline void XPU_REG_CTS_TO_RTS_CONFIG_write(u32 Data) {
reg_write(XPU_REG_CTS_TO_RTS_CONFIG_ADDR, Data);
}
static inline u32 XPU_REG_CTS_TO_RTS_CONFIG_read(void){
return reg_read(XPU_REG_CTS_TO_RTS_CONFIG_ADDR);
}
static inline void XPU_REG_MAC_ADDR_LOW_write(u32 Data) {
reg_write(XPU_REG_MAC_ADDR_LOW_ADDR, Data);
}
static inline u32 XPU_REG_MAC_ADDR_LOW_read(void){
return reg_read(XPU_REG_MAC_ADDR_LOW_ADDR);
}
static inline void XPU_REG_MAC_ADDR_HIGH_write(u32 Data) {
reg_write(XPU_REG_MAC_ADDR_HIGH_ADDR, Data);
}
static inline u32 XPU_REG_MAC_ADDR_HIGH_read(void){
return reg_read(XPU_REG_MAC_ADDR_HIGH_ADDR);
}
static inline void XPU_REG_BSSID_FILTER_LOW_write(u32 Data) {
reg_write(XPU_REG_BSSID_FILTER_LOW_ADDR, Data);
}
static inline u32 XPU_REG_BSSID_FILTER_LOW_read(void){
return reg_read(XPU_REG_BSSID_FILTER_LOW_ADDR);
}
static inline void XPU_REG_BSSID_FILTER_HIGH_write(u32 Data) {
reg_write(XPU_REG_BSSID_FILTER_HIGH_ADDR, Data);
}
static inline u32 XPU_REG_BSSID_FILTER_HIGH_read(void){
return reg_read(XPU_REG_BSSID_FILTER_HIGH_ADDR);
}
static inline void XPU_REG_BAND_CHANNEL_write(u32 Data) {
reg_write(XPU_REG_BAND_CHANNEL_ADDR, Data);
}
static inline u32 XPU_REG_BAND_CHANNEL_read(void){
return reg_read(XPU_REG_BAND_CHANNEL_ADDR);
}
static inline void XPU_REG_DIFS_ADVANCE_write(u32 Data) {
reg_write(XPU_REG_DIFS_ADVANCE_ADDR, Data);
}
static inline u32 XPU_REG_DIFS_ADVANCE_read(void){
return reg_read(XPU_REG_DIFS_ADVANCE_ADDR);
}
static inline void XPU_REG_FORCE_IDLE_MISC_write(u32 Data) {
reg_write(XPU_REG_FORCE_IDLE_MISC_ADDR, Data);
}
static inline u32 XPU_REG_FORCE_IDLE_MISC_read(void){
return reg_read(XPU_REG_FORCE_IDLE_MISC_ADDR);
}
static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){
return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR);
}
static inline u32 XPU_REG_TSF_RUNTIME_VAL_HIGH_read(void){
return reg_read(XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR);
}
static inline void XPU_REG_TSF_LOAD_VAL_LOW_write(u32 value){
reg_write(XPU_REG_TSF_LOAD_VAL_LOW_ADDR, value);
}
static inline void XPU_REG_TSF_LOAD_VAL_HIGH_write(u32 value){
reg_write(XPU_REG_TSF_LOAD_VAL_HIGH_ADDR, value);
}
static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){
XPU_REG_TSF_LOAD_VAL_LOW_write(low_value);
XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value|0x80000000); // msb high
XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low
}
static inline void XPU_REG_LBT_TH_write(u32 value) {
reg_write(XPU_REG_LBT_TH_ADDR, value);
}
static inline u32 XPU_REG_RSSI_DB_CFG_read(void){
return reg_read(XPU_REG_RSSI_DB_CFG_ADDR);
}
static inline void XPU_REG_RSSI_DB_CFG_write(u32 Data) {
reg_write(XPU_REG_RSSI_DB_CFG_ADDR, Data);
}
static inline u32 XPU_REG_LBT_TH_read(void){
return reg_read(XPU_REG_LBT_TH_ADDR);
}
static inline void XPU_REG_CSMA_DEBUG_write(u32 value){
reg_write(XPU_REG_CSMA_DEBUG_ADDR, value);
}
static inline u32 XPU_REG_CSMA_DEBUG_read(void){
return reg_read(XPU_REG_CSMA_DEBUG_ADDR);
}
static inline void XPU_REG_CSMA_CFG_write(u32 value){
reg_write(XPU_REG_CSMA_CFG_ADDR, value);
}
static inline u32 XPU_REG_CSMA_CFG_read(void){
return reg_read(XPU_REG_CSMA_CFG_ADDR);
}
static inline void XPU_REG_SLICE_COUNT_TOTAL_write(u32 value){
reg_write(XPU_REG_SLICE_COUNT_TOTAL_ADDR, value);
}
static inline void XPU_REG_SLICE_COUNT_START_write(u32 value){
reg_write(XPU_REG_SLICE_COUNT_START_ADDR, value);
}
static inline void XPU_REG_SLICE_COUNT_END_write(u32 value){
reg_write(XPU_REG_SLICE_COUNT_END_ADDR, value);
}
static inline u32 XPU_REG_SLICE_COUNT_TOTAL_read(void){
return reg_read(XPU_REG_SLICE_COUNT_TOTAL_ADDR);
}
static inline u32 XPU_REG_SLICE_COUNT_START_read(void){
return reg_read(XPU_REG_SLICE_COUNT_START_ADDR);
}
static inline u32 XPU_REG_SLICE_COUNT_END_read(void){
return reg_read(XPU_REG_SLICE_COUNT_END_ADDR);
}
static inline void XPU_REG_BB_RF_DELAY_write(u32 value){
reg_write(XPU_REG_BB_RF_DELAY_ADDR, value);
}
static inline void XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(u32 value){
reg_write(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR, value);
}
static inline u32 XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read(void){
return reg_read(XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR);
}
static inline void XPU_REG_AMPDU_ACTION_write(u32 Data) {
reg_write(XPU_REG_AMPDU_ACTION_ADDR, Data);
}
static inline u32 XPU_REG_AMPDU_ACTION_read(void){
return reg_read(XPU_REG_AMPDU_ACTION_ADDR);
}
static inline void XPU_REG_SPI_DISABLE_write(u32 Data) {
reg_write(XPU_REG_SPI_DISABLE_ADDR, Data);
}
static inline u32 XPU_REG_SPI_DISABLE_read(void){
return reg_read(XPU_REG_SPI_DISABLE_ADDR);
}
static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){
XPU_REG_MAC_ADDR_LOW_write( *( (u32*)(mac_addr) ) );
XPU_REG_MAC_ADDR_HIGH_write( *( (u16*)(mac_addr + 4) ) );
#if 0
if (en_flag) {
XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) | 0x80000000 ); // 0x80000000 by default we turn on mac addr filter
} else {
XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) & 0x7FFFFFFF );
}
#endif
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,xpu", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct xpu_driver_api xpu_driver_api_inst;
struct xpu_driver_api *xpu_api = &xpu_driver_api_inst;
EXPORT_SYMBOL(xpu_api);
static inline u32 hw_init(enum xpu_mode mode){
int err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay;
// u32 filter_flag = 0;
printk("%s hw_init mode %d\n", xpu_compatible_str, mode);
//rst
for (i=0;i<8;i++)
xpu_api->XPU_REG_MULTI_RST_write(0);
for (i=0;i<32;i++)
xpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF);
for (i=0;i<8;i++)
xpu_api->XPU_REG_MULTI_RST_write(0);
// http://www.studioreti.it/slide/802-11-Frame_E_C.pdf
// https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/
// https://mrncciew.com/2014/09/27/cwap-mac-header-frame-control/
// https://mrncciew.com/2014/10/25/cwap-mac-header-durationid/
// https://mrncciew.com/2014/11/01/cwap-mac-header-sequence-control/
// https://witestlab.poly.edu/blog/802-11-wireless-lan-2/
// phy_rx byte idx:
// 5(3 sig + 2 service), -- PHY
// 2 frame control, 2 duration/conn ID, --MAC PDU
// 6 receiver address, 6 destination address, 6 transmitter address
// 2 sequence control
// 6 source address
// reg_val = 5 + 0;
// xpu_api->XPU_REG_PHY_RX_PKT_READ_OFFSET_write(reg_val);
// printk("%s hw_init XPU_REG_PHY_RX_PKT_READ_OFFSET_write %d\n", xpu_compatible_str, reg_val);
// by default turn off filter, because all register are zeros
// let's filter out packet according to: enum ieee80211_filter_flags at: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html
#if 0 // define in FPGA
localparam [13:0] FIF_ALLMULTI = 14b00000000000010, //get all mac addr like 01:00:5E:xx:xx:xx and 33:33:xx:xx:xx:xx through to ARM
FIF_FCSFAIL = 14b00000000000100, //not support
FIF_PLCPFAIL = 14b00000000001000, //not support
FIF_BCN_PRBRESP_PROMISC= 14b00000000010000,
FIF_CONTROL = 14b00000000100000,
FIF_OTHER_BSS = 14b00000001000000,
FIF_PSPOLL = 14b00000010000000,
FIF_PROBE_REQ = 14b00000100000000,
UNICAST_FOR_US = 14b00001000000000,
BROADCAST_ALL_ONE = 14b00010000000000,
BROADCAST_ALL_ZERO = 14b00100000000000,
MY_BEACON = 14b01000000000000,
MONITOR_ALL = 14b10000000000000;
#endif
// Remove XPU_REG_FILTER_FLAG_write to avoid hw_init call in openwifi_start causing inconsistency
// filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL);
// xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag);
xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB
// after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel
// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"!
// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz
//xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit
// From CMW measurement: lo up 1us before the packet; lo down 0.4us after the packet/RF port switches 1.2us before and 0.2us after
xpu_api->XPU_REG_BB_RF_DELAY_write((16<<24)|(0<<16)|(26<<8)|9); // calibrated by ila and spectrum analyzer (trigger mode)
// setup time schedule of all queues. all time open.
for (i=0; i<4; i++) {
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((i<<20)|16);//total 16us
xpu_api->XPU_REG_SLICE_COUNT_START_write((i<<20)|0); //start 0us
xpu_api->XPU_REG_SLICE_COUNT_END_write((i<<20)|16); //end 16us
}
// all slice sync rest
xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time
xpu_api->XPU_REG_MULTI_RST_write(0<<7);
switch(mode)
{
case XPU_TEST:
printk("%s hw_init mode XPU_TEST\n", xpu_compatible_str);
break;
case XPU_NORMAL:
printk("%s hw_init mode XPU_NORMAL\n", xpu_compatible_str);
break;
default:
printk("%s hw_init mode %d is wrong!\n", xpu_compatible_str, mode);
err=1;
}
// Remove this XPU_REG_BAND_CHANNEL_write in xpu.c, because
// 1. the 44 for channel field is out dated. Now the channel actually should be frequency in MHz
// 2. PROBLEM! this hw_init call in openwifi_start will cause lossing consistency between XPU register and
// (priv->use_short_slot<<24)|(priv->band<<16)|(priv->actual_rx_lo)
// xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot
agc_gain_delay = 39; //samples
rssi_half_db_offset = 75<<1;
xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) );
xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) );
//rssi_half_db_th = 70<<1; // with splitter
rssi_half_db_th = 87<<1; // -62dBm
xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it
// control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals
// (1<<26) to disable eifs_trigger_by_last_tx_fail by default (standard does not ask so)
xpu_api->XPU_REG_FORCE_IDLE_MISC_write((1<<26)|75);
//xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5));
xpu_api->XPU_REG_CSMA_DEBUG_write(0);
// xpu_api->XPU_REG_CSMA_CFG_write(268435459); // Linux will do config for each queue via openwifi_conf_tx
// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); // Linux will do config for each queue via openwifi_conf_tx
// // ------- assume 2.4 and 5GHz have the same SIFS (6us signal extension) --------
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+25+7-3+8-2)<<16)|((16+25+7-3+8-2)<<0) ); //+7 according to the ACK timing check by IQ sample: iq_ack_timing.md. -3 after Colvin LLR. +8 after new faster dac intf. -2 calibration in Oct. 2024
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | (10+3) );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M). +3 after Colvin LLR
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | (10+3) );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M). +3 after Colvin LLR
// // ------- assume 2.4 and 5GHz have different SIFS --------
// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+23)<<16)|(0+23) );
// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
xpu_api->XPU_REG_DIFS_ADVANCE_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|2); //us. bit31~16 max pkt length threshold
printk("%s hw_init err %d\n", xpu_compatible_str, err);
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
u32 test_us0, test_us1, test_us2;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", xpu_compatible_str);
err = 0;
}
}
if (err)
return err;
xpu_api->hw_init=hw_init;
xpu_api->reg_read=reg_read;
xpu_api->reg_write=reg_write;
xpu_api->XPU_REG_MULTI_RST_write=XPU_REG_MULTI_RST_write;
xpu_api->XPU_REG_MULTI_RST_read=XPU_REG_MULTI_RST_read;
xpu_api->XPU_REG_SRC_SEL_write=XPU_REG_SRC_SEL_write;
xpu_api->XPU_REG_SRC_SEL_read=XPU_REG_SRC_SEL_read;
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write=XPU_REG_RECV_ACK_COUNT_TOP0_write;
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_read=XPU_REG_RECV_ACK_COUNT_TOP0_read;
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write=XPU_REG_RECV_ACK_COUNT_TOP1_write;
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_read=XPU_REG_RECV_ACK_COUNT_TOP1_read;
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write=XPU_REG_SEND_ACK_WAIT_TOP_write;
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_read=XPU_REG_SEND_ACK_WAIT_TOP_read;
xpu_api->XPU_REG_MAC_ADDR_LOW_write=XPU_REG_MAC_ADDR_LOW_write;
xpu_api->XPU_REG_MAC_ADDR_LOW_read=XPU_REG_MAC_ADDR_LOW_read;
xpu_api->XPU_REG_MAC_ADDR_HIGH_write=XPU_REG_MAC_ADDR_HIGH_write;
xpu_api->XPU_REG_MAC_ADDR_HIGH_read=XPU_REG_MAC_ADDR_HIGH_read;
xpu_api->XPU_REG_FILTER_FLAG_write=XPU_REG_FILTER_FLAG_write;
xpu_api->XPU_REG_FILTER_FLAG_read=XPU_REG_FILTER_FLAG_read;
xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write=XPU_REG_CTS_TO_RTS_CONFIG_write;
xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_read=XPU_REG_CTS_TO_RTS_CONFIG_read;
xpu_api->XPU_REG_BSSID_FILTER_LOW_write=XPU_REG_BSSID_FILTER_LOW_write;
xpu_api->XPU_REG_BSSID_FILTER_LOW_read=XPU_REG_BSSID_FILTER_LOW_read;
xpu_api->XPU_REG_BSSID_FILTER_HIGH_write=XPU_REG_BSSID_FILTER_HIGH_write;
xpu_api->XPU_REG_BSSID_FILTER_HIGH_read=XPU_REG_BSSID_FILTER_HIGH_read;
xpu_api->XPU_REG_BAND_CHANNEL_write=XPU_REG_BAND_CHANNEL_write;
xpu_api->XPU_REG_BAND_CHANNEL_read=XPU_REG_BAND_CHANNEL_read;
xpu_api->XPU_REG_DIFS_ADVANCE_write=XPU_REG_DIFS_ADVANCE_write;
xpu_api->XPU_REG_DIFS_ADVANCE_read=XPU_REG_DIFS_ADVANCE_read;
xpu_api->XPU_REG_FORCE_IDLE_MISC_write=XPU_REG_FORCE_IDLE_MISC_write;
xpu_api->XPU_REG_FORCE_IDLE_MISC_read=XPU_REG_FORCE_IDLE_MISC_read;
xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read;
xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read;
xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write;
xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write;
xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write;
xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write;
xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read;
xpu_api->XPU_REG_RSSI_DB_CFG_read=XPU_REG_RSSI_DB_CFG_read;
xpu_api->XPU_REG_RSSI_DB_CFG_write=XPU_REG_RSSI_DB_CFG_write;
xpu_api->XPU_REG_CSMA_DEBUG_write=XPU_REG_CSMA_DEBUG_write;
xpu_api->XPU_REG_CSMA_DEBUG_read=XPU_REG_CSMA_DEBUG_read;
xpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write;
xpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read;
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write=XPU_REG_SLICE_COUNT_TOTAL_write;
xpu_api->XPU_REG_SLICE_COUNT_START_write=XPU_REG_SLICE_COUNT_START_write;
xpu_api->XPU_REG_SLICE_COUNT_END_write=XPU_REG_SLICE_COUNT_END_write;
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read=XPU_REG_SLICE_COUNT_TOTAL_read;
xpu_api->XPU_REG_SLICE_COUNT_START_read=XPU_REG_SLICE_COUNT_START_read;
xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read;
xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write;
xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write;
xpu_api->XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read=XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read;
xpu_api->XPU_REG_AMPDU_ACTION_write=XPU_REG_AMPDU_ACTION_write;
xpu_api->XPU_REG_AMPDU_ACTION_read=XPU_REG_AMPDU_ACTION_read;
xpu_api->XPU_REG_SPI_DISABLE_write=XPU_REG_SPI_DISABLE_write;
xpu_api->XPU_REG_SPI_DISABLE_read=XPU_REG_SPI_DISABLE_read;
xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", xpu_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr);
printk("%s dev_probe xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst);
printk("%s dev_probe xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api);
printk("%s dev_probe reset tsf timer\n", xpu_compatible_str);
xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0);
test_us0 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();
mdelay(33);
test_us1 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();
mdelay(67);
test_us2 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();
printk("%s dev_probe XPU_REG_TSF_RUNTIME_VAL_LOW_read %d %d %dus\n", xpu_compatible_str, test_us0, test_us1, test_us2);
printk("%s dev_probe succeed!\n", xpu_compatible_str);
err = hw_init(XPU_NORMAL);
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr);
printk("%s dev_remove xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst);
printk("%s dev_remove xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api);
printk("%s dev_remove succeed!\n", xpu_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,xpu",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,xpu");
MODULE_LICENSE("GPL v2");
================================================
FILE: kernel_boot/10-network-device.rules
================================================
SUBSYSTEM=="net", ACTION=="add", ATTR{address}=="66:55:44:33:22:*", NAME="sdr0"
================================================
FILE: kernel_boot/70-persistent-net.rules
================================================
SUBSYSTEM=="net", ACTION=="add", DRIVERS=="?*", ATTR{address}=="66:55:44:33:22:*", ATTR{dev_id}=="0x0", ATTR{type}=="1", KERNEL=="wlan*", NAME="sdr0"
================================================
FILE: kernel_boot/ad9361.patch
================================================
diff --git a/drivers/iio/adc/ad9361.c b/drivers/iio/adc/ad9361.c
index 91f166675024..8403edc6f482 100644
--- a/drivers/iio/adc/ad9361.c
+++ b/drivers/iio/adc/ad9361.c
@@ -1234,7 +1234,7 @@ static int ad9361_load_mixer_gm_subtable(struct ad9361_rf_phy *phy)
return 0;
}
-static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
+int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
bool tx1, bool tx2, bool immed)
{
u8 buf[2];
@@ -1266,8 +1266,9 @@ static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
return ret;
}
+EXPORT_SYMBOL(ad9361_set_tx_atten);
-static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)
+int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)
{
u8 buf[2];
int ret = 0;
@@ -1285,6 +1286,7 @@ static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)
return code;
}
+EXPORT_SYMBOL(ad9361_get_tx_atten);
int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state)
{
@@ -3449,6 +3451,8 @@ static int ad9361_gc_setup(struct ad9361_rf_phy *phy, struct gain_control *ctrl)
AGCLL_MAX_INCREASE(~0), reg);
/* Fast AGC - Peak Detectors and Final Settling */
+ ad9361_spi_writef(spi, REG_AGC_LOCK_LEVEL, ENABLE_DIG_SAT_OVRG, ctrl->f_agc_dig_sat_ovrg_en);
+
reg = ctrl->f_agc_lpf_final_settling_steps;
reg = clamp_t(u32, reg, 0U, 3U);
ad9361_spi_writef(spi, REG_FAST_ENERGY_LOST_THRESH,
@@ -3744,7 +3748,7 @@ static int ad9361_get_auxadc(struct ad9361_rf_phy *phy)
// Setup Control Outs
//************************************************************
-static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
+int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
struct ctrl_outs_control *ctrl)
{
struct spi_device *spi = phy->spi;
@@ -3754,6 +3758,7 @@ static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
ad9361_spi_write(spi, REG_CTRL_OUTPUT_POINTER, ctrl->index); // Ctrl Out index
return ad9361_spi_write(spi, REG_CTRL_OUTPUT_ENABLE, ctrl->en_mask); // Ctrl Out [7:0] output enable
}
+EXPORT_SYMBOL(ad9361_ctrl_outs_setup);
//************************************************************
// Setup GPO
//************************************************************
@@ -5252,7 +5257,7 @@ static int ad9361_setup(struct ad9361_rf_phy *phy)
}
-static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
+int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
{
struct ad9361_rf_phy_state *st = phy->state;
int ret;
@@ -5285,6 +5290,7 @@ static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
return ret;
}
+EXPORT_SYMBOL(ad9361_do_calib_run);
static int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,
u32 rf_rx_bw, u32 rf_tx_bw)
@@ -8906,6 +8912,8 @@ static struct ad9361_phy_platform_data
ad9361_of_get_u32(iodev, np, "adi,fagc-lock-level-gain-increase-upper-limit", 5,
&pdata->gain_ctrl.f_agc_lock_level_gain_increase_upper_limit); /* 0x118 0..63 */
/* Fast AGC - Peak Detectors and Final Settling */
+ ad9361_of_get_bool(iodev, np, "adi,fagc-dig-sat-ovrg-enable",
+ &pdata->gain_ctrl.f_agc_dig_sat_ovrg_en); /* 0x101:7 (full table) */
ad9361_of_get_u32(iodev, np, "adi,fagc-lpf-final-settling-steps", 1,
&pdata->gain_ctrl.f_agc_lpf_final_settling_steps); /* 0x112:6 0..3 (Post Lock Level Step)*/
ad9361_of_get_u32(iodev, np, "adi,fagc-lmt-final-settling-steps", 1,
================================================
FILE: kernel_boot/ad9361_conv.patch
================================================
diff --git a/drivers/iio/adc/ad9361_conv.c b/drivers/iio/adc/ad9361_conv.c
index 1902e7d07501..ef421dbd5e70 100644
--- a/drivers/iio/adc/ad9361_conv.c
+++ b/drivers/iio/adc/ad9361_conv.c
@@ -449,7 +449,8 @@ static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy,
unsigned long max_freq,
enum dig_tune_flags flags, bool tx)
{
- static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};
+ // static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};
+ static const unsigned int rates[3] = {25000000U, 40000000U, 40000000U};
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
unsigned int s0, s1, c0, c1;
unsigned int i, j, r;
================================================
FILE: kernel_boot/ad9361_private.patch
================================================
diff --git a/drivers/iio/adc/ad9361_private.h b/drivers/iio/adc/ad9361_private.h
index dfffc4fa88a9..99dadf844614 100644
--- a/drivers/iio/adc/ad9361_private.h
+++ b/drivers/iio/adc/ad9361_private.h
@@ -127,6 +127,7 @@ struct gain_control {
u8 f_agc_lp_thresh_increment_steps; /* 0x117 1..8 */
/* Fast AGC - Lock Level */
+ bool f_agc_dig_sat_ovrg_en; /* 0x101:7 Enable digital saturation cause gain decrease */
u8 f_agc_lock_level; /* NOT USED: 0x101 0..-127 dBFS same as agc_inner_thresh_high */
bool f_agc_lock_level_lmt_gain_increase_en; /* 0x111:6 */
u8 f_agc_lock_level_gain_increase_upper_limit; /* 0x118 0..63 */
================================================
FILE: kernel_boot/axi_hdmi_crtc.patch
================================================
diff --git a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c
index e8241767b9f9..37809fc10bde 100644
--- a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c
+++ b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c
@@ -54,7 +54,7 @@ static struct dma_async_tx_descriptor *axi_hdmi_vdma_prep_interleaved_desc(
memset(&vdma_config, 0, sizeof(vdma_config));
vdma_config.park = 1;
vdma_config.coalesc = 0xff;
- xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config);
+ // xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config);
}
#endif
================================================
FILE: kernel_boot/boards/adrv9361z7035/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x1>;
model = "Analog Devices ADRV9361-Z7035 (Z7035/AD9361)";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <0x2 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <0x3>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <0x2 0x3>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x4>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <0x1>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <0x3>;
phandle = <0x3>;
};
amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x1>;
ranges;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <0x1>;
clocks = <0x2 0xc>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x13 0x2 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x14 0x2 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <0x2 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x26>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x19 0x4>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x27>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x30 0x4>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
linux,phandle = <0x1>;
phandle = <0x1>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x3 0x4>;
reg = <0xf800c000 0x1000>;
};
serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <0x2 0x17 0x2 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
};
serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x2 0x18 0x2 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x1a 0x4>;
clocks = <0x2 0x19 0x2 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5 0x0>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x62 0x0>;
sync-gpios = <0x6 0x63 0x0>;
reset-gpios = <0x6 0x64 0x0>;
enable-gpios = <0x6 0x65 0x0>;
txnrx-gpios = <0x6 0x66 0x0>;
linux,phandle = <0xc>;
phandle = <0xc>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x1>;
interrupts = <0x0 0x31 0x4>;
clocks = <0x2 0x1a 0x2 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <0x2 0xa 0x2 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
is-dual = <0x0>;
num-cs = <0x1>;
ps7-qspi@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
spi-tx-bus-width = <0x1>;
spi-rx-bus-width = <0x4>;
compatible = "n25q256a", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <0x2faf080>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x0 0xe0000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0xe0000 0x20000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
label = "qspi-rootfs";
reg = <0x620000 0xce0000>;
};
partition@qspi-bitstream {
label = "qspi-bitstream";
reg = <0x1300000 0xd00000>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "disabled";
clock-names = "memclk", "aclk";
clocks = <0x2 0xb 0x2 0x2c>;
compatible = "arm,pl353-smc-r2p1";
interrupt-parent = <0x1>;
interrupts = <0x0 0x12 0x4>;
ranges;
reg = <0xe000e000 0x1000>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <0x7>;
phy-mode = "rgmii-id";
phy@0 {
device_type = "ethernet-phy";
reg = <0x0>;
marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;
linux,phandle = <0x7>;
phandle = <0x7>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x0 0x2d 0x4>;
clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x15 0x2 0x20>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
disable-wp;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x16 0x2 0x21>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
linux,phandle = <0x8>;
phandle = <0x8>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <0x8>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x8>;
};
};
dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x1>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x4>;
clocks = <0x2 0x1b>;
clock-names = "apb_pclk";
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x8 0x4>;
reg = <0xf8007000 0x100>;
clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <0x8>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <0x1>;
clocks = <0x2 0x4>;
};
timer@f8001000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8001000 0x1000>;
};
timer@f8002000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8002000 0x1000>;
};
timer@f8f00600 {
interrupt-parent = <0x1>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x2 0x4>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "okay";
clocks = <0x2 0x1c>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x2 0x1d>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog@f8005000 {
clocks = <0x2 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x1>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
};
aliases {
ethernet0 = "/amba/ethernet@e000b000";
serial0 = "/amba/serial@e0001000";
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
linux,stdout-path = "/amba@0/uart@E0001000";
};
clocks {
clock@0 {
#clock-cells = <0x0>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "XO_40MHz";
linux,phandle = <0x9>;
phandle = <0x9>;
};
clock@2 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "24MHz";
linux,phandle = <0xa>;
phandle = <0xa>;
};
};
ad9361-refclk-gpio-gate@0 {
#clock-cells = <0x0>;
compatible = "gpio-gate-clock";
clocks = <0x9>;
enable-gpios = <0x6 0x69 0x0>;
clk-set-rate-parent-enable;
clock-output-names = "ad9361_ext_refclk";
linux,phandle = <0x5>;
phandle = <0x5>;
};
usb-ulpe-gpio-gate@0 {
#clock-cells = <0x0>;
compatible = "gpio-gate-clock";
clocks = <0xa>;
enable-gpios = <0x6 0x9 0x1>;
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x3a 0x4>;
clocks = <0x2 0xf>;
clock-names = "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
adm1166@68 {
compatible = "adi,adm1166";
reg = <0x68>;
};
ad7291-bob@2f {
compatible = "adi,ad7291";
reg = <0x2f>;
};
eeprom@50 {
compatible = "at24,24c32";
reg = <0x50>;
};
};
// dma@7c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c400000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x39 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xb>;
// phandle = <0xb>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x2>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x0>;
// };
// };
// };
// dma@7c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c420000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x38 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xd>;
// phandle = <0xd>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x0>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x2>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0xb 0x0>;
// dma-names = "rx";
spibus-connected = <0xc>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0xc 0xd>;
clock-names = "sampl_clk";
// dmas = <0xd 0x0>;
// dma-names = "tx";
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
/*axi-sysid-0@45000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x45000000 0x10000>;
};*/
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0:green";
gpios = <0x6 0x3a 0x0>;
};
led1 {
label = "led1:green";
gpios = <0x6 0x3b 0x0>;
};
led2 {
label = "led2:green";
gpios = <0x6 0x3c 0x0>;
};
led3 {
label = "led3:green";
gpios = <0x6 0x3d 0x0>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <0x1>;
#size-cells = <0x0>;
autorepeat;
pb0 {
label = "Left";
linux,code = <0x69>;
gpios = <0x6 0x36 0x0>;
};
pb1 {
label = "Right";
linux,code = <0x6a>;
gpios = <0x6 0x37 0x0>;
};
pb2 {
label = "Up";
linux,code = <0x67>;
gpios = <0x6 0x38 0x0>;
};
pb3 {
label = "Down";
linux,code = <0x6c>;
gpios = <0x6 0x39 0x0>;
};
sw0 {
label = "SW0";
linux,input-type = <0x5>;
linux,code = <0x0>;
gpios = <0x6 0x3e 0x0>;
};
sw1 {
label = "SW1";
linux,input-type = <0x5>;
linux,code = <0x1>;
gpios = <0x6 0x3f 0x0>;
};
sw2 {
label = "SW2";
linux,input-type = <0x5>;
linux,code = <0x2>;
gpios = <0x6 0x40 0x0>;
};
sw3 {
label = "SW3";
linux,input-type = <0x5>;
linux,code = <0x3>;
gpios = <0x6 0x41 0x0>;
};
};
};
================================================
FILE: kernel_boot/boards/adrv9361z7035_fmc/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x1>;
model = "Analog Devices ADRV9361-Z7035 (Z7035/AD9361)";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <0x2 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <0x3>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <0x2 0x3>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x4>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <0x1>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <0x3>;
phandle = <0x3>;
};
amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x1>;
ranges;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <0x1>;
clocks = <0x2 0xc>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x13 0x2 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x14 0x2 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <0x2 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x26>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x19 0x4>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x27>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x30 0x4>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
linux,phandle = <0x1>;
phandle = <0x1>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x3 0x4>;
reg = <0xf800c000 0x1000>;
};
serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <0x2 0x17 0x2 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
};
serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x2 0x18 0x2 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x1a 0x4>;
clocks = <0x2 0x19 0x2 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5 0x0>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x62 0x0>;
sync-gpios = <0x6 0x63 0x0>;
reset-gpios = <0x6 0x64 0x0>;
enable-gpios = <0x6 0x65 0x0>;
txnrx-gpios = <0x6 0x66 0x0>;
linux,phandle = <0x10>;
phandle = <0x10>;
};
ad9517@1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9517-3";
reg = <0x1>;
spi-max-frequency = <0x989680>;
clocks = <0x7 0x7>;
clock-names = "refclk", "clkin";
clock-output-names = "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7";
firmware = "pzsdr-fmc-ad9517.stp";
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x1>;
interrupts = <0x0 0x31 0x4>;
clocks = <0x2 0x1a 0x2 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <0x2 0xa 0x2 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
is-dual = <0x0>;
num-cs = <0x1>;
ps7-qspi@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
spi-tx-bus-width = <0x1>;
spi-rx-bus-width = <0x4>;
compatible = "n25q256a", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <0x2faf080>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x0 0xe0000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0xe0000 0x20000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
label = "qspi-rootfs";
reg = <0x620000 0xce0000>;
};
partition@qspi-bitstream {
label = "qspi-bitstream";
reg = <0x1300000 0xd00000>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "disabled";
clock-names = "memclk", "aclk";
clocks = <0x2 0xb 0x2 0x2c>;
compatible = "arm,pl353-smc-r2p1";
interrupt-parent = <0x1>;
interrupts = <0x0 0x12 0x4>;
ranges;
reg = <0xe000e000 0x1000>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <0x8>;
phy-mode = "rgmii-id";
phy@0 {
device_type = "ethernet-phy";
reg = <0x0>;
marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;
linux,phandle = <0x8>;
phandle = <0x8>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "okay";
interrupts = <0x0 0x2d 0x4>;
clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <0x9>;
phy-mode = "gmii";
phy@1 {
device_type = "ethernet-phy";
reg = <0x1>;
marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;
linux,phandle = <0x9>;
phandle = <0x9>;
};
gmiitorgmii@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
reg = <0x8>;
phy-handle = <0x9>;
};
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x15 0x2 0x20>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
disable-wp;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x16 0x2 0x21>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
linux,phandle = <0xa>;
phandle = <0xa>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <0xa>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0xa>;
};
};
dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x1>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x4>;
clocks = <0x2 0x1b>;
clock-names = "apb_pclk";
linux,phandle = <0x15>;
phandle = <0x15>;
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x8 0x4>;
reg = <0xf8007000 0x100>;
clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <0xa>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <0x1>;
clocks = <0x2 0x4>;
};
timer@f8001000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8001000 0x1000>;
};
timer@f8002000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8002000 0x1000>;
};
timer@f8f00600 {
interrupt-parent = <0x1>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x2 0x4>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "okay";
clocks = <0x2 0x1c>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x2 0x1d>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog@f8005000 {
clocks = <0x2 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x1>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
};
aliases {
ethernet0 = "/amba/ethernet@e000b000";
serial0 = "/amba/serial@e0001000";
ethernet1 = "/amba/ethernet@e000c000";
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
linux,stdout-path = "/amba@0/uart@E0001000";
};
clocks {
clock@0 {
#clock-cells = <0x0>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "XO_40MHz";
linux,phandle = <0xb>;
phandle = <0xb>;
};
clock@2 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "24MHz";
linux,phandle = <0xc>;
phandle = <0xc>;
};
clock@3 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x17d7840>;
clock-output-names = "ad9517_refclk";
linux,phandle = <0x7>;
phandle = <0x7>;
};
audio_clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0xbb8000>;
linux,phandle = <0xe>;
phandle = <0xe>;
};
};
ad9361-refclk-gpio-gate@0 {
#clock-cells = <0x0>;
compatible = "gpio-gate-clock";
clocks = <0xb>;
enable-gpios = <0x6 0x69 0x0>;
clk-set-rate-parent-enable;
clock-output-names = "ad9361_ext_refclk";
linux,phandle = <0x5>;
phandle = <0x5>;
};
usb-ulpe-gpio-gate@0 {
#clock-cells = <0x0>;
compatible = "gpio-gate-clock";
clocks = <0xc>;
enable-gpios = <0x6 0x9 0x1>;
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x3a 0x4>;
clocks = <0x2 0xf>;
clock-names = "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
adm1166@68 {
compatible = "adi,adm1166";
reg = <0x68>;
};
i2cswitch@74 {
compatible = "nxp,pca9548";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x70>;
i2c@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x0>;
};
i2c@1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x1>;
};
i2c@2 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x2>;
adv7511@39 {
compatible = "adi,adv7511";
reg = <0x39 0x3f>;
reg-names = "primary", "edid";
adi,input-depth = <0x8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <0x1>;
adi,input-justification = "left";
adi,clock-delay = <0x0>;
#sound-dai-cells = <0x0>;
linux,phandle = <0x17>;
phandle = <0x17>;
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xd>;
linux,phandle = <0x14>;
phandle = <0x14>;
};
};
port@1 {
reg = <0x1>;
};
};
};
};
i2c@3 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x3>;
adau1761@3b {
compatible = "adi,adau1761";
reg = <0x3b>;
clocks = <0xe>;
clock-names = "mclk";
#sound-dai-cells = <0x0>;
linux,phandle = <0x19>;
phandle = <0x19>;
};
};
i2c@4 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x4>;
};
i2c@5 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x5>;
eeprom@50 {
compatible = "at24,24c32";
reg = <0x50>;
};
};
i2c@6 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x6>;
ad7291@2f {
compatible = "adi,ad7291";
reg = <0x2f>;
};
};
i2c@7 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x7>;
};
};
};
dma@7c400000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c400000 0x10000>;
#dma-cells = <0x1>;
interrupts = <0x0 0x39 0x0>;
clocks = <0x2 0x10>;
linux,phandle = <0xf>;
phandle = <0xf>;
adi,channels {
#size-cells = <0x0>;
#address-cells = <0x1>;
dma-channel@0 {
reg = <0x0>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x2>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x0>;
};
};
};
dma@7c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c420000 0x10000>;
#dma-cells = <0x1>;
interrupts = <0x0 0x38 0x0>;
clocks = <0x2 0x10>;
linux,phandle = <0x11>;
phandle = <0x11>;
adi,channels {
#size-cells = <0x0>;
#address-cells = <0x1>;
dma-channel@0 {
reg = <0x0>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x0>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x2>;
};
};
};
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 0
&rx_dma 1
&tx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "rx_dma_s2mm", "tx_dma_mm2s", "tx_dma_s2mm";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt0", "tx_itrpt1";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk", "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt0", "tx_itrpt1";
interrupt-parent = <1>;
interrupts = <0 33 1 0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
dmas = <0xf 0x0>;
dma-names = "rx";
spibus-connected = <0x10>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0x10 0xd>;
clock-names = "sampl_clk";
dmas = <0x11 0x0>;
dma-names = "tx";
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
/*axi-sysid-0@45000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x45000000 0x10000>;
};*/
dma@43000000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43000000 0x10000>;
#dma-cells = <0x1>;
interrupts = <0x0 0x3b 0x0>;
clocks = <0x2 0x10>;
linux,phandle = <0x12>;
phandle = <0x12>;
adi,channels {
#size-cells = <0x0>;
#address-cells = <0x1>;
dma-channel@0 {
reg = <0x0>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x0>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x1>;
};
};
};
axi-clkgen@79000000 {
compatible = "adi,axi-clkgen-2.00.a";
reg = <0x79000000 0x10000>;
#clock-cells = <0x0>;
clocks = <0x2 0x10>;
linux,phandle = <0x13>;
phandle = <0x13>;
};
axi_hdmi@70e00000 {
compatible = "adi,axi-hdmi-tx-1.00.a";
reg = <0x70e00000 0x10000>;
dmas = <0x12 0x0>;
dma-names = "video";
clocks = <0x13>;
port {
endpoint {
remote-endpoint = <0x14>;
linux,phandle = <0xd>;
phandle = <0xd>;
};
};
};
axi-spdif-tx@75c00000 {
compatible = "adi,axi-spdif-tx-1.00.a";
reg = <0x75c00000 0x1000>;
dmas = <0x15 0x0>;
dma-names = "tx";
clocks = <0x2 0xf 0xe>;
clock-names = "axi", "ref";
#sound-dai-cells = <0x0>;
linux,phandle = <0x16>;
phandle = <0x16>;
};
axi-i2s@77600000 {
compatible = "adi,axi-i2s-1.00.a";
reg = <0x77600000 0x1000>;
dmas = <0x15 0x1 0x15 0x2>;
dma-names = "tx", "rx";
clocks = <0x2 0xf 0xe>;
clock-names = "axi", "ref";
#sound-dai-cells = <0x0>;
linux,phandle = <0x18>;
phandle = <0x18>;
};
};
adv7511_hdmi_snd {
compatible = "simple-audio-card";
simple-audio-card,name = "HDMI monitor";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing = "Speaker", "TX";
simple-audio-card,dai-link@0 {
format = "spdif";
cpu {
sound-dai = <0x16>;
frame-master;
bitclock-master;
};
codec {
sound-dai = <0x17>;
};
};
};
zed_sound {
compatible = "simple-audio-card";
simple-audio-card,name = "ZED ADAU1761";
simple-audio-card,widgets = "Microphone", "Mic In", "Headphone", "Headphone Out", "Line", "Line In", "Line", "Line Out";
simple-audio-card,routing = "Line Out", "LOUT", "Line Out", "ROUT", "Headphone Out", "LHP", "Headphone Out", "RHP", "Mic In", "MICBIAS", "LINN", "Mic In", "RINN", "Mic In", "LAUX", "Line In", "RAUX", "Line In";
simple-audio-card,dai-link@0 {
format = "i2s";
cpu {
sound-dai = <0x18>;
frame-master;
bitclock-master;
};
codec {
sound-dai = <0x19>;
};
};
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0:red";
gpios = <0x6 0x3d 0x0>;
};
led1 {
label = "led1:red";
gpios = <0x6 0x3b 0x0>;
};
led2 {
label = "led2:red";
gpios = <0x6 0x3a 0x0>;
};
led3 {
label = "led3:red";
gpios = <0x6 0x3c 0x0>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <0x1>;
#size-cells = <0x0>;
autorepeat;
bt0 {
label = "BT0";
linux,code = <0x69>;
gpios = <0x6 0x36 0x0>;
};
bt1 {
label = "BT1";
linux,code = <0x6a>;
gpios = <0x6 0x37 0x0>;
};
bt2 {
label = "BT2";
linux,code = <0x1c>;
gpios = <0x6 0x38 0x0>;
};
bt3 {
label = "BT3";
linux,code = <0x1>;
gpios = <0x6 0x39 0x0>;
};
sw0 {
label = "SW0";
linux,input-type = <0x5>;
linux,code = <0x0>;
gpios = <0x6 0x41 0x0>;
};
sw1 {
label = "SW1";
linux,input-type = <0x5>;
linux,code = <0x1>;
gpios = <0x6 0x3e 0x0>;
};
sw2 {
label = "SW2";
linux,input-type = <0x5>;
linux,code = <0x2>;
gpios = <0x6 0x40 0x0>;
};
sw3 {
label = "SW3";
linux,input-type = <0x5>;
linux,code = <0x3>;
gpios = <0x6 0x3f 0x0>;
};
};
};
================================================
FILE: kernel_boot/boards/adrv9364z7020/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x01>;
model = "Analog Devices ADRV9364-Z7020 (Z7020/AD9364)";
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x00>;
clocks = <0x02 0x03>;
clock-latency = <0x3e8>;
cpu0-supply = <0x03>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
phandle = <0x11>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x01>;
clocks = <0x02 0x03>;
phandle = <0x13>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x04>;
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
phandle = <0x19>;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;
interrupt-parent = <0x01>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
phandle = <0x03>;
};
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
out-ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x05>;
phandle = <0x0d>;
};
};
port@1 {
reg = <0x01>;
endpoint {
remote-endpoint = <0x06>;
phandle = <0x0c>;
};
};
};
in-ports {
port {
endpoint {
remote-endpoint = <0x07>;
phandle = <0x0e>;
};
};
};
};
axi {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x01>;
interrupt-parent = <0x01>;
ranges;
phandle = <0x1a>;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x00 0x07 0x04>;
interrupt-parent = <0x01>;
clocks = <0x02 0x0c>;
phandle = <0x1b>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x02 0x13 0x02 0x24>;
clock-names = "can_clk\0pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x00 0x1c 0x04>;
interrupt-parent = <0x01>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
phandle = <0x1c>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x02 0x14 0x02 0x25>;
clock-names = "can_clk\0pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x00 0x33 0x04>;
interrupt-parent = <0x01>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
phandle = <0x1d>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x02>;
clocks = <0x02 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x02>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x14 0x04>;
reg = <0xe000a000 0x1000>;
phandle = <0x09>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x02 0x26>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x19 0x04>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x1e>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x02 0x27>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x30 0x04>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x1f>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x03>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
phandle = <0x01>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x00 0x02 0x04>;
arm,data-latency = <0x03 0x02 0x02>;
arm,tag-latency = <0x02 0x02 0x02>;
cache-unified;
cache-level = <0x02>;
phandle = <0x20>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
phandle = <0x21>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x01>;
interrupts = <0x00 0x03 0x04>;
reg = <0xf800c000 0x1000>;
phandle = <0x22>;
};
serial@e0000000 {
compatible = "xlnx,xuartps\0cdns,uart-r1p8";
status = "disabled";
clocks = <0x02 0x17 0x02 0x28>;
clock-names = "uart_clk\0pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x00 0x1b 0x04>;
phandle = <0x23>;
};
serial@e0001000 {
compatible = "xlnx,xuartps\0cdns,uart-r1p8";
status = "okay";
clocks = <0x02 0x18 0x02 0x29>;
clock-names = "uart_clk\0pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x00 0x32 0x04>;
phandle = <0x24>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x01>;
interrupts = <0x00 0x1a 0x04>;
clocks = <0x02 0x19 0x02 0x22>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x25>;
ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x08 0x00>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x09 0x62 0x0>;
sync-gpios = <0x09 0x63 0x0>;
reset-gpios = <0x09 0x64 0x0>;
enable-gpios = <0x09 0x65 0x0>;
txnrx-gpios = <0x09 0x66 0x0>;
phandle = <0x17>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x01>;
interrupts = <0x00 0x31 0x04>;
clocks = <0x02 0x1a 0x02 0x23>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x26>;
};
spi@e000d000 {
clock-names = "ref_clk\0pclk";
clocks = <0x02 0x0a 0x02 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x01>;
interrupts = <0x00 0x13 0x04>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
is-dual = <0x00>;
num-cs = <0x01>;
phandle = <0x27>;
ps7-qspi@0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
spi-tx-bus-width = <0x01>;
spi-rx-bus-width = <0x04>;
compatible = "n25q256a\0jedec,spi-nor";
reg = <0x00>;
spi-max-frequency = <0x2faf080>;
phandle = <0x28>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x00 0xe0000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0xe0000 0x20000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
label = "qspi-rootfs";
reg = <0x620000 0xce0000>;
};
partition@qspi-bitstream {
label = "qspi-bitstream";
reg = <0x1300000 0xd00000>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
status = "disabled";
clock-names = "memclk\0apb_pclk";
clocks = <0x02 0x0b 0x02 0x2c>;
compatible = "arm,pl353-smc-r2p1\0arm,primecell";
interrupt-parent = <0x01>;
interrupts = <0x00 0x12 0x04>;
ranges;
reg = <0xe000e000 0x1000>;
phandle = <0x29>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x2a>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x2b>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem\0cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x00 0x16 0x04>;
clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>;
clock-names = "pclk\0hclk\0tx_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phy-handle = <0x0a>;
phy-mode = "rgmii-id";
phandle = <0x2c>;
phy@0 {
device_type = "ethernet-phy";
reg = <0x00>;
marvell,reg-init = <0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00>;
phandle = <0x0a>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem\0cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x00 0x2d 0x04>;
clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>;
clock-names = "pclk\0hclk\0tx_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x2d>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin\0clk_ahb";
clocks = <0x02 0x15 0x02 0x20>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x18 0x04>;
reg = <0xe0100000 0x1000>;
disable-wp;
phandle = <0x2e>;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin\0clk_ahb";
clocks = <0x02 0x16 0x02 0x21>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2f 0x04>;
reg = <0xe0101000 0x1000>;
phandle = <0x2f>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
phandle = <0x0b>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x01>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0x0f>;
clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
phandle = <0x02>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x01>;
syscon = <0x0b>;
phandle = <0x30>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x0b>;
phandle = <0x31>;
};
};
dmac@f8003000 {
compatible = "arm,pl330\0arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x01>;
interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7";
interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;
#dma-cells = <0x01>;
#dma-channels = <0x08>;
#dma-requests = <0x04>;
clocks = <0x02 0x1b>;
clock-names = "apb_pclk";
phandle = <0x32>;
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x01>;
interrupts = <0x00 0x08 0x04>;
reg = <0xf8007000 0x100>;
clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>;
clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3";
syscon = <0x0b>;
phandle = <0x04>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
phandle = <0x33>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x01 0x0b 0x301>;
interrupt-parent = <0x01>;
clocks = <0x02 0x04>;
phandle = <0x34>;
};
timer@f8001000 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;
compatible = "cdns,ttc";
clocks = <0x02 0x06>;
reg = <0xf8001000 0x1000>;
phandle = <0x35>;
};
timer@f8002000 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;
compatible = "cdns,ttc";
clocks = <0x02 0x06>;
reg = <0xf8002000 0x1000>;
phandle = <0x36>;
};
timer@f8f00600 {
interrupt-parent = <0x01>;
interrupts = <0x01 0x0d 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x02 0x04>;
phandle = <0x37>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
status = "okay";
clocks = <0x02 0x1c>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x15 0x04>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x09 0x07 0x00>;
phandle = <0x38>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
status = "disabled";
clocks = <0x02 0x1d>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2c 0x04>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
phandle = <0x39>;
};
watchdog@f8005000 {
clocks = <0x02 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x01>;
interrupts = <0x00 0x09 0x01>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0x0a>;
phandle = <0x3a>;
};
etb@f8801000 {
compatible = "arm,coresight-etb10\0arm,primecell";
reg = <0xf8801000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
in-ports {
port {
endpoint {
remote-endpoint = <0x0c>;
phandle = <0x06>;
};
};
};
};
tpiu@f8803000 {
compatible = "arm,coresight-tpiu\0arm,primecell";
reg = <0xf8803000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
in-ports {
port {
endpoint {
remote-endpoint = <0x0d>;
phandle = <0x05>;
};
};
};
};
funnel@f8804000 {
compatible = "arm,coresight-static-funnel\0arm,primecell";
reg = <0xf8804000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
out-ports {
port {
endpoint {
remote-endpoint = <0x0e>;
phandle = <0x07>;
};
};
};
in-ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x0f>;
phandle = <0x12>;
};
};
port@1 {
reg = <0x01>;
endpoint {
remote-endpoint = <0x10>;
phandle = <0x14>;
};
};
port@2 {
reg = <0x02>;
endpoint {
phandle = <0x3b>;
};
};
};
};
ptm@f889c000 {
compatible = "arm,coresight-etm3x\0arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
cpu = <0x11>;
out-ports {
port {
endpoint {
remote-endpoint = <0x12>;
phandle = <0x0f>;
};
};
};
};
ptm@f889d000 {
compatible = "arm,coresight-etm3x\0arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
cpu = <0x13>;
out-ports {
port {
endpoint {
remote-endpoint = <0x14>;
phandle = <0x10>;
};
};
};
};
};
aliases {
ethernet0 = "/axi/ethernet@e000b000";
serial0 = "/axi/serial@e0001000";
phandle = <0x3c>;
};
memory {
device_type = "memory";
reg = <0x00 0x40000000>;
};
chosen {
stdout-path = "/amba@0/uart@E0001000";
};
clocks {
clock@0 {
#clock-cells = <0x00>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "ad9364_ext_refclk";
phandle = <0x08>;
};
clock@1 {
#clock-cells = <0x00>;
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "24MHz";
phandle = <0x15>;
};
};
usb-ulpi-gpio-gate@0 {
compatible = "gpio-gate-clock";
clocks = <0x15>;
#clock-cells = <0x00>;
enable-gpios = <0x09 0x09 0x01>;
phandle = <0x3d>;
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
phandle = <0x3e>;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x3a 0x04>;
clocks = <0x02 0x0f>;
clock-names = "pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x3f>;
ad7291@20 {
compatible = "adi,ad7291";
reg = <0x20>;
};
ad7291-bob@2C {
compatible = "adi,ad7291";
reg = <0x2c>;
};
eeprom@50 {
compatible = "at24,24c32";
reg = <0x50>;
};
};
// dma@7c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c400000 0x10000>;
// #dma-cells = <0x01>;
// interrupts = <0x00 0x39 0x04>;
// clocks = <0x02 0x10>;
// phandle = <0x16>;
// adi,channels {
// #size-cells = <0x00>;
// #address-cells = <0x01>;
// dma-channel@0 {
// reg = <0x00>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x02>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x00>;
// };
// };
// };
// dma@7c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c420000 0x10000>;
// #dma-cells = <0x01>;
// interrupts = <0x00 0x38 0x04>;
// clocks = <0x02 0x10>;
// phandle = <0x18>;
// adi,channels {
// #size-cells = <0x00>;
// #address-cells = <0x01>;
// dma-channel@0 {
// reg = <0x00>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x00>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x02>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
// axidmatest_1: axidmatest@1 {
// compatible ="xlnx,axi-dma-test-1.00.a";
// dmas = <&rx_dma 0
// &rx_dma 1>;
// dma-names = "axidma0", "axidma1";
// } ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0x16 0x00>;
// dma-names = "rx";
spibus-connected = <0x17>;
phandle = <0x40>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0x17 0x0d>;
clock-names = "sampl_clk";
// dmas = <0x18 0x00>;
// dma-names = "tx";
phandle = <0x41>;
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
// axi-sysid-0@45000000 {
// compatible = "adi,axi-sysid-1.00.a";
// reg = <0x45000000 0x10000>;
// phandle = <0x42>;
// };
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0:green";
gpios = <0x09 0x3a 0x00>;
};
led1 {
label = "led1:green";
gpios = <0x09 0x3b 0x00>;
};
led2 {
label = "led2:green";
gpios = <0x09 0x3c 0x00>;
};
led3 {
label = "led3:green";
gpios = <0x09 0x3d 0x00>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <0x01>;
#size-cells = <0x00>;
autorepeat;
pb0 {
label = "Left";
linux,code = <0x69>;
gpios = <0x09 0x36 0x00>;
};
pb1 {
label = "Right";
linux,code = <0x6a>;
gpios = <0x09 0x37 0x00>;
};
pb2 {
label = "Up";
linux,code = <0x67>;
gpios = <0x09 0x38 0x00>;
};
pb3 {
label = "Down";
linux,code = <0x6c>;
gpios = <0x09 0x39 0x00>;
};
sw0 {
label = "SW0";
linux,input-type = <0x05>;
linux,code = <0x0d>;
gpios = <0x09 0x3e 0x00>;
};
sw1 {
label = "SW1";
linux,input-type = <0x05>;
linux,code = <0x01>;
gpios = <0x09 0x3f 0x00>;
};
sw2 {
label = "SW2";
linux,input-type = <0x05>;
linux,code = <0x02>;
gpios = <0x09 0x40 0x00>;
};
sw3 {
label = "SW3";
linux,input-type = <0x05>;
linux,code = <0x03>;
gpios = <0x09 0x41 0x00>;
};
};
};
================================================
FILE: kernel_boot/boards/antsdr/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x1>;
model = "MicroPhase ANTSDR-E310 (Z7020/AD9361 Z7020/AD9363)";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <0x2 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <0x3>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <0x2 0x3>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x4>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <0x1>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <0x3>;
phandle = <0x3>;
};
amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x1>;
ranges;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <0x1>;
clocks = <0x2 0xc>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x13 0x2 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x14 0x2 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <0x2 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x26>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x19 0x4>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x27>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x30 0x4>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
linux,phandle = <0x1>;
phandle = <0x1>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x3 0x4>;
reg = <0xf800c000 0x1000>;
};
serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <0x2 0x17 0x2 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
};
serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x2 0x18 0x2 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x1a 0x4>;
clocks = <0x2 0x19 0x2 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5 0x0>;
clock-names = "ad9364_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x62 0x0>;
sync-gpios = <0x6 0x63 0x0>;
reset-gpios = <0x6 0x64 0x0>;
enable-gpios = <0x6 0x65 0x0>;
txnrx-gpios = <0x6 0x66 0x0>;
linux,phandle = <0xb>;
phandle = <0xb>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x1>;
interrupts = <0x0 0x31 0x4>;
clocks = <0x2 0x1a 0x2 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <0x2 0xa 0x2 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
is-dual = <0x0>;
num-cs = <0x1>;
ps7-qspi@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
spi-tx-bus-width = <0x1>;
spi-rx-bus-width = <0x4>;
compatible = "n25q256a", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <0x2faf080>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x0 0xe0000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0xe0000 0x20000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
label = "qspi-rootfs";
reg = <0x620000 0xce0000>;
};
partition@qspi-bitstream {
label = "qspi-bitstream";
reg = <0x1300000 0xd00000>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "disabled";
clock-names = "memclk", "aclk";
clocks = <0x2 0xb 0x2 0x2c>;
compatible = "arm,pl353-smc-r2p1";
interrupt-parent = <0x1>;
interrupts = <0x0 0x12 0x4>;
ranges;
reg = <0xe000e000 0x1000>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <0x7>;
phy-mode = "rgmii-id";
phy@0 {
device_type = "ethernet-phy";
reg = <0x0>;
marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;
linux,phandle = <0x7>;
phandle = <0x7>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x0 0x2d 0x4>;
clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x15 0x2 0x20>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
disable-wp;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x16 0x2 0x21>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
linux,phandle = <0x8>;
phandle = <0x8>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <0x8>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x8>;
};
};
dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x1>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x4>;
clocks = <0x2 0x1b>;
clock-names = "apb_pclk";
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x8 0x4>;
reg = <0xf8007000 0x100>;
clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <0x8>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <0x1>;
clocks = <0x2 0x4>;
};
timer@f8001000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8001000 0x1000>;
};
timer@f8002000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8002000 0x1000>;
};
timer@f8f00600 {
interrupt-parent = <0x1>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x2 0x4>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "okay";
clocks = <0x2 0x1c>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x2 0x1d>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog@f8005000 {
clocks = <0x2 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x1>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
};
aliases {
ethernet0 = "/amba/ethernet@e000b000";
serial0 = "/amba/serial@e0001000";
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
linux,stdout-path = "/amba@0/uart@E0001000";
};
clocks {
clock@0 {
#clock-cells = <0x0>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "ad9364_ext_refclk";
linux,phandle = <0x5>;
phandle = <0x5>;
};
clock@1 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "24MHz";
linux,phandle = <0x9>;
phandle = <0x9>;
};
};
usb-ulpi-gpio-gate@0 {
compatible = "gpio-gate-clock";
clocks = <0x9>;
#clock-cells = <0x0>;
enable-gpios = <0x6 0x9 0x1>;
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x3a 0x4>;
clocks = <0x2 0xf>;
clock-names = "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad7291@20 {
compatible = "adi,ad7291";
reg = <0x20>;
};
ad7291-bob@2C {
compatible = "adi,ad7291";
reg = <0x2c>;
};
eeprom@50 {
compatible = "at24,24c32";
reg = <0x50>;
};
};
// dma@7c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c400000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x39 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xa>;
// phandle = <0xa>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x2>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x0>;
// };
// };
// };
// dma@7c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c420000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x38 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xc>;
// phandle = <0xc>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x0>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x2>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0xa 0x0>;
// dma-names = "rx";
spibus-connected = <0xb>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0xb 0xd>;
clock-names = "sampl_clk";
// dmas = <0xc 0x0>;
// dma-names = "tx";
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
/*axi-sysid-0@45000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x45000000 0x10000>;
};*/
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0:green";
gpios = <0x6 0xF 0>;
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <0x1>;
#size-cells = <0x0>;
autorepeat;
sw1 {
label = "SW1";
linux,input-type = <0x5>;
linux,code = <0x3>;
gpios = <0x6 0xE 0x0>;
};
};
};
================================================
FILE: kernel_boot/boards/antsdr/notes.md
================================================
# antsdr for openwifi-hw
## Introduction
[ANTSDR](https://github.com/MicroPhase/antsdr-fw) is a SDR hardware platform based on [xilinx zynq7020](https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html) and [adi ad936x](https://www.analog.com/en/products/ad9361.html). It could be used as a traditional SDR device such as PlutoSDR or FMCOMMS2/3/4 with Xilinx evaluation board, and it also be used as hardware platform to support openwifi.
## Work to be done
The antsdr has RF switch in the front-end, for now, the RF switch is fixed at a higer range, which will isolation the frequency below 3GHz and pass the frequency at 3GHz~6GHz.
For future work, it can add the rf swicth control in the devicetree, and this will change the rf switch with the frequency change.
================================================
FILE: kernel_boot/boards/antsdr_e200/README.md
================================================
# ANTSDR-E200
ANTSDR-E200 is similar to MicroPhase ANTSDR-E310 device.
ANTSDR-E200 has a smaller size and some differences in hardware structure. The ethernet is placed at the PL side.
Since the performance of the zynq processor is not very strong, the Ethernet cannot run at a very high bandwidth. For some SDR applications, the Ethernet may be required to transmit baseband signals above 20MSPS sample rate. In this case, the bandwidth of the Ethernet will reach 80MB/s. If the Ethernet on the PS side wants to run at this bandwidth, it will take up a lot of CPU resources and the bandwidth is still difficult to meet. For this reason, we moved the network port to the PL side.
But this has no effect on IIO-based SDR drivers, because we still use ZYNQ's GEM controller. O(∩_∩)O
When we moved the ethernet to PL, the ANTSDR-E200 could support UHD driver, If anyone is interested in this, you can refer to our project [antsdr_uhd](https://github.com/MicroPhase/antsdr_uhd).
================================================
FILE: kernel_boot/boards/antsdr_e200/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x1>;
model = "ANTSDR-E200";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <0x2 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <0x3>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <0x2 0x3>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x4>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <0x1>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <0x3>;
phandle = <0x3>;
};
amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x1>;
ranges;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <0x1>;
clocks = <0x2 0xc>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x13 0x2 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x14 0x2 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <0x2 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x26>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x19 0x4>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x27>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x30 0x4>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
linux,phandle = <0x1>;
phandle = <0x1>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x3 0x4>;
reg = <0xf800c000 0x1000>;
};
serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x2 0x17 0x2 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
};
serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x2 0x18 0x2 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x1a 0x4>;
clocks = <0x2 0x19 0x2 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5 0x0>;
clock-names = "ad9364_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x62 0x0>;
sync-gpios = <0x6 0x63 0x0>;
reset-gpios = <0x6 0x64 0x0>;
enable-gpios = <0x6 0x65 0x0>;
txnrx-gpios = <0x6 0x66 0x0>;
linux,phandle = <0xb>;
phandle = <0xb>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x1>;
interrupts = <0x0 0x31 0x4>;
clocks = <0x2 0x1a 0x2 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <0x2 0xa 0x2 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
is-dual = <0x0>;
num-cs = <0x1>;
ps7-qspi@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
spi-tx-bus-width = <0x1>;
spi-rx-bus-width = <0x4>;
compatible = "n25q256a", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <0x2faf080>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x0 0xe0000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0xe0000 0x20000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
label = "qspi-rootfs";
reg = <0x620000 0xce0000>;
};
partition@qspi-bitstream {
label = "qspi-bitstream";
reg = <0x1300000 0xd00000>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "disabled";
clock-names = "memclk", "aclk";
clocks = <0x2 0xb 0x2 0x2c>;
compatible = "arm,pl353-smc-r2p1";
interrupt-parent = <0x1>;
interrupts = <0x0 0x12 0x4>;
ranges;
reg = <0xe000e000 0x1000>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
xlnx,has-mdio = <0x1>;
gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;
phy0: phy@1 {
compatible = "ethernet-phy-id011c.c916";
device_type = "ethernet-phy";
reg = <0x1>;
};
gmii_to_rgmii_0: gmiitorgmii@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
reg = <0x8>;
phy-handle = <&phy0>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x0 0x2d 0x4>;
clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x15 0x2 0x20>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
disable-wp;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x16 0x2 0x21>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
linux,phandle = <0x8>;
phandle = <0x8>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <0x8>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x8>;
};
};
dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x1>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x4>;
clocks = <0x2 0x1b>;
clock-names = "apb_pclk";
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x8 0x4>;
reg = <0xf8007000 0x100>;
clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <0x8>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <0x1>;
clocks = <0x2 0x4>;
};
timer@f8001000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8001000 0x1000>;
};
timer@f8002000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8002000 0x1000>;
};
timer@f8f00600 {
interrupt-parent = <0x1>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x2 0x4>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x2 0x1c>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x2 0x1d>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog@f8005000 {
clocks = <0x2 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x1>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
};
aliases {
ethernet0 = "/amba/ethernet@e000b000";
serial0 = "/amba/serial@e0000000";
};
memory {
device_type = "memory";
reg = <0x0 0x20000000>;
};
chosen {
linux,stdout-path = "/amba@0/uart@E0000000";
};
clocks {
clock@0 {
#clock-cells = <0x0>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "ad9364_ext_refclk";
linux,phandle = <0x5>;
phandle = <0x5>;
};
clock@1 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "24MHz";
linux,phandle = <0x9>;
phandle = <0x9>;
};
};
usb-ulpi-gpio-gate@0 {
compatible = "gpio-gate-clock";
clocks = <0x9>;
#clock-cells = <0x0>;
enable-gpios = <0x6 0x9 0x1>;
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x3a 0x4>;
clocks = <0x2 0xf>;
clock-names = "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad7291@20 {
compatible = "adi,ad7291";
reg = <0x20>;
};
ad7291-bob@2C {
compatible = "adi,ad7291";
reg = <0x2c>;
};
eeprom@50 {
compatible = "at24,24c32";
reg = <0x50>;
};
};
// dma@7c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c400000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x39 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xa>;
// phandle = <0xa>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x2>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x0>;
// };
// };
// };
// dma@7c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c420000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x38 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xc>;
// phandle = <0xc>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x0>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x2>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0xa 0x0>;
// dma-names = "rx";
spibus-connected = <0xb>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0xb 0xd>;
clock-names = "sampl_clk";
// dmas = <0xc 0x0>;
// dma-names = "tx";
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
/*axi-sysid-0@45000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x45000000 0x10000>;
};*/
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0:green";
gpios = <0x6 0x0 0>;
linux,default-trigger = "heartbeat";
};
};
};
================================================
FILE: kernel_boot/boards/e310v2/README.md
================================================
# ANTSDR-E310V2
**AntSDR E310V2** is a powerful and versatile software-defined radio (SDR) platform. It is a low-cost, easy-to-use system for developing, testing, and deploying wireless communication solutions such as LTE, GSM, and Wi-Fi. With its wide range of supported frequencies and modulation schemes, it’s possible to easily experiment with various wireless technologies.
Based on the original version, we have optimized the RF performance, added a GPS module, increased an external 10M/PPS input interface, and used a VCXO. The combination of VCXO and external reference input with DAC can generate a more accurate and stable clock. In addition, the Ethernet on the PL makes it possible for E310V2 to be compatible with UHD for higher bandwidth transmission.
If you are interested in using UHD with E310V2, you can find more information in our [repository](https://github.com/MicroPhase/antsdr_uhd).
================================================
FILE: kernel_boot/boards/e310v2/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x01>;
model = "ANTSDR-E310V2";
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x00>;
clocks = <0x02 0x03>;
clock-latency = <0x3e8>;
cpu0-supply = <0x03>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
phandle = <0x11>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x01>;
clocks = <0x02 0x03>;
phandle = <0x13>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x04>;
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
phandle = <0x19>;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;
interrupt-parent = <0x01>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
phandle = <0x03>;
};
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
out-ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x05>;
phandle = <0x0d>;
};
};
port@1 {
reg = <0x01>;
endpoint {
remote-endpoint = <0x06>;
phandle = <0x0c>;
};
};
};
in-ports {
port {
endpoint {
remote-endpoint = <0x07>;
phandle = <0x0e>;
};
};
};
};
axi {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x01>;
interrupt-parent = <0x01>;
ranges;
phandle = <0x1a>;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x00 0x07 0x04>;
interrupt-parent = <0x01>;
clocks = <0x02 0x0c>;
phandle = <0x1b>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x02 0x13 0x02 0x24>;
clock-names = "can_clk\0pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x00 0x1c 0x04>;
interrupt-parent = <0x01>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
phandle = <0x1c>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x02 0x14 0x02 0x25>;
clock-names = "can_clk\0pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x00 0x33 0x04>;
interrupt-parent = <0x01>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
phandle = <0x1d>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x02>;
clocks = <0x02 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x02>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x14 0x04>;
reg = <0xe000a000 0x1000>;
phandle = <0x09>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x02 0x26>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x19 0x04>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x1e>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x02 0x27>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x30 0x04>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x1f>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x03>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
phandle = <0x01>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x00 0x02 0x04>;
arm,data-latency = <0x03 0x02 0x02>;
arm,tag-latency = <0x02 0x02 0x02>;
cache-unified;
cache-level = <0x02>;
phandle = <0x20>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
phandle = <0x21>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x01>;
interrupts = <0x00 0x03 0x04>;
reg = <0xf800c000 0x1000>;
phandle = <0x22>;
};
serial@e0000000 {
compatible = "xlnx,xuartps\0cdns,uart-r1p8";
status = "disabled";
clocks = <0x02 0x17 0x02 0x28>;
clock-names = "uart_clk\0pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x00 0x1b 0x04>;
phandle = <0x23>;
};
serial@e0001000 {
compatible = "xlnx,xuartps\0cdns,uart-r1p8";
status = "okay";
clocks = <0x02 0x18 0x02 0x29>;
clock-names = "uart_clk\0pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x00 0x32 0x04>;
phandle = <0x24>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x01>;
interrupts = <0x00 0x1a 0x04>;
clocks = <0x02 0x19 0x02 0x22>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x25>;
ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x08 0x00>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x09 0x62 0x0>;
sync-gpios = <0x09 0x63 0x0>;
reset-gpios = <0x09 0x64 0x0>;
enable-gpios = <0x09 0x65 0x0>;
txnrx-gpios = <0x09 0x66 0x0>;
phandle = <0x17>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x01>;
interrupts = <0x00 0x31 0x04>;
clocks = <0x02 0x1a 0x02 0x23>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x26>;
};
spi@e000d000 {
clock-names = "ref_clk\0pclk";
clocks = <0x02 0x0a 0x02 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x01>;
interrupts = <0x00 0x13 0x04>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
is-dual = <0x00>;
num-cs = <0x01>;
phandle = <0x27>;
ps7-qspi@0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
spi-tx-bus-width = <0x01>;
spi-rx-bus-width = <0x04>;
compatible = "n25q256a\0jedec,spi-nor";
reg = <0x00>;
spi-max-frequency = <0x2faf080>;
phandle = <0x28>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x00 0xe0000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0xe0000 0x20000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
label = "qspi-rootfs";
reg = <0x620000 0xce0000>;
};
partition@qspi-bitstream {
label = "qspi-bitstream";
reg = <0x1300000 0xd00000>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
status = "disabled";
clock-names = "memclk\0apb_pclk";
clocks = <0x02 0x0b 0x02 0x2c>;
compatible = "arm,pl353-smc-r2p1\0arm,primecell";
interrupt-parent = <0x01>;
interrupts = <0x00 0x12 0x04>;
ranges;
reg = <0xe000e000 0x1000>;
phandle = <0x29>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x2a>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x2b>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
xlnx,has-mdio = <0x1>;
gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;
phy0: phy@1 {
compatible = "ethernet-phy-id011c.c916";
device_type = "ethernet-phy";
reg = <0x1>;
};
gmii_to_rgmii_0: gmiitorgmii@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
reg = <0x8>;
phy-handle = <&phy0>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem\0cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x00 0x2d 0x04>;
clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>;
clock-names = "pclk\0hclk\0tx_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x2d>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin\0clk_ahb";
clocks = <0x02 0x15 0x02 0x20>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x18 0x04>;
reg = <0xe0100000 0x1000>;
disable-wp;
phandle = <0x2e>;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin\0clk_ahb";
clocks = <0x02 0x16 0x02 0x21>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2f 0x04>;
reg = <0xe0101000 0x1000>;
phandle = <0x2f>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
phandle = <0x0b>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x01>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0x0f>;
clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
phandle = <0x02>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x01>;
syscon = <0x0b>;
phandle = <0x30>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x0b>;
phandle = <0x31>;
};
};
dmac@f8003000 {
compatible = "arm,pl330\0arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x01>;
interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7";
interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;
#dma-cells = <0x01>;
#dma-channels = <0x08>;
#dma-requests = <0x04>;
clocks = <0x02 0x1b>;
clock-names = "apb_pclk";
phandle = <0x32>;
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x01>;
interrupts = <0x00 0x08 0x04>;
reg = <0xf8007000 0x100>;
clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>;
clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3";
syscon = <0x0b>;
phandle = <0x04>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
phandle = <0x33>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x01 0x0b 0x301>;
interrupt-parent = <0x01>;
clocks = <0x02 0x04>;
phandle = <0x34>;
};
timer@f8001000 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;
compatible = "cdns,ttc";
clocks = <0x02 0x06>;
reg = <0xf8001000 0x1000>;
phandle = <0x35>;
};
timer@f8002000 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;
compatible = "cdns,ttc";
clocks = <0x02 0x06>;
reg = <0xf8002000 0x1000>;
phandle = <0x36>;
};
timer@f8f00600 {
interrupt-parent = <0x01>;
interrupts = <0x01 0x0d 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x02 0x04>;
phandle = <0x37>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
status = "okay";
clocks = <0x02 0x1c>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x15 0x04>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x09 0x07 0x00>;
phandle = <0x38>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
status = "disabled";
clocks = <0x02 0x1d>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2c 0x04>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
phandle = <0x39>;
};
watchdog@f8005000 {
clocks = <0x02 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x01>;
interrupts = <0x00 0x09 0x01>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0x0a>;
phandle = <0x3a>;
};
etb@f8801000 {
compatible = "arm,coresight-etb10\0arm,primecell";
reg = <0xf8801000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
in-ports {
port {
endpoint {
remote-endpoint = <0x0c>;
phandle = <0x06>;
};
};
};
};
tpiu@f8803000 {
compatible = "arm,coresight-tpiu\0arm,primecell";
reg = <0xf8803000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
in-ports {
port {
endpoint {
remote-endpoint = <0x0d>;
phandle = <0x05>;
};
};
};
};
funnel@f8804000 {
compatible = "arm,coresight-static-funnel\0arm,primecell";
reg = <0xf8804000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
out-ports {
port {
endpoint {
remote-endpoint = <0x0e>;
phandle = <0x07>;
};
};
};
in-ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x0f>;
phandle = <0x12>;
};
};
port@1 {
reg = <0x01>;
endpoint {
remote-endpoint = <0x10>;
phandle = <0x14>;
};
};
port@2 {
reg = <0x02>;
endpoint {
phandle = <0x3b>;
};
};
};
};
ptm@f889c000 {
compatible = "arm,coresight-etm3x\0arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
cpu = <0x11>;
out-ports {
port {
endpoint {
remote-endpoint = <0x12>;
phandle = <0x0f>;
};
};
};
};
ptm@f889d000 {
compatible = "arm,coresight-etm3x\0arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
cpu = <0x13>;
out-ports {
port {
endpoint {
remote-endpoint = <0x14>;
phandle = <0x10>;
};
};
};
};
};
aliases {
ethernet0 = "/axi/ethernet@e000b000";
serial0 = "/axi/serial@e0001000";
phandle = <0x3c>;
};
memory {
device_type = "memory";
reg = <0x00 0x40000000>;
};
chosen {
stdout-path = "/amba@0/uart@E0001000";
};
clocks {
clock@0 {
#clock-cells = <0x00>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "ad9364_ext_refclk";
phandle = <0x08>;
};
clock@1 {
#clock-cells = <0x00>;
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "24MHz";
phandle = <0x15>;
};
};
usb-ulpi-gpio-gate@0 {
compatible = "gpio-gate-clock";
clocks = <0x15>;
#clock-cells = <0x00>;
enable-gpios = <0x09 0x09 0x01>;
phandle = <0x3d>;
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
phandle = <0x3e>;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x3a 0x04>;
clocks = <0x02 0x0f>;
clock-names = "pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x3f>;
ad7291@20 {
compatible = "adi,ad7291";
reg = <0x20>;
};
ad7291-bob@2C {
compatible = "adi,ad7291";
reg = <0x2c>;
};
eeprom@50 {
compatible = "at24,24c32";
reg = <0x50>;
};
};
// dma@7c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c400000 0x10000>;
// #dma-cells = <0x01>;
// interrupts = <0x00 0x39 0x04>;
// clocks = <0x02 0x10>;
// phandle = <0x16>;
// adi,channels {
// #size-cells = <0x00>;
// #address-cells = <0x01>;
// dma-channel@0 {
// reg = <0x00>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x02>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x00>;
// };
// };
// };
// dma@7c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c420000 0x10000>;
// #dma-cells = <0x01>;
// interrupts = <0x00 0x38 0x04>;
// clocks = <0x02 0x10>;
// phandle = <0x18>;
// adi,channels {
// #size-cells = <0x00>;
// #address-cells = <0x01>;
// dma-channel@0 {
// reg = <0x00>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x00>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x02>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
// axidmatest_1: axidmatest@1 {
// compatible ="xlnx,axi-dma-test-1.00.a";
// dmas = <&rx_dma 0
// &rx_dma 1>;
// dma-names = "axidma0", "axidma1";
// } ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0x16 0x00>;
// dma-names = "rx";
spibus-connected = <0x17>;
phandle = <0x40>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0x17 0x0d>;
clock-names = "sampl_clk";
// dmas = <0x18 0x00>;
// dma-names = "tx";
phandle = <0x41>;
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
// axi-sysid-0@45000000 {
// compatible = "adi,axi-sysid-1.00.a";
// reg = <0x45000000 0x10000>;
// phandle = <0x42>;
// };
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0:green";
gpios = <0x09 0x15 0>;
linux,default-trigger = "heartbeat";
};
};
};
================================================
FILE: kernel_boot/boards/neptunesdr/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x01>;
model = "neptunesdr";
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x00>;
clocks = <0x02 0x03>;
clock-latency = <0x3e8>;
cpu0-supply = <0x03>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
phandle = <0x11>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x01>;
clocks = <0x02 0x03>;
phandle = <0x13>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x04>;
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
phandle = <0x19>;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;
interrupt-parent = <0x01>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
phandle = <0x03>;
};
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
out-ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x05>;
phandle = <0x0d>;
};
};
port@1 {
reg = <0x01>;
endpoint {
remote-endpoint = <0x06>;
phandle = <0x0c>;
};
};
};
in-ports {
port {
endpoint {
remote-endpoint = <0x07>;
phandle = <0x0e>;
};
};
};
};
axi {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x01>;
interrupt-parent = <0x01>;
ranges;
phandle = <0x1a>;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x00 0x07 0x04>;
interrupt-parent = <0x01>;
clocks = <0x02 0x0c>;
phandle = <0x1b>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x02 0x13 0x02 0x24>;
clock-names = "can_clk\0pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x00 0x1c 0x04>;
interrupt-parent = <0x01>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
phandle = <0x1c>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x02 0x14 0x02 0x25>;
clock-names = "can_clk\0pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x00 0x33 0x04>;
interrupt-parent = <0x01>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
phandle = <0x1d>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x02>;
clocks = <0x02 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x02>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x14 0x04>;
reg = <0xe000a000 0x1000>;
phandle = <0x09>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x02 0x26>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x19 0x04>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x1e>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x02 0x27>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x30 0x04>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x1f>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x03>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
phandle = <0x01>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x00 0x02 0x04>;
arm,data-latency = <0x03 0x02 0x02>;
arm,tag-latency = <0x02 0x02 0x02>;
cache-unified;
cache-level = <0x02>;
phandle = <0x20>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
phandle = <0x21>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x01>;
interrupts = <0x00 0x03 0x04>;
reg = <0xf800c000 0x1000>;
phandle = <0x22>;
};
serial@e0000000 {
compatible = "xlnx,xuartps\0cdns,uart-r1p8";
status = "disabled";
clocks = <0x02 0x17 0x02 0x28>;
clock-names = "uart_clk\0pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x00 0x1b 0x04>;
phandle = <0x23>;
};
serial@e0001000 {
compatible = "xlnx,xuartps\0cdns,uart-r1p8";
status = "okay";
clocks = <0x02 0x18 0x02 0x29>;
clock-names = "uart_clk\0pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x00 0x32 0x04>;
phandle = <0x24>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x01>;
interrupts = <0x00 0x1a 0x04>;
clocks = <0x02 0x19 0x02 0x22>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x25>;
ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x08 0x00>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x09 0x62 0x0>;
sync-gpios = <0x09 0x63 0x0>;
reset-gpios = <0x09 0x64 0x0>;
enable-gpios = <0x09 0x65 0x0>;
txnrx-gpios = <0x09 0x66 0x0>;
phandle = <0x17>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x01>;
interrupts = <0x00 0x31 0x04>;
clocks = <0x02 0x1a 0x02 0x23>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x26>;
};
spi@e000d000 {
clock-names = "ref_clk\0pclk";
clocks = <0x02 0x0a 0x02 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x01>;
interrupts = <0x00 0x13 0x04>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
is-dual = <0x00>;
num-cs = <0x01>;
phandle = <0x27>;
ps7-qspi@0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
spi-tx-bus-width = <0x01>;
spi-rx-bus-width = <0x04>;
compatible = "n25q256a\0jedec,spi-nor";
reg = <0x00>;
spi-max-frequency = <0x2faf080>;
phandle = <0x28>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x00 0xe0000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0xe0000 0x20000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
label = "qspi-rootfs";
reg = <0x620000 0xce0000>;
};
partition@qspi-bitstream {
label = "qspi-bitstream";
reg = <0x1300000 0xd00000>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
status = "disabled";
clock-names = "memclk\0apb_pclk";
clocks = <0x02 0x0b 0x02 0x2c>;
compatible = "arm,pl353-smc-r2p1\0arm,primecell";
interrupt-parent = <0x01>;
interrupts = <0x00 0x12 0x04>;
ranges;
reg = <0xe000e000 0x1000>;
phandle = <0x29>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x2a>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x2b>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem\0cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x00 0x16 0x04>;
clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>;
clock-names = "pclk\0hclk\0tx_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phy-handle = <0x0a>;
phy-mode = "rgmii-id";
phandle = <0x2c>;
phy@0 {
device_type = "ethernet-phy";
reg = <0x00>;
marvell,reg-init = <0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00>;
phandle = <0x0a>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem\0cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x00 0x2d 0x04>;
clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>;
clock-names = "pclk\0hclk\0tx_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x2d>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin\0clk_ahb";
clocks = <0x02 0x15 0x02 0x20>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x18 0x04>;
reg = <0xe0100000 0x1000>;
disable-wp;
phandle = <0x2e>;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin\0clk_ahb";
clocks = <0x02 0x16 0x02 0x21>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2f 0x04>;
reg = <0xe0101000 0x1000>;
phandle = <0x2f>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
phandle = <0x0b>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x01>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0x0f>;
clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
phandle = <0x02>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x01>;
syscon = <0x0b>;
phandle = <0x30>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x0b>;
phandle = <0x31>;
};
};
dmac@f8003000 {
compatible = "arm,pl330\0arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x01>;
interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7";
interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;
#dma-cells = <0x01>;
#dma-channels = <0x08>;
#dma-requests = <0x04>;
clocks = <0x02 0x1b>;
clock-names = "apb_pclk";
phandle = <0x32>;
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x01>;
interrupts = <0x00 0x08 0x04>;
reg = <0xf8007000 0x100>;
clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>;
clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3";
syscon = <0x0b>;
phandle = <0x04>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
phandle = <0x33>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x01 0x0b 0x301>;
interrupt-parent = <0x01>;
clocks = <0x02 0x04>;
phandle = <0x34>;
};
timer@f8001000 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;
compatible = "cdns,ttc";
clocks = <0x02 0x06>;
reg = <0xf8001000 0x1000>;
phandle = <0x35>;
};
timer@f8002000 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;
compatible = "cdns,ttc";
clocks = <0x02 0x06>;
reg = <0xf8002000 0x1000>;
phandle = <0x36>;
};
timer@f8f00600 {
interrupt-parent = <0x01>;
interrupts = <0x01 0x0d 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x02 0x04>;
phandle = <0x37>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
status = "okay";
clocks = <0x02 0x1c>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x15 0x04>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x09 0x07 0x00>;
phandle = <0x38>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
status = "disabled";
clocks = <0x02 0x1d>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2c 0x04>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
phandle = <0x39>;
};
watchdog@f8005000 {
clocks = <0x02 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x01>;
interrupts = <0x00 0x09 0x01>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0x0a>;
phandle = <0x3a>;
};
etb@f8801000 {
compatible = "arm,coresight-etb10\0arm,primecell";
reg = <0xf8801000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
in-ports {
port {
endpoint {
remote-endpoint = <0x0c>;
phandle = <0x06>;
};
};
};
};
tpiu@f8803000 {
compatible = "arm,coresight-tpiu\0arm,primecell";
reg = <0xf8803000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
in-ports {
port {
endpoint {
remote-endpoint = <0x0d>;
phandle = <0x05>;
};
};
};
};
funnel@f8804000 {
compatible = "arm,coresight-static-funnel\0arm,primecell";
reg = <0xf8804000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
out-ports {
port {
endpoint {
remote-endpoint = <0x0e>;
phandle = <0x07>;
};
};
};
in-ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x0f>;
phandle = <0x12>;
};
};
port@1 {
reg = <0x01>;
endpoint {
remote-endpoint = <0x10>;
phandle = <0x14>;
};
};
port@2 {
reg = <0x02>;
endpoint {
phandle = <0x3b>;
};
};
};
};
ptm@f889c000 {
compatible = "arm,coresight-etm3x\0arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
cpu = <0x11>;
out-ports {
port {
endpoint {
remote-endpoint = <0x12>;
phandle = <0x0f>;
};
};
};
};
ptm@f889d000 {
compatible = "arm,coresight-etm3x\0arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
cpu = <0x13>;
out-ports {
port {
endpoint {
remote-endpoint = <0x14>;
phandle = <0x10>;
};
};
};
};
};
aliases {
ethernet0 = "/axi/ethernet@e000b000";
serial0 = "/axi/serial@e0001000";
phandle = <0x3c>;
};
memory {
device_type = "memory";
reg = <0x00 0x20000000>;
};
chosen {
stdout-path = "/amba@0/uart@E0001000";
};
clocks {
clock@0 {
#clock-cells = <0x00>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "ad9364_ext_refclk";
phandle = <0x08>;
};
clock@1 {
#clock-cells = <0x00>;
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "24MHz";
phandle = <0x15>;
};
};
usb-ulpi-gpio-gate@0 {
compatible = "gpio-gate-clock";
clocks = <0x15>;
#clock-cells = <0x00>;
enable-gpios = <0x09 0x09 0x01>;
phandle = <0x3d>;
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
phandle = <0x3e>;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x3a 0x04>;
clocks = <0x02 0x0f>;
clock-names = "pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x3f>;
ad7291@20 {
compatible = "adi,ad7291";
reg = <0x20>;
};
ad7291-bob@2C {
compatible = "adi,ad7291";
reg = <0x2c>;
};
eeprom@50 {
compatible = "at24,24c32";
reg = <0x50>;
};
};
// dma@7c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c400000 0x10000>;
// #dma-cells = <0x01>;
// interrupts = <0x00 0x39 0x04>;
// clocks = <0x02 0x10>;
// phandle = <0x16>;
// adi,channels {
// #size-cells = <0x00>;
// #address-cells = <0x01>;
// dma-channel@0 {
// reg = <0x00>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x02>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x00>;
// };
// };
// };
// dma@7c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c420000 0x10000>;
// #dma-cells = <0x01>;
// interrupts = <0x00 0x38 0x04>;
// clocks = <0x02 0x10>;
// phandle = <0x18>;
// adi,channels {
// #size-cells = <0x00>;
// #address-cells = <0x01>;
// dma-channel@0 {
// reg = <0x00>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x00>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x02>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
// axidmatest_1: axidmatest@1 {
// compatible ="xlnx,axi-dma-test-1.00.a";
// dmas = <&rx_dma 0
// &rx_dma 1>;
// dma-names = "axidma0", "axidma1";
// } ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0x16 0x00>;
// dma-names = "rx";
spibus-connected = <0x17>;
phandle = <0x40>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0x17 0x0d>;
clock-names = "sampl_clk";
// dmas = <0x18 0x00>;
// dma-names = "tx";
phandle = <0x41>;
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
// axi-sysid-0@45000000 {
// compatible = "adi,axi-sysid-1.00.a";
// reg = <0x45000000 0x10000>;
// phandle = <0x42>;
// };
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0:green";
gpios = <0x09 0x3a 0x00>;
};
led1 {
label = "led1:green";
gpios = <0x09 0x3b 0x00>;
};
led2 {
label = "led2:green";
gpios = <0x09 0x3c 0x00>;
};
led3 {
label = "led3:green";
gpios = <0x09 0x3d 0x00>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <0x01>;
#size-cells = <0x00>;
autorepeat;
pb0 {
label = "Left";
linux,code = <0x69>;
gpios = <0x09 0x36 0x00>;
};
pb1 {
label = "Right";
linux,code = <0x6a>;
gpios = <0x09 0x37 0x00>;
};
pb2 {
label = "Up";
linux,code = <0x67>;
gpios = <0x09 0x38 0x00>;
};
pb3 {
label = "Down";
linux,code = <0x6c>;
gpios = <0x09 0x39 0x00>;
};
sw0 {
label = "SW0";
linux,input-type = <0x05>;
linux,code = <0x0d>;
gpios = <0x09 0x3e 0x00>;
};
sw1 {
label = "SW1";
linux,input-type = <0x05>;
linux,code = <0x01>;
gpios = <0x09 0x3f 0x00>;
};
sw2 {
label = "SW2";
linux,input-type = <0x05>;
linux,code = <0x02>;
gpios = <0x09 0x40 0x00>;
};
sw3 {
label = "SW3";
linux,input-type = <0x05>;
linux,code = <0x03>;
gpios = <0x09 0x41 0x00>;
};
};
};
================================================
FILE: kernel_boot/boards/sdrpi/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x1>;
model = "HexSDR sdrpi (7z020+ad9361 SDR smart platform with GPSTCXO and RF AP)";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <0x2 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <0x3>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <0x2 0x3>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x4>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <0x1>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <0x3>;
phandle = <0x3>;
};
amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x1>;
ranges;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <0x1>;
clocks = <0x2 0xc>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x13 0x2 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x14 0x2 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <0x2 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x26>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x19 0x4>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x27>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x30 0x4>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
linux,phandle = <0x1>;
phandle = <0x1>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x3 0x4>;
reg = <0xf800c000 0x1000>;
};
serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <0x2 0x17 0x2 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
};
serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x2 0x18 0x2 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x1a 0x4>;
clocks = <0x2 0x19 0x2 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5 0x0>;
clock-names = "ad9364_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x62 0x0>;
sync-gpios = <0x6 0x63 0x0>;
reset-gpios = <0x6 0x64 0x0>;
enable-gpios = <0x6 0x65 0x0>;
txnrx-gpios = <0x6 0x66 0x0>;
linux,phandle = <0xb>;
phandle = <0xb>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x1>;
interrupts = <0x0 0x31 0x4>;
clocks = <0x2 0x1a 0x2 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <0x2 0xa 0x2 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
is-dual = <0x0>;
num-cs = <0x1>;
ps7-qspi@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
spi-tx-bus-width = <0x1>;
spi-rx-bus-width = <0x4>;
compatible = "n25q256a", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <0x2faf080>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x0 0xe0000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0xe0000 0x20000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
label = "qspi-rootfs";
reg = <0x620000 0xce0000>;
};
partition@qspi-bitstream {
label = "qspi-bitstream";
reg = <0x1300000 0xd00000>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "disabled";
clock-names = "memclk", "aclk";
clocks = <0x2 0xb 0x2 0x2c>;
compatible = "arm,pl353-smc-r2p1";
interrupt-parent = <0x1>;
interrupts = <0x0 0x12 0x4>;
ranges;
reg = <0xe000e000 0x1000>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <0x7>;
phy-mode = "rgmii-id";
phy@0 {
device_type = "ethernet-phy";
reg = <0x0>;
marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;
linux,phandle = <0x7>;
phandle = <0x7>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "okay";
interrupts = <0x0 0x2d 0x4>;
clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-mode = "gmii";
phy-handle = <&phy1>;
phy1: phy@0{
reg = <0>;
};
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x15 0x2 0x20>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
disable-wp;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x16 0x2 0x21>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
linux,phandle = <0x8>;
phandle = <0x8>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <0x8>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x8>;
};
};
dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x1>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x4>;
clocks = <0x2 0x1b>;
clock-names = "apb_pclk";
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x8 0x4>;
reg = <0xf8007000 0x100>;
clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <0x8>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <0x1>;
clocks = <0x2 0x4>;
};
timer@f8001000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8001000 0x1000>;
};
timer@f8002000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8002000 0x1000>;
};
timer@f8f00600 {
interrupt-parent = <0x1>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x2 0x4>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "okay";
clocks = <0x2 0x1c>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x2 0x1d>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog@f8005000 {
clocks = <0x2 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x1>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
};
aliases {
ethernet0 = "/amba/ethernet@e000b000";
serial0 = "/amba/serial@e0001000";
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
linux,stdout-path = "/amba@0/uart@E0001000";
};
clocks {
clock@0 {
#clock-cells = <0x0>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "ad9364_ext_refclk";
linux,phandle = <0x5>;
phandle = <0x5>;
};
clock@1 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "24MHz";
linux,phandle = <0x9>;
phandle = <0x9>;
};
};
usb-ulpi-gpio-gate@0 {
compatible = "gpio-gate-clock";
clocks = <0x9>;
#clock-cells = <0x0>;
enable-gpios = <0x6 0x9 0x1>;
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x3a 0x4>;
clocks = <0x2 0xf>;
clock-names = "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad7291@20 {
compatible = "adi,ad7291";
reg = <0x20>;
};
ad7291-bob@2C {
compatible = "adi,ad7291";
reg = <0x2c>;
};
eeprom@50 {
compatible = "at24,24c32";
reg = <0x50>;
};
};
// dma@7c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c400000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x39 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xa>;
// phandle = <0xa>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x2>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x0>;
// };
// };
// };
// dma@7c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c420000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x38 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xc>;
// phandle = <0xc>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x0>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x2>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0xa 0x0>;
// dma-names = "rx";
spibus-connected = <0xb>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0xb 0xd>;
clock-names = "sampl_clk";
// dmas = <0xc 0x0>;
// dma-names = "tx";
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
/*axi-sysid-0@45000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x45000000 0x10000>;
};*/
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0:green";
gpios = <0x6 0xF 0>;
linux,default-trigger = "heartbeat";
};
};
// gpio_keys {
// compatible = "gpio-keys";
// #address-cells = <0x1>;
// #size-cells = <0x0>;
// autorepeat;
//
// sw1 {
// label = "SW1";
// linux,input-type = <0x5>;
// linux,code = <0x3>;
// gpios = <0x6 0xE 0x0>;
// };
// };
};
================================================
FILE: kernel_boot/boards/sdrpi/notes.md
================================================
# sdrpi for openwifi
## Introduction
[SDRPi](https://github.com/hexsdr/) is a smart and powerful SDR platform according Raspberry Pi size,which is based on [xilinx zynq7020](https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html) and [adi ad936x](https://www.analog.com/en/products/ad9361.html).
Hareware feature is : ZYNQ 7Z020CLG400 ,1GB DDR3 memory fo PS, 1G Ethernet RJ45 for PS,1G Ethernet RJ45 for PL, USB OTG(act as USB host or USB SLAVE ), dual USB uarts for PS and PL,on board USB to JTAG debuger,TF card , bootable QSPI FLASH and also external 27 IO pins from PL bank in 3.3v vatage with enable this board connect to other boards or modules. AD9361 RF design is based FMCOMMS3 with RF amplifier additionally.It also has a Ublox m8t GPS module and 40MHZ VCXO.
It could be used as a traditional SDR device such as PlutoSDR or FMCOMMS2/3/4 with Xilinx evaluation board, and it also be used as hardware platform to support openwifi.
================================================
FILE: kernel_boot/boards/zc702_fmcs2/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x01>;
model = "Xilinx Zynq ZC702";
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x00>;
clocks = <0x02 0x03>;
clock-latency = <0x3e8>;
cpu0-supply = <0x03>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
phandle = <0x12>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x01>;
clocks = <0x02 0x03>;
phandle = <0x14>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x04>;
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
phandle = <0x21>;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>;
interrupt-parent = <0x01>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
phandle = <0x03>;
};
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
out-ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x05>;
phandle = <0x0e>;
};
};
port@1 {
reg = <0x01>;
endpoint {
remote-endpoint = <0x06>;
phandle = <0x0d>;
};
};
};
in-ports {
port {
endpoint {
remote-endpoint = <0x07>;
phandle = <0x0f>;
};
};
};
};
axi {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x01>;
interrupt-parent = <0x01>;
ranges;
phandle = <0x22>;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x00 0x07 0x04>;
interrupt-parent = <0x01>;
clocks = <0x02 0x0c>;
phandle = <0x23>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x02 0x13 0x02 0x24>;
clock-names = "can_clk\0pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x00 0x1c 0x04>;
interrupt-parent = <0x01>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
phandle = <0x24>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x02 0x14 0x02 0x25>;
clock-names = "can_clk\0pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x00 0x33 0x04>;
interrupt-parent = <0x01>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
phandle = <0x25>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x02>;
clocks = <0x02 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x02>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x14 0x04>;
reg = <0xe000a000 0x1000>;
phandle = <0x09>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x02 0x26>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x19 0x04>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x26>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x02 0x27>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x30 0x04>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x27>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x03>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
phandle = <0x01>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x00 0x02 0x04>;
arm,data-latency = <0x03 0x02 0x02>;
arm,tag-latency = <0x02 0x02 0x02>;
cache-unified;
cache-level = <0x02>;
phandle = <0x28>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
phandle = <0x29>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x01>;
interrupts = <0x00 0x03 0x04>;
reg = <0xf800c000 0x1000>;
phandle = <0x2a>;
};
serial@e0000000 {
compatible = "xlnx,xuartps\0cdns,uart-r1p8";
status = "disabled";
clocks = <0x02 0x17 0x02 0x28>;
clock-names = "uart_clk\0pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x00 0x1b 0x04>;
phandle = <0x2b>;
};
serial@e0001000 {
compatible = "xlnx,xuartps\0cdns,uart-r1p8";
status = "okay";
clocks = <0x02 0x18 0x02 0x29>;
clock-names = "uart_clk\0pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x00 0x32 0x04>;
phandle = <0x2c>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x01>;
interrupts = <0x00 0x1a 0x04>;
clocks = <0x02 0x19 0x02 0x22>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x2d>;
ad9361-phy@0 {
compatible = "adi,ad9361";
reg = <0x00>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x08 0x00>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk\0tx_sampl_clk";
#clock-cells = <0x01>;
adi,digital-interface-tune-skip-mode = <0x00>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x04>;
adi,tx-fb-clock-delay = <0x07>;
adi,dcxo-coarse-and-fine-tune = <0x08 0x1720>;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x00>;
adi,tx-rf-port-input-select = <0x00>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x00 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x02>;
adi,gc-rx2-mode = <0x02>;
adi,gc-adc-ovr-sample-size = <0x04>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x02>;
adi,mgc-dec-gain-step = <0x02>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x00>;
adi,agc-attack-delay-extra-margin-us = <0x01>;
adi,agc-outer-thresh-high = <0x05>;
adi,agc-outer-thresh-high-dec-steps = <0x02>;
adi,agc-inner-thresh-high = <0x0a>;
adi,agc-inner-thresh-high-dec-steps = <0x01>;
adi,agc-inner-thresh-low = <0x0c>;
adi,agc-inner-thresh-low-inc-steps = <0x01>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x02>;
adi,agc-adc-small-overload-exceed-counter = <0x0a>;
adi,agc-adc-large-overload-exceed-counter = <0x0a>;
adi,agc-adc-large-overload-inc-steps = <0x07>;
adi,agc-lmt-overload-large-exceed-counter = <0x0a>;
adi,agc-lmt-overload-small-exceed-counter = <0x0a>;
adi,agc-lmt-overload-large-inc-steps = <0x07>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x01>;
adi,fagc-lp-thresh-increment-time = <0x05>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x03>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x00>;
adi,fagc-lmt-final-settling-steps = <0x01>;
adi,fagc-lock-level = <0x0a>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x05>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x01>;
adi,fagc-optimized-gain-offset = <0x05>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x03>;
adi,rssi-delay = <0x01>;
adi,rssi-wait = <0x01>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x00>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x00>;
adi,aux-dac1-rx-delay-us = <0x00>;
adi,aux-dac1-tx-delay-us = <0x00>;
adi,aux-dac2-default-value-mV = <0x00>;
adi,aux-dac2-rx-delay-us = <0x00>;
adi,aux-dac2-tx-delay-us = <0x00>;
en_agc-gpios = <0x09 0x62 0x00>;
sync-gpios = <0x09 0x63 0x00>;
reset-gpios = <0x09 0x64 0x00>;
enable-gpios = <0x09 0x65 0x00>;
txnrx-gpios = <0x09 0x66 0x00>;
phandle = <0x1d>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "okay";
interrupt-parent = <0x01>;
interrupts = <0x00 0x31 0x04>;
clocks = <0x02 0x1a 0x02 0x23>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x2e>;
adf4351-udc-tx-pmod@0 {
compatible = "adi,adf4351";
reg = <0x00>;
spi-max-frequency = <0x989680>;
clocks = <0x0a>;
clock-names = "clkin";
adi,channel-spacing = <0xf4240>;
adi,power-up-frequency = <0x160dc080>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <0x9c4>;
adi,output-power = <0x03>;
adi,mute-till-lock-enable;
adi,muxout-select = <0x06>;
gpios = <0x09 0x68 0x00>;
phandle = <0x2f>;
};
adf4351-udc-rx-pmod@1 {
compatible = "adi,adf4351";
reg = <0x01>;
spi-max-frequency = <0x989680>;
clocks = <0x0a>;
clock-names = "clkin";
adi,channel-spacing = <0xf4240>;
adi,power-up-frequency = <0x1443fd00>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <0x9c4>;
adi,output-power = <0x03>;
adi,mute-till-lock-enable;
adi,muxout-select = <0x06>;
gpios = <0x09 0x67 0x00>;
phandle = <0x30>;
};
};
spi@e000d000 {
clock-names = "ref_clk\0pclk";
clocks = <0x02 0x0a 0x02 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x01>;
interrupts = <0x00 0x13 0x04>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
is-dual = <0x00>;
num-cs = <0x01>;
phandle = <0x31>;
ps7-qspi@0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "n25q128a11";
reg = <0x00>;
spi-tx-bus-width = <0x01>;
spi-rx-bus-width = <0x04>;
spi-max-frequency = <0x2faf080>;
phandle = <0x32>;
partition@0 {
label = "boot";
reg = <0x00 0x500000>;
};
partition@500000 {
label = "bootenv";
reg = <0x500000 0x20000>;
};
partition@520000 {
label = "config";
reg = <0x520000 0x20000>;
};
partition@540000 {
label = "image";
reg = <0x540000 0xa80000>;
};
partition@fc0000 {
label = "spare";
reg = <0xfc0000 0x00>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
status = "disabled";
clock-names = "memclk\0apb_pclk";
clocks = <0x02 0x0b 0x02 0x2c>;
compatible = "arm,pl353-smc-r2p1\0arm,primecell";
interrupt-parent = <0x01>;
interrupts = <0x00 0x12 0x04>;
ranges;
reg = <0xe000e000 0x1000>;
phandle = <0x33>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x34>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x35>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem\0cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x00 0x16 0x04>;
clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>;
clock-names = "pclk\0hclk\0tx_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phy-handle = <0x0b>;
phy-mode = "rgmii-id";
phandle = <0x36>;
phy@7 {
device_type = "ethernet-phy";
reg = <0x07>;
phandle = <0x0b>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem\0cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x00 0x2d 0x04>;
clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>;
clock-names = "pclk\0hclk\0tx_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x37>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin\0clk_ahb";
clocks = <0x02 0x15 0x02 0x20>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x18 0x04>;
reg = <0xe0100000 0x1000>;
phandle = <0x38>;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin\0clk_ahb";
clocks = <0x02 0x16 0x02 0x21>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2f 0x04>;
reg = <0xe0101000 0x1000>;
phandle = <0x39>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
phandle = <0x0c>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x01>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0x0f>;
clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
phandle = <0x02>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x01>;
syscon = <0x0c>;
phandle = <0x3a>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x0c>;
phandle = <0x3b>;
};
};
dmac@f8003000 {
compatible = "arm,pl330\0arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x01>;
interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7";
interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>;
#dma-cells = <0x01>;
#dma-channels = <0x08>;
#dma-requests = <0x04>;
clocks = <0x02 0x1b>;
clock-names = "apb_pclk";
phandle = <0x1a>;
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x01>;
interrupts = <0x00 0x08 0x04>;
reg = <0xf8007000 0x100>;
clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>;
clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3";
syscon = <0x0c>;
phandle = <0x04>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
phandle = <0x3c>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x01 0x0b 0x301>;
interrupt-parent = <0x01>;
clocks = <0x02 0x04>;
phandle = <0x3d>;
};
timer@f8001000 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>;
compatible = "cdns,ttc";
clocks = <0x02 0x06>;
reg = <0xf8001000 0x1000>;
phandle = <0x3e>;
};
timer@f8002000 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>;
compatible = "cdns,ttc";
clocks = <0x02 0x06>;
reg = <0xf8002000 0x1000>;
phandle = <0x3f>;
};
timer@f8f00600 {
interrupt-parent = <0x01>;
interrupts = <0x01 0x0d 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x02 0x04>;
phandle = <0x40>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
status = "okay";
clocks = <0x02 0x1c>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x15 0x04>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x09 0x07 0x00>;
phandle = <0x41>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
status = "disabled";
clocks = <0x02 0x1d>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2c 0x04>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
phandle = <0x42>;
};
watchdog@f8005000 {
clocks = <0x02 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x01>;
interrupts = <0x00 0x09 0x01>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0x0a>;
phandle = <0x43>;
};
etb@f8801000 {
compatible = "arm,coresight-etb10\0arm,primecell";
reg = <0xf8801000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
in-ports {
port {
endpoint {
remote-endpoint = <0x0d>;
phandle = <0x06>;
};
};
};
};
tpiu@f8803000 {
compatible = "arm,coresight-tpiu\0arm,primecell";
reg = <0xf8803000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
in-ports {
port {
endpoint {
remote-endpoint = <0x0e>;
phandle = <0x05>;
};
};
};
};
funnel@f8804000 {
compatible = "arm,coresight-static-funnel\0arm,primecell";
reg = <0xf8804000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
out-ports {
port {
endpoint {
remote-endpoint = <0x0f>;
phandle = <0x07>;
};
};
};
in-ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x10>;
phandle = <0x13>;
};
};
port@1 {
reg = <0x01>;
endpoint {
remote-endpoint = <0x11>;
phandle = <0x15>;
};
};
port@2 {
reg = <0x02>;
endpoint {
phandle = <0x44>;
};
};
};
};
ptm@f889c000 {
compatible = "arm,coresight-etm3x\0arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
cpu = <0x12>;
out-ports {
port {
endpoint {
remote-endpoint = <0x13>;
phandle = <0x10>;
};
};
};
};
ptm@f889d000 {
compatible = "arm,coresight-etm3x\0arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>;
clock-names = "apb_pclk\0dbg_trc\0dbg_apb";
cpu = <0x14>;
out-ports {
port {
endpoint {
remote-endpoint = <0x15>;
phandle = <0x11>;
};
};
};
};
};
aliases {
ethernet0 = "/axi/ethernet@e000b000";
serial0 = "/axi/serial@e0001000";
phandle = <0x45>;
};
memory {
device_type = "memory";
reg = <0x00 0x40000000>;
};
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait";
stdout-path = "/amba@0/uart@E0001000";
};
leds {
compatible = "gpio-leds";
ds12 {
label = "ds12:green";
gpios = <0x09 0x08 0x00>;
};
ds15 {
label = "ds15:green";
gpios = <0x09 0x3a 0x00>;
};
ds16 {
label = "ds16:green";
gpios = <0x09 0x3b 0x00>;
};
ds17 {
label = "ds17:green";
gpios = <0x09 0x3c 0x00>;
};
ds18 {
label = "ds18:green";
gpios = <0x09 0x3d 0x00>;
};
ds19 {
label = "ds19:green";
gpios = <0x09 0x3e 0x00>;
};
ds20 {
label = "ds20:green";
gpios = <0x09 0x3f 0x00>;
};
ds21 {
label = "ds21:green";
gpios = <0x09 0x40 0x00>;
};
ds22 {
label = "ds22:green";
gpios = <0x09 0x41 0x00>;
};
ds23 {
label = "ds23:green";
gpios = <0x09 0x0a 0x00>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <0x01>;
#size-cells = <0x00>;
autorepeat;
sw5 {
label = "Left";
linux,code = <0x69>;
gpios = <0x09 0x36 0x00>;
};
sw7 {
label = "Right";
linux,code = <0x6a>;
gpios = <0x09 0x37 0x00>;
};
sw15_0 {
label = "SW15_0";
linux,code = <0x0d>;
linux,input-type = <0x05>;
gpios = <0x09 0x38 0x00>;
};
sw15_1 {
label = "SW15_1";
linux,code = <0x01>;
linux,input-type = <0x05>;
gpios = <0x09 0x39 0x00>;
};
sw13 {
label = "Select";
linux,code = <0x1c>;
gpios = <0x09 0x0e 0x00>;
};
sw14 {
label = "SW14";
linux,code = <0x01>;
gpios = <0x09 0x0c 0x00>;
};
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
phandle = <0x46>;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x3a 0x04>;
clocks = <0x02 0x0f>;
clock-names = "pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
mux@74 {
compatible = "pca9548";
reg = <0x74>;
#address-cells = <0x01>;
#size-cells = <0x00>;
i2c@1 {
#size-cells = <0x00>;
#address-cells = <0x01>;
reg = <0x01>;
adv7511@39 {
compatible = "adi,adv7511";
reg = <0x39 0x3f>;
reg-names = "primary\0edid";
adi,input-depth = <0x08>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <0x01>;
adi,input-justification = "right";
adi,clock-delay = <0x00>;
#sound-dai-cells = <0x01>;
phandle = <0x20>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
remote-endpoint = <0x16>;
phandle = <0x19>;
};
};
port@1 {
reg = <0x01>;
};
};
};
};
i2c@4 {
#size-cells = <0x00>;
#address-cells = <0x01>;
reg = <0x04>;
rtc@51 {
compatible = "rtc8564";
reg = <0x51>;
};
};
i2c@5 {
#size-cells = <0x00>;
#address-cells = <0x01>;
reg = <0x05>;
phandle = <0x47>;
ad7291@2f {
compatible = "adi,ad7291";
reg = <0x2f>;
};
eeprom@50 {
compatible = "at24,24c02";
reg = <0x50>;
};
};
};
};
/*
dma@43000000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43000000 0x10000>;
#dma-cells = <0x01>;
interrupts = <0x00 0x3b 0x04>;
clocks = <0x02 0x10>;
phandle = <0x17>;
adi,channels {
#size-cells = <0x00>;
#address-cells = <0x01>;
dma-channel@0 {
reg = <0x00>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x00>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x01>;
};
};
};
axi-clkgen@79000000 {
compatible = "adi,axi-clkgen-2.00.a";
reg = <0x79000000 0x10000>;
#clock-cells = <0x00>;
clocks = <0x02 0x0f 0x02 0x10>;
clock-names = "s_axi_aclk\0clkin1";
phandle = <0x18>;
};
axi_hdmi@70e00000 {
compatible = "adi,axi-hdmi-tx-1.00.a";
reg = <0x70e00000 0x10000>;
dmas = <0x17 0x00>;
dma-names = "video";
clocks = <0x18>;
port {
endpoint {
remote-endpoint = <0x19>;
phandle = <0x16>;
};
};
};
axi-spdif-tx@75c00000 {
compatible = "adi,axi-spdif-tx-1.00.a";
reg = <0x75c00000 0x1000>;
dmas = <0x1a 0x00>;
dma-names = "tx";
clocks = <0x02 0x0f 0x1b>;
clock-names = "axi\0ref";
#sound-dai-cells = <0x00>;
phandle = <0x1f>;
};
axi-sysid-0@45000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x45000000 0x10000>;
phandle = <0x48>;
};
dma@7c400000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c400000 0x10000>;
#dma-cells = <0x01>;
interrupts = <0x00 0x39 0x04>;
clocks = <0x02 0x10>;
phandle = <0x1c>;
adi,channels {
#size-cells = <0x00>;
#address-cells = <0x01>;
dma-channel@0 {
reg = <0x00>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x02>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x00>;
};
};
};
dma@7c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c420000 0x10000>;
#dma-cells = <0x01>;
interrupts = <0x00 0x38 0x04>;
clocks = <0x02 0x10>;
phandle = <0x1e>;
adi,channels {
#size-cells = <0x00>;
#address-cells = <0x01>;
dma-channel@0 {
reg = <0x00>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x00>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x02>;
};
};
};
*/
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0x1c 0x00>;
// dma-names = "rx";
spibus-connected = <0x1d>;
phandle = <0x49>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0x1d 0x0d>;
clock-names = "sampl_clk";
// dmas = <0x1e 0x00>;
// dma-names = "tx";
phandle = <0x4a>;
};
};
/*
audio_clock {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0xbb8000>;
phandle = <0x1b>;
};
adv7511_hdmi_snd {
compatible = "simple-audio-card";
simple-audio-card,name = "HDMI monitor";
simple-audio-card,widgets = "Speaker\0Speaker";
simple-audio-card,routing = "Speaker\0TX";
simple-audio-card,dai-link@0 {
format = "spdif";
cpu {
sound-dai = <0x1f>;
frame-master;
bitclock-master;
};
codec {
sound-dai = <0x20 0x01>;
};
};
};
*/
clocks {
clock@0 {
compatible = "fixed-clock";
clock-frequency = <0x2625a00>;
clock-output-names = "ad9361_ext_refclk";
#clock-cells = <0x00>;
phandle = <0x08>;
};
clock@1 {
compatible = "fixed-clock";
clock-frequency = <0x17d7840>;
clock-output-names = "refclk";
#clock-cells = <0x00>;
phandle = <0x0a>;
};
};
};
================================================
FILE: kernel_boot/boards/zc706_fmcs2/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x1>;
model = "Xilinx Zynq ZC706";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <0x2 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <0x3>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <0x2 0x3>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x4>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <0x1>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <0x3>;
phandle = <0x3>;
};
amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x1>;
ranges;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <0x1>;
clocks = <0x2 0xc>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x13 0x2 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x14 0x2 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <0x2 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x26>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x19 0x4>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x27>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x30 0x4>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
linux,phandle = <0x1>;
phandle = <0x1>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x3 0x4>;
reg = <0xf800c000 0x1000>;
};
serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <0x2 0x17 0x2 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
};
serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x2 0x18 0x2 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x1a 0x4>;
clocks = <0x2 0x19 0x2 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad9361-phy@0 {
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5 0x0>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <0x1>;
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x62 0x0>;
sync-gpios = <0x6 0x63 0x0>;
reset-gpios = <0x6 0x64 0x0>;
enable-gpios = <0x6 0x65 0x0>;
txnrx-gpios = <0x6 0x66 0x0>;
linux,phandle = <0x11>;
phandle = <0x11>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x31 0x4>;
clocks = <0x2 0x1a 0x2 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
adf4351-udc-tx-pmod@0 {
compatible = "adi,adf4351";
reg = <0x0>;
spi-max-frequency = <0x989680>;
clocks = <0x7>;
clock-names = "clkin";
adi,channel-spacing = <0xf4240>;
adi,power-up-frequency = <0x160dc080>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <0x9c4>;
adi,output-power = <0x3>;
adi,mute-till-lock-enable;
adi,muxout-select = <0x6>;
gpios = <0x6 0x68 0x0>;
};
adf4351-udc-rx-pmod@1 {
compatible = "adi,adf4351";
reg = <0x1>;
spi-max-frequency = <0x989680>;
clocks = <0x7>;
clock-names = "clkin";
adi,channel-spacing = <0xf4240>;
adi,power-up-frequency = <0x1443fd00>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <0x9c4>;
adi,output-power = <0x3>;
adi,mute-till-lock-enable;
adi,muxout-select = <0x6>;
gpios = <0x6 0x67 0x0>;
};
};
spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <0x2 0xa 0x2 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
is-dual = <0x1>;
num-cs = <0x1>;
ps7-qspi@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
spi-tx-bus-width = <0x1>;
spi-rx-bus-width = <0x4>;
compatible = "n25q128a11";
reg = <0x0>;
spi-max-frequency = <0x2faf080>;
partition@0 {
label = "boot";
reg = <0x0 0x500000>;
};
partition@500000 {
label = "bootenv";
reg = <0x500000 0x20000>;
};
partition@520000 {
label = "config";
reg = <0x520000 0x20000>;
};
partition@540000 {
label = "image";
reg = <0x540000 0xa80000>;
};
partition@fc0000 {
label = "spare";
reg = <0xfc0000 0x0>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "disabled";
clock-names = "memclk", "aclk";
clocks = <0x2 0xb 0x2 0x2c>;
compatible = "arm,pl353-smc-r2p1";
interrupt-parent = <0x1>;
interrupts = <0x0 0x12 0x4>;
ranges;
reg = <0xe000e000 0x1000>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <0x8>;
phy-mode = "rgmii-id";
phy@7 {
device_type = "ethernet-phy";
reg = <0x7>;
linux,phandle = <0x8>;
phandle = <0x8>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x0 0x2d 0x4>;
clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x15 0x2 0x20>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x16 0x2 0x21>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
linux,phandle = <0x9>;
phandle = <0x9>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <0x9>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x9>;
};
};
dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x1>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x4>;
clocks = <0x2 0x1b>;
clock-names = "apb_pclk";
linux,phandle = <0xe>;
phandle = <0xe>;
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x8 0x4>;
reg = <0xf8007000 0x100>;
clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <0x9>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <0x1>;
clocks = <0x2 0x4>;
};
timer@f8001000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8001000 0x1000>;
};
timer@f8002000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8002000 0x1000>;
};
timer@f8f00600 {
interrupt-parent = <0x1>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x2 0x4>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "okay";
clocks = <0x2 0x1c>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x2 0x1d>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog@f8005000 {
clocks = <0x2 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x1>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
};
aliases {
ethernet0 = "/amba/ethernet@e000b000";
serial0 = "/amba/serial@e0001000";
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait";
linux,stdout-path = "/amba@0/uart@E0001000";
};
leds {
compatible = "gpio-leds";
ds8 {
label = "ds12:green";
gpios = <0x6 0x3d 0x0>;
//gpios = <0x6 7 0x0>;//according to zc706 board, do not know why real gpio_bd[7] here becomes 0x3d
default-state = "off";
};
ds9 {
label = "ds15:green";
gpios = <0x6 0x3e 0x0>;
//gpios = <0x6 8 0x0>;//according to zc706 board, do not know why real gpio_bd[7] here becomes 0x3e
default-state = "off";
};
ds10 {
label = "ds16:green";
gpios = <0x6 0x3f 0x0>;
//gpios = <0x6 9 0x0>;//according to zc706 board, do not know why real gpio_bd[7] here becomes 0x3f
default-state = "off";
};
ds35 {
label = "ds17:green";
gpios = <0x6 0x40 0x0>;
//gpios = <0x6 10 0x0>;//according to zc706 board, do not know why real gpio_bd[7] here becomes 0x40
default-state = "on";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <0x1>;
#size-cells = <0x0>;
autorepeat;
sw7 {
label = "Left";
linux,code = <0x69>;
gpios = <0x6 0x3a 0x0>;
};
sw8 {
label = "Right";
linux,code = <0x6a>;
gpios = <0x6 0x3c 0x0>;
};
sw9 {
label = "Select";
linux,code = <0x1c>;
gpios = <0x6 0x3b 0x0>;
};
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
i2c@41600000 {
compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x3a 0x4>;
clocks = <0x2 0xf>;
clock-names = "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
i2cswitch@74 {
compatible = "nxp,pca9548";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x74>;
i2c@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x0>;
osc@5d {
compatible = "si570";
temperature-stability = <0x32>;
reg = <0x5d>;
factory-fout = <0x9502f90>;
initial-fout = <0x8d9ee20>;
};
};
i2c@1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x1>;
adv7511 {
compatible = "adi,adv7511";
reg = <0x39 0x3f>;
reg-names = "primary", "edid";
adi,input-depth = <0x8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,clock-delay = <0x0>;
#sound-dai-cells = <0x0>;
linux,phandle = <0x14>;
phandle = <0x14>;
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xa>;
linux,phandle = <0xd>;
phandle = <0xd>;
};
};
port@1 {
reg = <0x1>;
};
};
};
};
i2c@2 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x2>;
eeprom@54 {
compatible = "at,24c08";
reg = <0x54>;
};
};
i2c@3 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x3>;
gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <0x2>;
};
};
i2c@4 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x4>;
rtc@54 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
i2c@6 {
#size-cells = <0x0>;
#address-cells = <0x1>;
reg = <0x6>;
ad7291@2f {
compatible = "adi,ad7291";
reg = <0x2f>;
};
eeprom@50 {
compatible = "at24,24c02";
reg = <0x50>;
};
};
};
};
// dma@43000000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x43000000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x3b 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xb>;
// phandle = <0xb>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x0>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x1>;
// };
// };
// };
// axi-clkgen@79000000 {
// compatible = "adi,axi-clkgen-2.00.a";
// reg = <0x79000000 0x10000>;
// #clock-cells = <0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0xc>;
// phandle = <0xc>;
// };
// axi_hdmi@70e00000 {
// compatible = "adi,axi-hdmi-tx-1.00.a";
// reg = <0x70e00000 0x10000>;
// dmas = <0xb 0x0>;
// dma-names = "video";
// clocks = <0xc>;
// adi,is-rgb;
// port {
// endpoint {
// remote-endpoint = <0xd>;
// linux,phandle = <0xa>;
// phandle = <0xa>;
// };
// };
// };
// axi-spdif-tx@75c00000 {
// compatible = "adi,axi-spdif-tx-1.00.a";
// reg = <0x75c00000 0x1000>;
// dmas = <0xe 0x0>;
// dma-names = "tx";
// clocks = <0x2 0xf 0xf>;
// clock-names = "axi", "ref";
// #sound-dai-cells = <0x0>;
// linux,phandle = <0x13>;
// phandle = <0x13>;
// };
/*axi-sysid-0@45000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x45000000 0x10000>;
};*/
// dma@7c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c400000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x39 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0x10>;
// phandle = <0x10>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x2>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x0>;
// };
// };
// };
// dma@7c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c420000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x38 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0x12>;
// phandle = <0x12>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x0>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x2>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0x10 0x0>;
// dma-names = "rx";
spibus-connected = <0x11>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0x11 0xd>;
clock-names = "sampl_clk";
// dmas = <0x12 0x0>;
// dma-names = "tx";
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
};
audio_clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0xbb8000>;
linux,phandle = <0xf>;
phandle = <0xf>;
};
adv7511_hdmi_snd {
compatible = "simple-audio-card";
simple-audio-card,name = "HDMI monitor";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing = "Speaker", "TX";
simple-audio-card,dai-link@0 {
format = "spdif";
cpu {
sound-dai = <0x13>;
frame-master;
bitclock-master;
};
codec {
sound-dai = <0x14>;
};
};
};
clocks {
clock@0 {
compatible = "fixed-clock";
clock-frequency = <0x2625a00>;
clock-output-names = "ad9361_ext_refclk";
#clock-cells = <0x0>;
linux,phandle = <0x5>;
phandle = <0x5>;
};
clock@1 {
compatible = "fixed-clock";
clock-frequency = <0x17d7840>;
clock-output-names = "refclk";
#clock-cells = <0x0>;
linux,phandle = <0x7>;
phandle = <0x7>;
};
};
};
================================================
FILE: kernel_boot/boards/zcu102_fmcs2/system.dts
================================================
/dts-v1/;
/ {
compatible = "xlnx,zynqmp-zcu102-rev1.0\0xlnx,zynqmp-zcu102\0xlnx,zynqmp";
#address-cells = <0x02>;
#size-cells = <0x02>;
model = "ZynqMP ZCU102 Rev1.0";
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
operating-points-v2 = <0x01>;
reg = <0x00>;
cpu-idle-states = <0x02>;
clocks = <0x03 0x0a>;
phandle = <0x3f>;
};
cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x01>;
operating-points-v2 = <0x01>;
cpu-idle-states = <0x02>;
phandle = <0x40>;
};
cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x02>;
operating-points-v2 = <0x01>;
cpu-idle-states = <0x02>;
phandle = <0x41>;
};
cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x03>;
operating-points-v2 = <0x01>;
cpu-idle-states = <0x02>;
phandle = <0x42>;
};
idle-states {
entry-method = "psci";
cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000000>;
local-timer-stop;
entry-latency-us = <0x12c>;
exit-latency-us = <0x258>;
min-residency-us = <0x2710>;
phandle = <0x02>;
};
};
};
cpu-opp-table {
compatible = "operating-points-v2";
opp-shared;
phandle = <0x01>;
opp00 {
opp-hz = <0x00 0x47868bf4>;
opp-microvolt = <0xf4240>;
clock-latency-ns = <0x7a120>;
};
opp01 {
opp-hz = <0x00 0x23c345fa>;
opp-microvolt = <0xf4240>;
clock-latency-ns = <0x7a120>;
};
opp02 {
opp-hz = <0x00 0x17d783fc>;
opp-microvolt = <0xf4240>;
clock-latency-ns = <0x7a120>;
};
opp03 {
opp-hz = <0x00 0x11e1a2fd>;
opp-microvolt = <0xf4240>;
clock-latency-ns = <0x7a120>;
};
};
zynqmp_ipi {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <0x04>;
interrupts = <0x00 0x23 0x04>;
xlnx,ipi-id = <0x00>;
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
phandle = <0x43>;
mailbox@ff990400 {
u-boot,dm-pre-reloc;
reg = <0x00 0xff9905c0 0x00 0x20 0x00 0xff9905e0 0x00 0x20 0x00 0xff990e80 0x00 0x20 0x00 0xff990ea0 0x00 0x20>;
reg-names = "local_request_region\0local_response_region\0remote_request_region\0remote_response_region";
#mbox-cells = <0x01>;
xlnx,ipi-id = <0x04>;
phandle = <0x05>;
};
};
dcc {
compatible = "arm,dcc";
status = "okay";
u-boot,dm-pre-reloc;
phandle = <0x44>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <0x04>;
interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
firmware {
zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <0x01>;
method = "smc";
u-boot,dm-pre-reloc;
phandle = <0x0c>;
zynqmp-power {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-power";
interrupt-parent = <0x04>;
interrupts = <0x00 0x23 0x04>;
mboxes = <0x05 0x00 0x05 0x01>;
mbox-names = "tx\0rx";
phandle = <0x45>;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <0x01>;
#size-cells = <0x01>;
soc_revision@0 {
reg = <0x00 0x04>;
phandle = <0x1e>;
};
efuse_dna@c {
reg = <0x0c 0x0c>;
phandle = <0x46>;
};
efuse_usr0@20 {
reg = <0x20 0x04>;
phandle = <0x47>;
};
efuse_usr1@24 {
reg = <0x24 0x04>;
phandle = <0x48>;
};
efuse_usr2@28 {
reg = <0x28 0x04>;
phandle = <0x49>;
};
efuse_usr3@2c {
reg = <0x2c 0x04>;
phandle = <0x4a>;
};
efuse_usr4@30 {
reg = <0x30 0x04>;
phandle = <0x4b>;
};
efuse_usr5@34 {
reg = <0x34 0x04>;
phandle = <0x4c>;
};
efuse_usr6@38 {
reg = <0x38 0x04>;
phandle = <0x4d>;
};
efuse_usr7@3c {
reg = <0x3c 0x04>;
phandle = <0x4e>;
};
efuse_miscusr@40 {
reg = <0x40 0x04>;
phandle = <0x4f>;
};
efuse_chash@50 {
reg = <0x50 0x04>;
phandle = <0x50>;
};
efuse_pufmisc@54 {
reg = <0x54 0x04>;
phandle = <0x51>;
};
efuse_sec@58 {
reg = <0x58 0x04>;
phandle = <0x52>;
};
efuse_spkid@5c {
reg = <0x5c 0x04>;
phandle = <0x53>;
};
efuse_ppk0hash@a0 {
reg = <0xa0 0x30>;
phandle = <0x54>;
};
efuse_ppk1hash@d0 {
reg = <0xd0 0x30>;
phandle = <0x55>;
};
};
pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
clock-names = "ref_clk";
clocks = <0x03 0x29>;
phandle = <0x0b>;
};
zynqmp-aes {
compatible = "xlnx,zynqmp-aes";
phandle = <0x56>;
};
reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <0x01>;
phandle = <0x1c>;
};
pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
status = "okay";
phandle = <0x57>;
i2c0-default {
phandle = <0x12>;
mux {
groups = "i2c0_3_grp";
function = "i2c0";
};
conf {
groups = "i2c0_3_grp";
bias-pull-up;
slew-rate = <0x01>;
power-source = <0x01>;
};
};
i2c0-gpio {
phandle = <0x13>;
mux {
groups = "gpio0_14_grp\0gpio0_15_grp";
function = "gpio0";
};
conf {
groups = "gpio0_14_grp\0gpio0_15_grp";
slew-rate = <0x01>;
power-source = <0x01>;
};
};
i2c1-default {
phandle = <0x15>;
mux {
groups = "i2c1_4_grp";
function = "i2c1";
};
conf {
groups = "i2c1_4_grp";
bias-pull-up;
slew-rate = <0x01>;
power-source = <0x01>;
};
};
i2c1-gpio {
phandle = <0x16>;
mux {
groups = "gpio0_16_grp\0gpio0_17_grp";
function = "gpio0";
};
conf {
groups = "gpio0_16_grp\0gpio0_17_grp";
slew-rate = <0x01>;
power-source = <0x01>;
};
};
uart0-default {
phandle = <0x21>;
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <0x01>;
power-source = <0x01>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
};
};
uart1-default {
phandle = <0x22>;
mux {
groups = "uart1_5_grp";
function = "uart1";
};
conf {
groups = "uart1_5_grp";
slew-rate = <0x01>;
power-source = <0x01>;
};
conf-rx {
pins = "MIO21";
bias-high-impedance;
};
conf-tx {
pins = "MIO20";
bias-disable;
};
};
usb0-default {
phandle = <0x24>;
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <0x01>;
power-source = <0x01>;
};
conf-rx {
pins = "MIO52\0MIO53\0MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54\0MIO56\0MIO57\0MIO58\0MIO59\0MIO60\0MIO61\0MIO62\0MIO63";
bias-disable;
};
};
gem3-default {
phandle = <0x10>;
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <0x01>;
power-source = <0x01>;
};
conf-rx {
pins = "MIO70\0MIO71\0MIO72\0MIO73\0MIO74\0MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64\0MIO65\0MIO66\0MIO67\0MIO68\0MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <0x01>;
power-source = <0x01>;
bias-disable;
};
};
can1-default {
phandle = <0x0d>;
mux {
function = "can1";
groups = "can1_6_grp";
};
conf {
groups = "can1_6_grp";
slew-rate = <0x01>;
power-source = <0x01>;
};
conf-rx {
pins = "MIO25";
bias-high-impedance;
};
conf-tx {
pins = "MIO24";
bias-disable;
};
};
sdhci1-default {
phandle = <0x1f>;
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
conf {
groups = "sdio1_0_grp";
slew-rate = <0x01>;
power-source = <0x01>;
bias-disable;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <0x01>;
power-source = <0x01>;
};
mux-wp {
groups = "sdio1_wp_0_grp";
function = "sdio1_wp";
};
conf-wp {
groups = "sdio1_wp_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <0x01>;
power-source = <0x01>;
};
};
gpio-default {
phandle = <0x11>;
mux-sw {
function = "gpio0";
groups = "gpio0_22_grp\0gpio0_23_grp";
};
conf-sw {
groups = "gpio0_22_grp\0gpio0_23_grp";
slew-rate = <0x01>;
power-source = <0x01>;
};
mux-msp {
function = "gpio0";
groups = "gpio0_13_grp\0gpio0_38_grp";
};
conf-msp {
groups = "gpio0_13_grp\0gpio0_38_grp";
slew-rate = <0x01>;
power-source = <0x01>;
};
conf-pull-up {
pins = "MIO22\0MIO23";
bias-pull-up;
};
conf-pull-none {
pins = "MIO13\0MIO38";
bias-disable;
};
};
};
sha384 {
compatible = "xlnx,zynqmp-keccak-384";
phandle = <0x58>;
};
zynqmp-rsa {
compatible = "xlnx,zynqmp-rsa";
phandle = <0x59>;
};
gpio {
compatible = "xlnx,zynqmp-gpio-modepin";
gpio-controller;
#gpio-cells = <0x02>;
phandle = <0x23>;
};
clock-controller {
u-boot,dm-pre-reloc;
#clock-cells = <0x01>;
compatible = "xlnx,zynqmp-clk";
clocks = <0x06 0x07 0x08 0x09 0x0a>;
clock-names = "pss_ref_clk\0video_clk\0pss_alt_ref_clk\0aux_ref_clk\0gt_crx_ref_clk";
phandle = <0x03>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <0x04>;
interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
};
edac {
compatible = "arm,cortex-a53-edac";
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x0b>;
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
phandle = <0x5a>;
};
smmu@fd800000 {
compatible = "arm,mmu-500";
reg = <0x00 0xfd800000 0x00 0x20000>;
#iommu-cells = <0x01>;
status = "disabled";
#global-interrupts = <0x01>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>;
phandle = <0x0e>;
};
axi {
compatible = "simple-bus";
u-boot,dm-pre-reloc;
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
phandle = <0x5b>;
can@ff060000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk\0pclk";
reg = <0x00 0xff060000 0x00 0x1000>;
interrupts = <0x00 0x17 0x04>;
interrupt-parent = <0x04>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
power-domains = <0x0c 0x2f>;
clocks = <0x03 0x3f 0x03 0x1f>;
phandle = <0x5c>;
};
can@ff070000 {
compatible = "xlnx,zynq-can-1.0";
status = "okay";
clock-names = "can_clk\0pclk";
reg = <0x00 0xff070000 0x00 0x1000>;
interrupts = <0x00 0x18 0x04>;
interrupt-parent = <0x04>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
power-domains = <0x0c 0x30>;
clocks = <0x03 0x40 0x03 0x1f>;
pinctrl-names = "default";
pinctrl-0 = <0x0d>;
phandle = <0x5d>;
};
cci@fd6e0000 {
compatible = "arm,cci-400";
status = "disabled";
reg = <0x00 0xfd6e0000 0x00 0x9000>;
ranges = <0x00 0x00 0xfd6e0000 0x10000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x5e>;
pmu@9000 {
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04>;
};
};
dma@fd500000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xfd500000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x7c 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x80>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x14e8>;
power-domains = <0x0c 0x2a>;
clocks = <0x03 0x13 0x03 0x1f>;
phandle = <0x5f>;
};
dma@fd510000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xfd510000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x7d 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x80>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x14e9>;
power-domains = <0x0c 0x2a>;
clocks = <0x03 0x13 0x03 0x1f>;
phandle = <0x60>;
};
dma@fd520000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xfd520000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x7e 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x80>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x14ea>;
power-domains = <0x0c 0x2a>;
clocks = <0x03 0x13 0x03 0x1f>;
phandle = <0x61>;
};
dma@fd530000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xfd530000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x7f 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x80>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x14eb>;
power-domains = <0x0c 0x2a>;
clocks = <0x03 0x13 0x03 0x1f>;
phandle = <0x62>;
};
dma@fd540000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xfd540000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x80 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x80>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x14ec>;
power-domains = <0x0c 0x2a>;
clocks = <0x03 0x13 0x03 0x1f>;
phandle = <0x63>;
};
dma@fd550000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xfd550000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x81 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x80>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x14ed>;
power-domains = <0x0c 0x2a>;
clocks = <0x03 0x13 0x03 0x1f>;
phandle = <0x64>;
};
dma@fd560000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xfd560000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x82 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x80>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x14ee>;
power-domains = <0x0c 0x2a>;
clocks = <0x03 0x13 0x03 0x1f>;
phandle = <0x65>;
};
dma@fd570000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xfd570000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x83 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x80>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x14ef>;
power-domains = <0x0c 0x2a>;
clocks = <0x03 0x13 0x03 0x1f>;
phandle = <0x66>;
};
interrupt-controller@f9010000 {
compatible = "arm,gic-400";
#interrupt-cells = <0x03>;
reg = <0x00 0xf9010000 0x00 0x10000 0x00 0xf9020000 0x00 0x20000 0x00 0xf9040000 0x00 0x20000 0x00 0xf9060000 0x00 0x20000>;
interrupt-controller;
interrupt-parent = <0x04>;
interrupts = <0x01 0x09 0xf04>;
phandle = <0x04>;
};
gpu@fd4b0000 {
status = "okay";
compatible = "arm,mali-400\0arm,mali-utgard";
reg = <0x00 0xfd4b0000 0x00 0x10000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04>;
interrupt-names = "IRQGP\0IRQGPMMU\0IRQPP0\0IRQPPMMU0\0IRQPP1\0IRQPPMMU1";
clock-names = "gpu\0gpu_pp0\0gpu_pp1";
power-domains = <0x0c 0x3a>;
clocks = <0x03 0x18 0x03 0x19 0x03 0x1a>;
phandle = <0x67>;
};
dma@ffa80000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xffa80000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x4d 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x40>;
#stream-id-cells = <0x01>;
power-domains = <0x0c 0x2b>;
clocks = <0x03 0x44 0x03 0x1f>;
phandle = <0x68>;
};
dma@ffa90000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xffa90000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x4e 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x40>;
#stream-id-cells = <0x01>;
power-domains = <0x0c 0x2b>;
clocks = <0x03 0x44 0x03 0x1f>;
phandle = <0x69>;
};
dma@ffaa0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xffaa0000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x4f 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x40>;
#stream-id-cells = <0x01>;
power-domains = <0x0c 0x2b>;
clocks = <0x03 0x44 0x03 0x1f>;
phandle = <0x6a>;
};
dma@ffab0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xffab0000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x50 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x40>;
#stream-id-cells = <0x01>;
power-domains = <0x0c 0x2b>;
clocks = <0x03 0x44 0x03 0x1f>;
phandle = <0x6b>;
};
dma@ffac0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xffac0000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x51 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x40>;
#stream-id-cells = <0x01>;
power-domains = <0x0c 0x2b>;
clocks = <0x03 0x44 0x03 0x1f>;
phandle = <0x6c>;
};
dma@ffad0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xffad0000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x52 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x40>;
#stream-id-cells = <0x01>;
power-domains = <0x0c 0x2b>;
clocks = <0x03 0x44 0x03 0x1f>;
phandle = <0x6d>;
};
dma@ffae0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xffae0000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x53 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x40>;
#stream-id-cells = <0x01>;
power-domains = <0x0c 0x2b>;
clocks = <0x03 0x44 0x03 0x1f>;
phandle = <0x6e>;
};
dma@ffaf0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x00 0xffaf0000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x54 0x04>;
clock-names = "clk_main\0clk_apb";
xlnx,bus-width = <0x40>;
#stream-id-cells = <0x01>;
power-domains = <0x0c 0x2b>;
clocks = <0x03 0x44 0x03 0x1f>;
phandle = <0x6f>;
};
memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x00 0xfd070000 0x00 0x30000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x70 0x04>;
phandle = <0x70>;
};
nand-controller@ff100000 {
compatible = "xlnx,zynqmp-nand-controller\0arasan,nfc-v3p10";
status = "disabled";
reg = <0x00 0xff100000 0x00 0x1000>;
clock-names = "controller\0bus";
interrupt-parent = <0x04>;
interrupts = <0x00 0x0e 0x04>;
#address-cells = <0x01>;
#size-cells = <0x00>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x872>;
power-domains = <0x0c 0x2c>;
clocks = <0x03 0x3c 0x03 0x1f>;
phandle = <0x71>;
};
ethernet@ff0b0000 {
compatible = "cdns,zynqmp-gem\0cdns,gem";
status = "disabled";
interrupt-parent = <0x04>;
interrupts = <0x00 0x39 0x04 0x00 0x39 0x04>;
reg = <0x00 0xff0b0000 0x00 0x1000>;
clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x874>;
power-domains = <0x0c 0x1d>;
clocks = <0x03 0x1f 0x03 0x68 0x03 0x2d 0x03 0x31 0x03 0x2c>;
phandle = <0x72>;
};
ethernet@ff0c0000 {
compatible = "cdns,zynqmp-gem\0cdns,gem";
status = "disabled";
interrupt-parent = <0x04>;
interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>;
reg = <0x00 0xff0c0000 0x00 0x1000>;
clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x875>;
power-domains = <0x0c 0x1e>;
clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>;
phandle = <0x73>;
};
ethernet@ff0d0000 {
compatible = "cdns,zynqmp-gem\0cdns,gem";
status = "disabled";
interrupt-parent = <0x04>;
interrupts = <0x00 0x3d 0x04 0x00 0x3d 0x04>;
reg = <0x00 0xff0d0000 0x00 0x1000>;
clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x876>;
power-domains = <0x0c 0x1f>;
clocks = <0x03 0x1f 0x03 0x6a 0x03 0x2f 0x03 0x33 0x03 0x2c>;
phandle = <0x74>;
};
ethernet@ff0e0000 {
compatible = "cdns,zynqmp-gem\0cdns,gem";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x3f 0x04 0x00 0x3f 0x04>;
reg = <0x00 0xff0e0000 0x00 0x1000>;
clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
#address-cells = <0x01>;
#size-cells = <0x00>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x877>;
power-domains = <0x0c 0x20>;
clocks = <0x03 0x1f 0x03 0x6b 0x03 0x30 0x03 0x34 0x03 0x2c>;
phy-handle = <0x0f>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <0x10>;
phandle = <0x75>;
ethernet-phy@c {
reg = <0x0c>;
ti,rx-internal-delay = <0x08>;
ti,tx-internal-delay = <0x0a>;
ti,fifo-depth = <0x01>;
ti,dp83867-rxctrl-strap-quirk;
phandle = <0x0f>;
};
};
gpio@ff0a0000 {
compatible = "xlnx,zynqmp-gpio-1.0";
status = "okay";
#gpio-cells = <0x02>;
gpio-controller;
interrupt-parent = <0x04>;
interrupts = <0x00 0x10 0x04>;
interrupt-controller;
#interrupt-cells = <0x02>;
reg = <0x00 0xff0a0000 0x00 0x1000>;
power-domains = <0x0c 0x2e>;
clocks = <0x03 0x1f>;
pinctrl-names = "default";
pinctrl-0 = <0x11>;
phandle = <0x14>;
};
i2c@ff020000 {
compatible = "cdns,i2c-r1p14";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x11 0x04>;
reg = <0x00 0xff020000 0x00 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
power-domains = <0x0c 0x25>;
clocks = <0x03 0x3d>;
clock-frequency = <0x61a80>;
pinctrl-names = "default\0gpio";
pinctrl-0 = <0x12>;
pinctrl-1 = <0x13>;
scl-gpios = <0x14 0x0e 0x00>;
sda-gpios = <0x14 0x0f 0x00>;
phandle = <0x76>;
gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <0x02>;
gpio-line-names = "PS_GTR_LAN_SEL0\0PS_GTR_LAN_SEL1\0PS_GTR_LAN_SEL2\0PS_GTR_LAN_SEL3\0PCI_CLK_DIR_SEL\0IIC_MUX_RESET_B\0GEM3_EXP_RESET_B\0\0\0\0\0\0\0\0\0";
phandle = <0x77>;
gtr-sel0-hog {
gpio-hog;
gpios = <0x00 0x00>;
output-low;
line-name = "sel0";
};
gtr-sel1-hog {
gpio-hog;
gpios = <0x01 0x00>;
output-high;
line-name = "sel1";
};
gtr-sel2-hog {
gpio-hog;
gpios = <0x02 0x00>;
output-high;
line-name = "sel2";
};
gtr-sel3-hog {
gpio-hog;
gpios = <0x03 0x00>;
output-high;
line-name = "sel3";
};
};
gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <0x02>;
gpio-line-names = "VCCPSPLL_EN\0MGTRAVCC_EN\0MGTRAVTT_EN\0VCCPSDDRPLL_EN\0MIO26_PMU_INPUT_LS\0PL_PMBUS_ALERT\0PS_PMBUS_ALERT\0MAXIM_PMBUS_ALERT\0PL_DDR4_VTERM_EN\0PL_DDR4_VPP_2V5_EN\0PS_DIMM_VDDQ_TO_PSVCCO_ON\0PS_DIMM_SUSPEND_EN\0PS_DDR4_VTERM_EN\0PS_DDR4_VPP_2V5_EN\0\0";
phandle = <0x78>;
};
i2c-mux@75 {
compatible = "nxp,pca9544";
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x75>;
i2c@0 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x00>;
ina226@40 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u76";
reg = <0x40>;
shunt-resistor = <0x1388>;
phandle = <0x2a>;
};
ina226@41 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u77";
reg = <0x41>;
shunt-resistor = <0x1388>;
phandle = <0x2b>;
};
ina226@42 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u78";
reg = <0x42>;
shunt-resistor = <0x1388>;
phandle = <0x2c>;
};
ina226@43 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u87";
reg = <0x43>;
shunt-resistor = <0x1388>;
phandle = <0x2d>;
};
ina226@44 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u85";
reg = <0x44>;
shunt-resistor = <0x1388>;
phandle = <0x2e>;
};
ina226@45 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u86";
reg = <0x45>;
shunt-resistor = <0x1388>;
phandle = <0x2f>;
};
ina226@46 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u93";
reg = <0x46>;
shunt-resistor = <0x1388>;
phandle = <0x30>;
};
ina226@47 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u88";
reg = <0x47>;
shunt-resistor = <0x1388>;
phandle = <0x31>;
};
ina226@4a {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u15";
reg = <0x4a>;
shunt-resistor = <0x1388>;
phandle = <0x32>;
};
ina226@4b {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u92";
reg = <0x4b>;
shunt-resistor = <0x1388>;
phandle = <0x33>;
};
};
i2c@1 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x01>;
ina226@40 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u79";
reg = <0x40>;
shunt-resistor = <0x7d0>;
phandle = <0x34>;
};
ina226@41 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u81";
reg = <0x41>;
shunt-resistor = <0x1388>;
phandle = <0x35>;
};
ina226@42 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u80";
reg = <0x42>;
shunt-resistor = <0x1388>;
phandle = <0x36>;
};
ina226@43 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u84";
reg = <0x43>;
shunt-resistor = <0x1388>;
phandle = <0x37>;
};
ina226@44 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u16";
reg = <0x44>;
shunt-resistor = <0x1388>;
phandle = <0x38>;
};
ina226@45 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u65";
reg = <0x45>;
shunt-resistor = <0x1388>;
phandle = <0x39>;
};
ina226@46 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u74";
reg = <0x46>;
shunt-resistor = <0x1388>;
phandle = <0x3a>;
};
ina226@47 {
compatible = "ti,ina226";
#io-channel-cells = <0x01>;
label = "ina226-u75";
reg = <0x47>;
shunt-resistor = <0x1388>;
phandle = <0x3b>;
};
};
i2c@2 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x02>;
max15301@a {
compatible = "maxim,max15301";
reg = <0x0a>;
};
max15303@b {
compatible = "maxim,max15303";
reg = <0x0b>;
};
max15303@10 {
compatible = "maxim,max15303";
reg = <0x10>;
};
max15301@13 {
compatible = "maxim,max15301";
reg = <0x13>;
};
max15303@14 {
compatible = "maxim,max15303";
reg = <0x14>;
};
max15303@15 {
compatible = "maxim,max15303";
reg = <0x15>;
};
max15303@16 {
compatible = "maxim,max15303";
reg = <0x16>;
};
max15303@17 {
compatible = "maxim,max15303";
reg = <0x17>;
};
max15301@18 {
compatible = "maxim,max15301";
reg = <0x18>;
};
max15303@1a {
compatible = "maxim,max15303";
reg = <0x1a>;
};
max15303@1d {
compatible = "maxim,max15303";
reg = <0x1d>;
};
max20751@72 {
compatible = "maxim,max20751";
reg = <0x72>;
};
max20751@73 {
compatible = "maxim,max20751";
reg = <0x73>;
};
max15303@1b {
compatible = "maxim,max15303";
reg = <0x1b>;
};
};
};
};
i2c@ff030000 {
compatible = "cdns,i2c-r1p14";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x12 0x04>;
reg = <0x00 0xff030000 0x00 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
power-domains = <0x0c 0x26>;
clocks = <0x03 0x3e>;
clock-frequency = <0x61a80>;
pinctrl-names = "default\0gpio";
pinctrl-0 = <0x15>;
pinctrl-1 = <0x16>;
scl-gpios = <0x14 0x10 0x00>;
sda-gpios = <0x14 0x11 0x00>;
phandle = <0x79>;
i2c-mux@74 {
compatible = "nxp,pca9548";
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x74>;
i2c@0 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x00>;
eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
#address-cells = <0x01>;
#size-cells = <0x01>;
phandle = <0x7a>;
board-sn@0 {
reg = <0x00 0x14>;
phandle = <0x7b>;
};
eth-mac@20 {
reg = <0x20 0x06>;
phandle = <0x7c>;
};
board-name@d0 {
reg = <0xd0 0x06>;
phandle = <0x7d>;
};
board-revision@e0 {
reg = <0xe0 0x03>;
phandle = <0x7e>;
};
};
};
i2c@1 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x01>;
clock-generator@36 {
compatible = "silabs,si5341";
reg = <0x36>;
#clock-cells = <0x02>;
#address-cells = <0x01>;
#size-cells = <0x00>;
clocks = <0x17>;
clock-names = "xtal";
clock-output-names = "si5341";
phandle = <0x1b>;
out@0 {
reg = <0x00>;
always-on;
phandle = <0x7f>;
};
out@2 {
reg = <0x02>;
always-on;
phandle = <0x80>;
};
out@3 {
reg = <0x03>;
always-on;
phandle = <0x81>;
};
out@4 {
reg = <0x04>;
always-on;
phandle = <0x82>;
};
out@5 {
reg = <0x05>;
always-on;
phandle = <0x83>;
};
out@6 {
reg = <0x06>;
always-on;
phandle = <0x84>;
};
out@7 {
reg = <0x07>;
always-on;
phandle = <0x85>;
};
out@9 {
reg = <0x09>;
always-on;
phandle = <0x86>;
};
};
};
i2c@2 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x02>;
clock-generator@5d {
#clock-cells = <0x00>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <0x32>;
factory-fout = <0x11e1a300>;
clock-frequency = <0x11e1a300>;
clock-output-names = "si570_user";
phandle = <0x87>;
};
};
i2c@3 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x03>;
clock-generator@5d {
#clock-cells = <0x00>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <0x32>;
factory-fout = <0x9502f90>;
clock-frequency = <0x8d9ee20>;
clock-output-names = "si570_mgt";
phandle = <0x88>;
};
};
i2c@4 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x04>;
clock-generator@69 {
compatible = "silabs,si5328";
reg = <0x69>;
#address-cells = <0x01>;
#size-cells = <0x00>;
#clock-cells = <0x01>;
clocks = <0x18>;
clock-names = "xtal";
clock-output-names = "si5328";
phandle = <0x89>;
clk0@0 {
reg = <0x00>;
clock-frequency = <0x19bfcc0>;
phandle = <0x8a>;
};
};
};
};
i2c-mux@75 {
compatible = "nxp,pca9548";
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x75>;
i2c@0 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x00>;
ad7291@2f {
compatible = "adi,ad7291";
reg = <0x2f>;
};
eeprom@50 {
compatible = "at24,24c02";
reg = <0x50>;
};
};
i2c@1 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x01>;
};
i2c@2 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x02>;
};
i2c@3 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x03>;
};
i2c@4 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x04>;
};
i2c@5 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x05>;
};
i2c@6 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x06>;
};
i2c@7 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x07>;
};
};
};
memory-controller@ff960000 {
compatible = "xlnx,zynqmp-ocmc-1.0";
reg = <0x00 0xff960000 0x00 0x1000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x0a 0x04>;
phandle = <0x8b>;
};
perf-monitor@ffa00000 {
compatible = "xlnx,axi-perf-monitor";
reg = <0x00 0xffa00000 0x00 0x10000>;
interrupts = <0x00 0x19 0x04>;
interrupt-parent = <0x04>;
xlnx,enable-profile = <0x00>;
xlnx,enable-trace = <0x00>;
xlnx,num-monitor-slots = <0x01>;
xlnx,enable-event-count = <0x01>;
xlnx,enable-event-log = <0x01>;
xlnx,have-sampled-metric-cnt = <0x01>;
xlnx,num-of-counters = <0x08>;
xlnx,metric-count-width = <0x20>;
xlnx,metrics-sample-count-width = <0x20>;
xlnx,global-count-width = <0x20>;
xlnx,metric-count-scale = <0x01>;
clocks = <0x03 0x1f>;
phandle = <0x8c>;
};
perf-monitor@fd0b0000 {
compatible = "xlnx,axi-perf-monitor";
reg = <0x00 0xfd0b0000 0x00 0x10000>;
interrupts = <0x00 0x7b 0x04>;
interrupt-parent = <0x04>;
xlnx,enable-profile = <0x00>;
xlnx,enable-trace = <0x00>;
xlnx,num-monitor-slots = <0x06>;
xlnx,enable-event-count = <0x01>;
xlnx,enable-event-log = <0x00>;
xlnx,have-sampled-metric-cnt = <0x01>;
xlnx,num-of-counters = <0x0a>;
xlnx,metric-count-width = <0x20>;
xlnx,metrics-sample-count-width = <0x20>;
xlnx,global-count-width = <0x20>;
xlnx,metric-count-scale = <0x01>;
clocks = <0x03 0x1c>;
phandle = <0x8d>;
};
perf-monitor@fd490000 {
compatible = "xlnx,axi-perf-monitor";
reg = <0x00 0xfd490000 0x00 0x10000>;
interrupts = <0x00 0x7b 0x04>;
interrupt-parent = <0x04>;
xlnx,enable-profile = <0x00>;
xlnx,enable-trace = <0x00>;
xlnx,num-monitor-slots = <0x01>;
xlnx,enable-event-count = <0x01>;
xlnx,enable-event-log = <0x00>;
xlnx,have-sampled-metric-cnt = <0x01>;
xlnx,num-of-counters = <0x08>;
xlnx,metric-count-width = <0x20>;
xlnx,metrics-sample-count-width = <0x20>;
xlnx,global-count-width = <0x20>;
xlnx,metric-count-scale = <0x01>;
clocks = <0x03 0x1c>;
phandle = <0x8e>;
};
perf-monitor@ffa10000 {
compatible = "xlnx,axi-perf-monitor";
reg = <0x00 0xffa10000 0x00 0x10000>;
interrupts = <0x00 0x19 0x04>;
interrupt-parent = <0x04>;
xlnx,enable-profile = <0x00>;
xlnx,enable-trace = <0x00>;
xlnx,num-monitor-slots = <0x01>;
xlnx,enable-event-count = <0x01>;
xlnx,enable-event-log = <0x01>;
xlnx,have-sampled-metric-cnt = <0x01>;
xlnx,num-of-counters = <0x08>;
xlnx,metric-count-width = <0x20>;
xlnx,metrics-sample-count-width = <0x20>;
xlnx,global-count-width = <0x20>;
xlnx,metric-count-scale = <0x01>;
clocks = <0x03 0x1f>;
phandle = <0x8f>;
};
pcie@fd0e0000 {
compatible = "xlnx,nwl-pcie-2.11";
status = "okay";
#address-cells = <0x03>;
#size-cells = <0x02>;
#interrupt-cells = <0x01>;
msi-controller;
device_type = "pci";
interrupt-parent = <0x04>;
interrupts = <0x00 0x76 0x04 0x00 0x75 0x04 0x00 0x74 0x04 0x00 0x73 0x04 0x00 0x72 0x04>;
interrupt-names = "misc\0dummy\0intx\0msi1\0msi0";
msi-parent = <0x19>;
reg = <0x00 0xfd0e0000 0x00 0x1000 0x00 0xfd480000 0x00 0x1000 0x80 0x00 0x00 0x1000000>;
reg-names = "breg\0pcireg\0cfg";
ranges = <0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
interrupt-map = <0x00 0x00 0x00 0x01 0x1a 0x01 0x00 0x00 0x00 0x02 0x1a 0x02 0x00 0x00 0x00 0x03 0x1a 0x03 0x00 0x00 0x00 0x04 0x1a 0x04>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x4d0>;
power-domains = <0x0c 0x3b>;
clocks = <0x03 0x17>;
phandle = <0x19>;
legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0x00>;
#interrupt-cells = <0x01>;
phandle = <0x1a>;
};
};
spi@ff0f0000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-qspi-1.0";
status = "okay";
clock-names = "ref_clk\0pclk";
interrupts = <0x00 0x0f 0x04>;
interrupt-parent = <0x04>;
num-cs = <0x01>;
reg = <0x00 0xff0f0000 0x00 0x1000 0x00 0xc0000000 0x00 0x8000000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x873>;
power-domains = <0x0c 0x2d>;
clocks = <0x03 0x35 0x03 0x1f>;
is-dual = <0x01>;
phandle = <0x90>;
flash@0 {
compatible = "m25p80\0jedec,spi-nor";
#address-cells = <0x01>;
#size-cells = <0x01>;
reg = <0x00>;
spi-tx-bus-width = <0x01>;
spi-rx-bus-width = <0x04>;
spi-max-frequency = <0x66ff300>;
partition@0 {
label = "qspi-fsbl-uboot";
reg = <0x00 0x100000>;
};
partition@100000 {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 {
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
phy@fd400000 {
compatible = "xlnx,zynqmp-psgtr-v1.1";
status = "okay";
reg = <0x00 0xfd400000 0x00 0x40000 0x00 0xfd3d0000 0x00 0x1000>;
reg-names = "serdes\0siou";
#phy-cells = <0x04>;
clocks = <0x1b 0x00 0x05 0x1b 0x00 0x03 0x1b 0x00 0x02 0x1b 0x00 0x00>;
clock-names = "ref0\0ref1\0ref2\0ref3";
phandle = <0x1d>;
};
rtc@ffa60000 {
compatible = "xlnx,zynqmp-rtc";
status = "okay";
reg = <0x00 0xffa60000 0x00 0x100>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>;
interrupt-names = "alarm\0sec";
calibration = <0x7fff>;
phandle = <0x91>;
};
ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "okay";
reg = <0x00 0xfd0c0000 0x00 0x2000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x85 0x04>;
power-domains = <0x0c 0x1c>;
resets = <0x1c 0x10>;
#stream-id-cells = <0x04>;
clocks = <0x03 0x16>;
ceva,p0-cominit-params = <0x18401828>;
ceva,p0-comwake-params = <0x614080e>;
ceva,p0-burst-params = <0x13084a06>;
ceva,p0-retry-params = <0x96a43ffc>;
ceva,p1-cominit-params = <0x18401828>;
ceva,p1-comwake-params = <0x614080e>;
ceva,p1-burst-params = <0x13084a06>;
ceva,p1-retry-params = <0x96a43ffc>;
phy-names = "sata-phy";
phys = <0x1d 0x03 0x01 0x01 0x01>;
phandle = <0x92>;
};
mmc@ff160000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a";
status = "disabled";
xlnx,has-cd = <0x1>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x1>;
disable-wp;
no-1-8-v;
broken-cd;
xlnx,mio-bank = <1>;
/* Do not run SD in HS mode from bootloader */
sdhci-caps-mask = <0 0x200000>;
sdhci-caps = <0 0>;
max-frequency = <19000000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x30 0x04>;
reg = <0x00 0xff160000 0x00 0x1000>;
clock-names = "clk_xin\0clk_ahb";
xlnx,device_id = <0x00>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x870>;
nvmem-cells = <0x1e>;
nvmem-cell-names = "soc_revision";
#clock-cells = <0x01>;
clock-output-names = "clk_out_sd0\0clk_in_sd0";
power-domains = <0x0c 0x27>;
clocks = <0x03 0x36 0x03 0x1f>;
phandle = <0x93>;
};
mmc@ff170000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a";
status = "okay";
xlnx,has-cd = <0x1>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x1>;
disable-wp;
no-1-8-v;
broken-cd;
xlnx,mio-bank = <1>;
/* Do not run SD in HS mode from bootloader */
sdhci-caps-mask = <0 0x200000>;
sdhci-caps = <0 0>;
max-frequency = <19000000>;
interrupt-parent = <0x04>;
interrupts = <0x00 0x31 0x04>;
reg = <0x00 0xff170000 0x00 0x1000>;
clock-names = "clk_xin\0clk_ahb";
xlnx,device_id = <0x01>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x871>;
nvmem-cells = <0x1e>;
nvmem-cell-names = "soc_revision";
#clock-cells = <0x01>;
clock-output-names = "clk_out_sd1\0clk_in_sd1";
power-domains = <0x0c 0x28>;
clocks = <0x03 0x37 0x03 0x1f>;
// no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <0x1f>;
// xlnx,mio-bank = <0x01>;
phandle = <0x94>;
};
spi@ff040000 {
compatible = "cdns,spi-r1p6";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x13 0x04>;
reg = <0x00 0xff040000 0x00 0x1000>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
power-domains = <0x0c 0x23>;
clocks = <0x03 0x3a 0x03 0x1f>;
phandle = <0x95>;
ad9361-phy@0 {
compatible = "adi,ad9361";
reg = <0x00>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x20 0x00>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk\0tx_sampl_clk";
#clock-cells = <0x01>;
adi,digital-interface-tune-skip-mode = <0x00>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x04>;
adi,tx-fb-clock-delay = <0x07>;
adi,dcxo-coarse-and-fine-tune = <0x08 0x1720>;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x00>;
adi,tx-rf-port-input-select = <0x00>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x00 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x02>;
adi,gc-rx2-mode = <0x02>;
adi,gc-adc-ovr-sample-size = <0x04>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x02>;
adi,mgc-dec-gain-step = <0x02>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x00>;
adi,agc-attack-delay-extra-margin-us = <0x01>;
adi,agc-outer-thresh-high = <0x05>;
adi,agc-outer-thresh-high-dec-steps = <0x02>;
adi,agc-inner-thresh-high = <0x0a>;
adi,agc-inner-thresh-high-dec-steps = <0x01>;
adi,agc-inner-thresh-low = <0x0c>;
adi,agc-inner-thresh-low-inc-steps = <0x01>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x02>;
adi,agc-adc-small-overload-exceed-counter = <0x0a>;
adi,agc-adc-large-overload-exceed-counter = <0x0a>;
adi,agc-adc-large-overload-inc-steps = <0x07>;
adi,agc-lmt-overload-large-exceed-counter = <0x0a>;
adi,agc-lmt-overload-small-exceed-counter = <0x0a>;
adi,agc-lmt-overload-large-inc-steps = <0x07>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x01>;
adi,fagc-lp-thresh-increment-time = <0x05>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x03>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x00>;
adi,fagc-lmt-final-settling-steps = <0x01>;
adi,fagc-lock-level = <0x0a>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x05>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x01>;
adi,fagc-optimized-gain-offset = <0x05>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x03>;
adi,rssi-delay = <0x01>;
adi,rssi-wait = <0x01>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x00>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x00>;
adi,aux-dac1-rx-delay-us = <0x00>;
adi,aux-dac1-tx-delay-us = <0x00>;
adi,aux-dac2-default-value-mV = <0x00>;
adi,aux-dac2-rx-delay-us = <0x00>;
adi,aux-dac2-tx-delay-us = <0x00>;
en_agc-gpios = <0x14 0x7a 0x00>;
sync-gpios = <0x14 0x7b 0x00>;
reset-gpios = <0x14 0x7c 0x00>;
enable-gpios = <0x14 0x7d 0x00>;
txnrx-gpios = <0x14 0x7e 0x00>;
phandle = <0x3d>;
};
};
spi@ff050000 {
compatible = "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <0x04>;
interrupts = <0x00 0x14 0x04>;
reg = <0x00 0xff050000 0x00 0x1000>;
clock-names = "ref_clk\0pclk";
#address-cells = <0x01>;
#size-cells = <0x00>;
power-domains = <0x0c 0x24>;
clocks = <0x03 0x3b 0x03 0x1f>;
phandle = <0x96>;
};
timer@ff110000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <0x04>;
interrupts = <0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04>;
reg = <0x00 0xff110000 0x00 0x1000>;
timer-width = <0x20>;
power-domains = <0x0c 0x18>;
clocks = <0x03 0x1f>;
phandle = <0x97>;
};
timer@ff120000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <0x04>;
interrupts = <0x00 0x27 0x04 0x00 0x28 0x04 0x00 0x29 0x04>;
reg = <0x00 0xff120000 0x00 0x1000>;
timer-width = <0x20>;
power-domains = <0x0c 0x19>;
clocks = <0x03 0x1f>;
phandle = <0x98>;
};
timer@ff130000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <0x04>;
interrupts = <0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04>;
reg = <0x00 0xff130000 0x00 0x1000>;
timer-width = <0x20>;
power-domains = <0x0c 0x1a>;
clocks = <0x03 0x1f>;
phandle = <0x99>;
};
timer@ff140000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <0x04>;
interrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04>;
reg = <0x00 0xff140000 0x00 0x1000>;
timer-width = <0x20>;
power-domains = <0x0c 0x1b>;
clocks = <0x03 0x1f>;
phandle = <0x9a>;
};
serial@ff000000 {
u-boot,dm-pre-reloc;
compatible = "cdns,uart-r1p12\0xlnx,xuartps";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x15 0x04>;
reg = <0x00 0xff000000 0x00 0x1000>;
clock-names = "uart_clk\0pclk";
power-domains = <0x0c 0x21>;
clocks = <0x03 0x38 0x03 0x1f>;
pinctrl-names = "default";
pinctrl-0 = <0x21>;
phandle = <0x9b>;
};
serial@ff010000 {
u-boot,dm-pre-reloc;
compatible = "cdns,uart-r1p12\0xlnx,xuartps";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x16 0x04>;
reg = <0x00 0xff010000 0x00 0x1000>;
clock-names = "uart_clk\0pclk";
power-domains = <0x0c 0x22>;
clocks = <0x03 0x39 0x03 0x1f>;
pinctrl-names = "default";
pinctrl-0 = <0x22>;
phandle = <0x9c>;
};
usb0@ff9d0000 {
#address-cells = <0x02>;
#size-cells = <0x02>;
status = "okay";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x00 0xff9d0000 0x00 0x100>;
clock-names = "bus_clk\0ref_clk";
power-domains = <0x0c 0x16>;
resets = <0x1c 0x3b 0x1c 0x3d 0x1c 0x3f>;
reset-names = "usb_crst\0usb_hibrst\0usb_apbrst";
reset-gpio = <0x23 0x01 0x00>;
ranges;
nvmem-cells = <0x1e>;
nvmem-cell-names = "soc_revision";
clocks = <0x03 0x20 0x03 0x22>;
pinctrl-names = "default";
pinctrl-0 = <0x24>;
phandle = <0x9d>;
dwc3@fe200000 {
compatible = "snps,dwc3";
status = "okay";
reg = <0x00 0xfe200000 0x00 0x40000>;
interrupt-parent = <0x04>;
interrupt-names = "dwc_usb3\0otg\0hiber";
interrupts = <0x00 0x41 0x04 0x00 0x45 0x04 0x00 0x4b 0x04>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
dr_mode = "otg";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <0x1d 0x02 0x04 0x00 0x02>;
maximum-speed = "super-speed";
phandle = <0x9e>;
};
};
usb1@ff9e0000 {
#address-cells = <0x02>;
#size-cells = <0x02>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x00 0xff9e0000 0x00 0x100>;
clock-names = "bus_clk\0ref_clk";
power-domains = <0x0c 0x17>;
resets = <0x1c 0x3c 0x1c 0x3e 0x1c 0x40>;
reset-names = "usb_crst\0usb_hibrst\0usb_apbrst";
ranges;
nvmem-cells = <0x1e>;
nvmem-cell-names = "soc_revision";
clocks = <0x03 0x21 0x03 0x22>;
phandle = <0x9f>;
dwc3@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x00 0xfe300000 0x00 0x40000>;
interrupt-parent = <0x04>;
interrupt-names = "dwc_usb3\0otg\0hiber";
interrupts = <0x00 0x46 0x04 0x00 0x4a 0x04 0x00 0x4c 0x04>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
phandle = <0xa0>;
};
};
watchdog@fd4d0000 {
compatible = "cdns,wdt-r1p2";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x71 0x01>;
reg = <0x00 0xfd4d0000 0x00 0x1000>;
timeout-sec = <0x3c>;
reset-on-timeout;
clocks = <0x03 0x4b>;
phandle = <0xa1>;
};
watchdog@ff150000 {
compatible = "cdns,wdt-r1p2";
status = "disabled";
interrupt-parent = <0x04>;
interrupts = <0x00 0x34 0x01>;
reg = <0x00 0xff150000 0x00 0x1000>;
timeout-sec = <0x0a>;
clocks = <0x03 0x70>;
phandle = <0xa2>;
};
ams@ffa50000 {
compatible = "xlnx,zynqmp-ams";
status = "okay";
interrupt-parent = <0x04>;
interrupts = <0x00 0x38 0x04>;
interrupt-names = "ams-irq";
reg = <0x00 0xffa50000 0x00 0x800>;
reg-names = "ams-base";
#address-cells = <0x02>;
#size-cells = <0x02>;
#io-channel-cells = <0x01>;
ranges;
clocks = <0x03 0x46>;
phandle = <0xa3>;
ams_ps@ffa50800 {
compatible = "xlnx,zynqmp-ams-ps";
status = "okay";
reg = <0x00 0xffa50800 0x00 0x400>;
phandle = <0xa4>;
};
ams_pl@ffa50c00 {
compatible = "xlnx,zynqmp-ams-pl";
status = "okay";
reg = <0x00 0xffa50c00 0x00 0x400>;
phandle = <0xa5>;
};
};
dma-controller@fd4c0000 {
compatible = "xlnx,zynqmp-dpdma";
status = "okay";
reg = <0x00 0xfd4c0000 0x00 0x1000>;
interrupts = <0x00 0x7a 0x04>;
interrupt-parent = <0x04>;
clock-names = "axi_clk";
power-domains = <0x0c 0x29>;
dma-channels = <0x06>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0xce4>;
#dma-cells = <0x01>;
clocks = <0x03 0x14>;
phandle = <0x25>;
};
display@fd4a0000 {
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "okay";
reg = <0x00 0xfd4a0000 0x00 0x1000 0x00 0xfd4aa000 0x00 0x1000 0x00 0xfd4ab000 0x00 0x1000 0x00 0xfd4ac000 0x00 0x1000>;
reg-names = "dp\0blend\0av_buf\0aud";
interrupts = <0x00 0x77 0x04>;
interrupt-parent = <0x04>;
#stream-id-cells = <0x01>;
iommus = <0x0e 0xce3>;
clock-names = "dp_apb_clk\0dp_aud_clk\0dp_vtc_pixel_clk_in";
power-domains = <0x0c 0x29>;
resets = <0x1c 0x03>;
dma-names = "vid0\0vid1\0vid2\0gfx0";
dmas = <0x25 0x00 0x25 0x01 0x25 0x02 0x25 0x03>;
clocks = <0x26 0x03 0x11 0x03 0x10>;
phy-names = "dp-phy0";
phys = <0x1d 0x01 0x06 0x00 0x03>;
phandle = <0xa6>;
i2c-bus {
};
zynqmp_dp_snd_codec0 {
compatible = "xlnx,dp-snd-codec";
clock-names = "aud_clk";
clocks = <0x03 0x11>;
status = "okay";
phandle = <0x29>;
};
zynqmp_dp_snd_pcm0 {
compatible = "xlnx,dp-snd-pcm";
dmas = <0x25 0x04>;
dma-names = "tx";
status = "okay";
phandle = <0x27>;
};
zynqmp_dp_snd_pcm1 {
compatible = "xlnx,dp-snd-pcm";
dmas = <0x25 0x05>;
dma-names = "tx";
status = "okay";
phandle = <0x28>;
};
zynqmp_dp_snd_card {
compatible = "xlnx,dp-snd-card";
xlnx,dp-snd-pcm = <0x27 0x28>;
xlnx,dp-snd-codec = <0x29>;
status = "okay";
phandle = <0xa7>;
};
};
};
fclk0 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <0x03 0x47>;
phandle = <0xa8>;
};
fclk1 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <0x03 0x48>;
phandle = <0xa9>;
};
fclk2 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <0x03 0x49>;
phandle = <0xaa>;
};
fclk3 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <0x03 0x4a>;
phandle = <0xab>;
};
pss_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x1fca055>;
phandle = <0x06>;
};
video_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x19bfcc0>;
phandle = <0x07>;
};
pss_alt_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x00>;
phandle = <0x08>;
};
gt_crx_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x66ff300>;
phandle = <0x0a>;
};
aux_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x19bfcc0>;
phandle = <0x09>;
};
dp_aclk {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x5f5e100>;
clock-accuracy = <0x64>;
phandle = <0x26>;
};
aliases {
ethernet0 = "/axi/ethernet@ff0e0000";
gpio0 = "/axi/gpio@ff0a0000";
i2c0 = "/axi/i2c@ff020000";
i2c1 = "/axi/i2c@ff030000";
mmc0 = "/axi/mmc@ff170000";
rtc0 = "/axi/rtc@ffa60000";
serial0 = "/axi/serial@ff000000";
serial1 = "/axi/serial@ff010000";
serial2 = "/dcc";
spi0 = "/axi/spi@ff0f0000";
usb0 = "/axi/usb0@ff9d0000";
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54";
};
memory@0 {
device_type = "memory";
reg = <0x00 0x00 0x00 0x80000000 0x08 0x00 0x00 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
sw19 {
label = "sw19";
gpios = <0x14 0x16 0x00>;
linux,code = <0x6c>;
wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
heartbeat-led {
label = "heartbeat";
gpios = <0x14 0x17 0x00>;
linux,default-trigger = "heartbeat";
};
};
ina226-u76 {
compatible = "iio-hwmon";
io-channels = <0x2a 0x00 0x2a 0x01 0x2a 0x02 0x2a 0x03>;
};
ina226-u77 {
compatible = "iio-hwmon";
io-channels = <0x2b 0x00 0x2b 0x01 0x2b 0x02 0x2b 0x03>;
};
ina226-u78 {
compatible = "iio-hwmon";
io-channels = <0x2c 0x00 0x2c 0x01 0x2c 0x02 0x2c 0x03>;
};
ina226-u87 {
compatible = "iio-hwmon";
io-channels = <0x2d 0x00 0x2d 0x01 0x2d 0x02 0x2d 0x03>;
};
ina226-u85 {
compatible = "iio-hwmon";
io-channels = <0x2e 0x00 0x2e 0x01 0x2e 0x02 0x2e 0x03>;
};
ina226-u86 {
compatible = "iio-hwmon";
io-channels = <0x2f 0x00 0x2f 0x01 0x2f 0x02 0x2f 0x03>;
};
ina226-u93 {
compatible = "iio-hwmon";
io-channels = <0x30 0x00 0x30 0x01 0x30 0x02 0x30 0x03>;
};
ina226-u88 {
compatible = "iio-hwmon";
io-channels = <0x31 0x00 0x31 0x01 0x31 0x02 0x31 0x03>;
};
ina226-u15 {
compatible = "iio-hwmon";
io-channels = <0x32 0x00 0x32 0x01 0x32 0x02 0x32 0x03>;
};
ina226-u92 {
compatible = "iio-hwmon";
io-channels = <0x33 0x00 0x33 0x01 0x33 0x02 0x33 0x03>;
};
ina226-u79 {
compatible = "iio-hwmon";
io-channels = <0x34 0x00 0x34 0x01 0x34 0x02 0x34 0x03>;
};
ina226-u81 {
compatible = "iio-hwmon";
io-channels = <0x35 0x00 0x35 0x01 0x35 0x02 0x35 0x03>;
};
ina226-u80 {
compatible = "iio-hwmon";
io-channels = <0x36 0x00 0x36 0x01 0x36 0x02 0x36 0x03>;
};
ina226-u84 {
compatible = "iio-hwmon";
io-channels = <0x37 0x00 0x37 0x01 0x37 0x02 0x37 0x03>;
};
ina226-u16 {
compatible = "iio-hwmon";
io-channels = <0x38 0x00 0x38 0x01 0x38 0x02 0x38 0x03>;
};
ina226-u65 {
compatible = "iio-hwmon";
io-channels = <0x39 0x00 0x39 0x01 0x39 0x02 0x39 0x03>;
};
ina226-u74 {
compatible = "iio-hwmon";
io-channels = <0x3a 0x00 0x3a 0x01 0x3a 0x02 0x3a 0x03>;
};
ina226-u75 {
compatible = "iio-hwmon";
io-channels = <0x3b 0x00 0x3b 0x01 0x3b 0x02 0x3b 0x03>;
};
ref48M {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x2dc6c00>;
phandle = <0x17>;
};
refhdmi {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x6cfd9c8>;
phandle = <0x18>;
};
fpga-axi@0 {
interrupt-parent = <0x04>;
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges = <0x00 0x00 0x00 0xffffffff>;
phandle = <0xac>;
// dma@9c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x9c400000 0x10000>;
// #dma-cells = <0x01>;
// #clock-cells = <0x00>;
// interrupts = <0x00 0x6d 0x04>;
// clocks = <0x03 0x47>;
// phandle = <0x3c>;
// adi,channels {
// #size-cells = <0x00>;
// #address-cells = <0x01>;
// dma-channel@0 {
// reg = <0x00>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x02>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x00>;
// };
// };
// };
// dma@9c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x9c420000 0x10000>;
// #dma-cells = <0x01>;
// #clock-cells = <0x00>;
// interrupts = <0x00 0x6c 0x04>;
// clocks = <0x03 0x47>;
// phandle = <0x3e>;
// adi,channels {
// #size-cells = <0x00>;
// #address-cells = <0x01>;
// dma-channel@0 {
// reg = <0x00>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x00>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x02>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt_useless", "tx_itrpt";
interrupts = <0 89 1 0 90 1 0 93 1 0 94 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
openwifi_ip_axi_bram_ctrl_0: axi_bram_ctrl@b0000000 {
clock-names = "s_axi_aclk";
clocks = <0x3 0x49>;
compatible = "xlnx,axi-bram-ctrl-4.1";
reg = <0x0 0xb0000000 0x0 0x80000>;
xlnx,bram-addr-width = <0x10>;
xlnx,bram-inst-mode = "EXTERNAL";
xlnx,ecc = <0x0>;
xlnx,ecc-onoff-reset-value = <0x0>;
xlnx,ecc-type = <0x0>;
xlnx,fault-inject = <0x0>;
xlnx,memory-depth = <0x10000>;
xlnx,rd-cmd-optimization = <0x1>;
xlnx,read-latency = <0x1>;
xlnx,s-axi-ctrl-addr-width = <0x20>;
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,s-axi-id-width = <0x10>;
xlnx,s-axi-supports-narrow-burst = <0x1>;
xlnx,single-port-bram = <0x1>;
};
tx_dma: dma@a0000000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x3 0x49>, <0x3 0x49>, <0x3 0x49>, <0x3 0x49>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupts = <0 95 4 0 96 4>;
reg = <0xa0000000 0x10000>;
xlnx,addrwidth = <0x28>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@a0000000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 95 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@a0000030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 96 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@a0010000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x3 0x49>, <0x3 0x49>, <0x3 0x49>, <0x3 0x49>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupts = <0 91 4 0 92 4>;
reg = <0xa0010000 0x10000>;
xlnx,addrwidth = <0x28>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@a0010000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 91 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@a0010030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 92 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@a0060000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x3 0x49>, <0x3 0x49>;//, <0x3 0x49>, <0x3 0x49>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupts = <0 94 1>;
reg = <0xa0060000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@a0040000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x3 0x49>, <0x3 0x49>;//, <0x3 0x49>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupts = <0 89 1 0 90 1>;
reg = <0xa0040000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@a0030000 {
clock-names = "clk";
clocks = <0x3 0x49>;
compatible = "sdr,openofdm_tx";
reg = <0xa0030000 0x10000>;
};
openofdm_rx_0: openofdm_rx@a0020000 {
clock-names = "clk";
clocks = <0x3 0x49>;
compatible = "sdr,openofdm_rx";
reg = <0xa0020000 0x10000>;
};
xpu_0: xpu@a0070000 {
clock-names = "s00_axi_aclk";
clocks = <0x3 0x49>;
compatible = "sdr,xpu";
reg = <0xa0070000 0x10000>;
};
side_ch_0: side_ch@a0050000 {
clock-names = "s00_axi_aclk";
clocks = <0x3 0x49>;
compatible = "sdr,side_ch";
reg = <0xa0050000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@99020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x99020000 0x6000>;
// dmas = <0x3c 0x00>;
// dma-names = "rx";
spibus-connected = <0x3d>;
phandle = <0xad>;
};
cf-ad9361-dds-core-lpc@99024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x99024000 0x1000>;
clocks = <0x3d 0x0d>;
clock-names = "sampl_clk";
// dmas = <0x3e 0x00>;
// dma-names = "tx";
phandle = <0xae>;
};
// axi-sysid-0@85000000 {
// compatible = "adi,axi-sysid-1.00.a";
// reg = <0x85000000 0x10000>;
// phandle = <0xaf>;
// };
};
clocks {
clock@0 {
compatible = "fixed-clock";
clock-frequency = <0x2625a00>;
clock-output-names = "ad9361_ext_refclk";
#clock-cells = <0x00>;
phandle = <0x20>;
};
};
__symbols__ {
cpu0 = "/cpus/cpu@0";
cpu1 = "/cpus/cpu@1";
cpu2 = "/cpus/cpu@2";
cpu3 = "/cpus/cpu@3";
CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0";
cpu_opp_table = "/cpu-opp-table";
zynqmp_ipi = "/zynqmp_ipi";
ipi_mailbox_pmu1 = "/zynqmp_ipi/mailbox@ff990400";
dcc = "/dcc";
zynqmp_firmware = "/firmware/zynqmp-firmware";
zynqmp_power = "/firmware/zynqmp-firmware/zynqmp-power";
soc_revision = "/firmware/zynqmp-firmware/nvmem_firmware/soc_revision@0";
efuse_dna = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_dna@c";
efuse_usr0 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr0@20";
efuse_usr1 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr1@24";
efuse_usr2 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr2@28";
efuse_usr3 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr3@2c";
efuse_usr4 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr4@30";
efuse_usr5 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr5@34";
efuse_usr6 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr6@38";
efuse_usr7 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr7@3c";
efuse_miscusr = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_miscusr@40";
efuse_chash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_chash@50";
efuse_pufmisc = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_pufmisc@54";
efuse_sec = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_sec@58";
efuse_spkid = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_spkid@5c";
efuse_ppk0hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk0hash@a0";
efuse_ppk1hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk1hash@d0";
zynqmp_pcap = "/firmware/zynqmp-firmware/pcap";
xlnx_aes = "/firmware/zynqmp-firmware/zynqmp-aes";
zynqmp_reset = "/firmware/zynqmp-firmware/reset-controller";
pinctrl0 = "/firmware/zynqmp-firmware/pinctrl";
pinctrl_i2c0_default = "/firmware/zynqmp-firmware/pinctrl/i2c0-default";
pinctrl_i2c0_gpio = "/firmware/zynqmp-firmware/pinctrl/i2c0-gpio";
pinctrl_i2c1_default = "/firmware/zynqmp-firmware/pinctrl/i2c1-default";
pinctrl_i2c1_gpio = "/firmware/zynqmp-firmware/pinctrl/i2c1-gpio";
pinctrl_uart0_default = "/firmware/zynqmp-firmware/pinctrl/uart0-default";
pinctrl_uart1_default = "/firmware/zynqmp-firmware/pinctrl/uart1-default";
pinctrl_usb0_default = "/firmware/zynqmp-firmware/pinctrl/usb0-default";
pinctrl_gem3_default = "/firmware/zynqmp-firmware/pinctrl/gem3-default";
pinctrl_can1_default = "/firmware/zynqmp-firmware/pinctrl/can1-default";
pinctrl_sdhci1_default = "/firmware/zynqmp-firmware/pinctrl/sdhci1-default";
pinctrl_gpio_default = "/firmware/zynqmp-firmware/pinctrl/gpio-default";
xlnx_keccak_384 = "/firmware/zynqmp-firmware/sha384";
xlnx_rsa = "/firmware/zynqmp-firmware/zynqmp-rsa";
modepin_gpio = "/firmware/zynqmp-firmware/gpio";
zynqmp_clk = "/firmware/zynqmp-firmware/clock-controller";
fpga_full = "/fpga-full";
smmu = "/smmu@fd800000";
amba = "/axi";
can0 = "/axi/can@ff060000";
can1 = "/axi/can@ff070000";
cci = "/axi/cci@fd6e0000";
fpd_dma_chan1 = "/axi/dma@fd500000";
fpd_dma_chan2 = "/axi/dma@fd510000";
fpd_dma_chan3 = "/axi/dma@fd520000";
fpd_dma_chan4 = "/axi/dma@fd530000";
fpd_dma_chan5 = "/axi/dma@fd540000";
fpd_dma_chan6 = "/axi/dma@fd550000";
fpd_dma_chan7 = "/axi/dma@fd560000";
fpd_dma_chan8 = "/axi/dma@fd570000";
gic = "/axi/interrupt-controller@f9010000";
gpu = "/axi/gpu@fd4b0000";
lpd_dma_chan1 = "/axi/dma@ffa80000";
lpd_dma_chan2 = "/axi/dma@ffa90000";
lpd_dma_chan3 = "/axi/dma@ffaa0000";
lpd_dma_chan4 = "/axi/dma@ffab0000";
lpd_dma_chan5 = "/axi/dma@ffac0000";
lpd_dma_chan6 = "/axi/dma@ffad0000";
lpd_dma_chan7 = "/axi/dma@ffae0000";
lpd_dma_chan8 = "/axi/dma@ffaf0000";
mc = "/axi/memory-controller@fd070000";
nand0 = "/axi/nand-controller@ff100000";
gem0 = "/axi/ethernet@ff0b0000";
gem1 = "/axi/ethernet@ff0c0000";
gem2 = "/axi/ethernet@ff0d0000";
gem3 = "/axi/ethernet@ff0e0000";
phyc = "/axi/ethernet@ff0e0000/ethernet-phy@c";
gpio = "/axi/gpio@ff0a0000";
i2c0 = "/axi/i2c@ff020000";
tca6416_u97 = "/axi/i2c@ff020000/gpio@20";
tca6416_u61 = "/axi/i2c@ff020000/gpio@21";
u76 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@40";
u77 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@41";
u78 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@42";
u87 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@43";
u85 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@44";
u86 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@45";
u93 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@46";
u88 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@47";
u15 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4a";
u92 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4b";
u79 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@40";
u81 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@41";
u80 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@42";
u84 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@43";
u16 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@44";
u65 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@45";
u74 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@46";
u75 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@47";
i2c1 = "/axi/i2c@ff030000";
eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54";
board_sn = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-sn@0";
eth_mac = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/eth-mac@20";
board_name = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-name@d0";
board_revision = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-revision@e0";
si5341 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36";
si5341_0 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@0";
si5341_2 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@2";
si5341_3 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@3";
si5341_4 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@4";
si5341_5 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@5";
si5341_6 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@6";
si5341_7 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@7";
si5341_9 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@9";
si570_1 = "/axi/i2c@ff030000/i2c-mux@74/i2c@2/clock-generator@5d";
si570_2 = "/axi/i2c@ff030000/i2c-mux@74/i2c@3/clock-generator@5d";
si5328 = "/axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69";
si5328_clk = "/axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69/clk0@0";
ocm = "/axi/memory-controller@ff960000";
perf_monitor_ocm = "/axi/perf-monitor@ffa00000";
perf_monitor_ddr = "/axi/perf-monitor@fd0b0000";
perf_monitor_cci = "/axi/perf-monitor@fd490000";
perf_monitor_lpd = "/axi/perf-monitor@ffa10000";
pcie = "/axi/pcie@fd0e0000";
pcie_intc = "/axi/pcie@fd0e0000/legacy-interrupt-controller";
qspi = "/axi/spi@ff0f0000";
psgtr = "/axi/phy@fd400000";
rtc = "/axi/rtc@ffa60000";
sata = "/axi/ahci@fd0c0000";
sdhci0 = "/axi/mmc@ff160000";
sdhci1 = "/axi/mmc@ff170000";
spi0 = "/axi/spi@ff040000";
adc0_ad9361 = "/axi/spi@ff040000/ad9361-phy@0";
spi1 = "/axi/spi@ff050000";
ttc0 = "/axi/timer@ff110000";
ttc1 = "/axi/timer@ff120000";
ttc2 = "/axi/timer@ff130000";
ttc3 = "/axi/timer@ff140000";
uart0 = "/axi/serial@ff000000";
uart1 = "/axi/serial@ff010000";
usb0 = "/axi/usb0@ff9d0000";
dwc3_0 = "/axi/usb0@ff9d0000/dwc3@fe200000";
usb1 = "/axi/usb1@ff9e0000";
dwc3_1 = "/axi/usb1@ff9e0000/dwc3@fe300000";
watchdog0 = "/axi/watchdog@fd4d0000";
lpd_watchdog = "/axi/watchdog@ff150000";
xilinx_ams = "/axi/ams@ffa50000";
ams_ps = "/axi/ams@ffa50000/ams_ps@ffa50800";
ams_pl = "/axi/ams@ffa50000/ams_pl@ffa50c00";
zynqmp_dpdma = "/axi/dma-controller@fd4c0000";
zynqmp_dpsub = "/axi/display@fd4a0000";
zynqmp_dp_snd_codec0 = "/axi/display@fd4a0000/zynqmp_dp_snd_codec0";
zynqmp_dp_snd_pcm0 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm0";
zynqmp_dp_snd_pcm1 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm1";
zynqmp_dp_snd_card0 = "/axi/display@fd4a0000/zynqmp_dp_snd_card";
fclk0 = "/fclk0";
fclk1 = "/fclk1";
fclk2 = "/fclk2";
fclk3 = "/fclk3";
pss_ref_clk = "/pss_ref_clk";
video_clk = "/video_clk";
pss_alt_ref_clk = "/pss_alt_ref_clk";
gt_crx_ref_clk = "/gt_crx_ref_clk";
aux_ref_clk = "/aux_ref_clk";
dp_aclk = "/dp_aclk";
ref48 = "/ref48M";
refhdmi = "/refhdmi";
fpga_axi = "/fpga-axi@0";
rx_dma = "/fpga-axi@0/dma@9c400000";
tx_dma = "/fpga-axi@0/dma@9c420000";
cf_ad9361_adc_core_0 = "/fpga-axi@0/cf-ad9361-lpc@99020000";
cf_ad9361_dac_core_0 = "/fpga-axi@0/cf-ad9361-dds-core-lpc@99024000";
axi_sysid_0 = "/fpga-axi@0/axi-sysid-0@85000000";
ad9361_clkin = "/clocks/clock@0";
};
};
================================================
FILE: kernel_boot/boards/zed_fmcs2/devicetree.dts
================================================
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-7000";
interrupt-parent = <0x1>;
model = "Xilinx Zynq ZED";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <0x2 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <0x3>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <0x2 0x3>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x4>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <0x1>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <0x3>;
phandle = <0x3>;
};
amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x1>;
ranges;
adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <0x1>;
clocks = <0x2 0xc>;
};
can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x13 0x2 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x2 0x14 0x2 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <0x1>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <0x2 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x26>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x19 0x4>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x2 0x27>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x30 0x4>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
linux,phandle = <0x1>;
phandle = <0x1>;
};
cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
};
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc@f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x3 0x4>;
reg = <0xf800c000 0x1000>;
};
serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <0x2 0x17 0x2 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
};
serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x2 0x18 0x2 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
};
spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x1a 0x4>;
clocks = <0x2 0x19 0x2 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
ad9361-phy@0 {
compatible = "adi,ad9361";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5 0x0>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <0x1>;
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x7>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x7>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x10>;
adi,fagc-adc-large-overload-inc-steps = <0x07>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-dig-sat-ovrg-enable;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x10>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x62 0x0>;
sync-gpios = <0x6 0x63 0x0>;
reset-gpios = <0x6 0x64 0x0>;
enable-gpios = <0x6 0x65 0x0>;
txnrx-gpios = <0x6 0x66 0x0>;
linux,phandle = <0x11>;
phandle = <0x11>;
};
};
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x31 0x4>;
clocks = <0x2 0x1a 0x2 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
adf4351-udc-tx-pmod@0 {
compatible = "adi,adf4351";
reg = <0x0>;
spi-max-frequency = <0x989680>;
clocks = <0x7>;
clock-names = "clkin";
adi,channel-spacing = <0xf4240>;
adi,power-up-frequency = <0x160dc080>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <0x9c4>;
adi,output-power = <0x3>;
adi,mute-till-lock-enable;
adi,muxout-select = <0x6>;
gpios = <0x6 0x68 0x0>;
};
adf4351-udc-rx-pmod@1 {
compatible = "adi,adf4351";
reg = <0x1>;
spi-max-frequency = <0x989680>;
clocks = <0x7>;
clock-names = "clkin";
adi,channel-spacing = <0xf4240>;
adi,power-up-frequency = <0x1443fd00>;
adi,phase-detector-polarity-positive-enable;
adi,charge-pump-current = <0x9c4>;
adi,output-power = <0x3>;
adi,mute-till-lock-enable;
adi,muxout-select = <0x6>;
gpios = <0x6 0x67 0x0>;
};
};
spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <0x2 0xa 0x2 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "okay";
interrupt-parent = <0x1>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
is-dual = <0x0>;
num-cs = <0x1>;
ps7-qspi@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "n25q128a11";
reg = <0x0>;
spi-max-frequency = <0x2faf080>;
partition@0 {
label = "boot";
reg = <0x0 0x500000>;
};
partition@500000 {
label = "bootenv";
reg = <0x500000 0x20000>;
};
partition@520000 {
label = "config";
reg = <0x520000 0x20000>;
};
partition@540000 {
label = "image";
reg = <0x540000 0xa80000>;
};
partition@fc0000 {
label = "spare";
reg = <0xfc0000 0x0>;
};
};
};
memory-controller@e000e000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "disabled";
clock-names = "memclk", "aclk";
clocks = <0x2 0xb 0x2 0x2c>;
compatible = "arm,pl353-smc-r2p1";
interrupt-parent = <0x1>;
interrupts = <0x0 0x12 0x4>;
ranges;
reg = <0xe000e000 0x1000>;
flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <0x8>;
phy-mode = "rgmii-id";
phy@0 {
device_type = "ethernet-phy";
reg = <0x0>;
marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0xa>;
linux,phandle = <0x8>;
phandle = <0x8>;
};
};
ethernet@e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x0 0x2d 0x4>;
clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x15 0x2 0x20>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
};
mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x2 0x16 0x2 0x21>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
linux,phandle = <0x9>;
phandle = <0x9>;
clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <0x9>;
};
pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x9>;
};
};
dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x1>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x4>;
clocks = <0x2 0x1b>;
clock-names = "apb_pclk";
linux,phandle = <0xf>;
phandle = <0xf>;
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x1>;
interrupts = <0x0 0x8 0x4>;
reg = <0xf8007000 0x100>;
clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <0x9>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <0x1>;
clocks = <0x2 0x4>;
};
timer@f8001000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8001000 0x1000>;
};
timer@f8002000 {
interrupt-parent = <0x1>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <0x2 0x6>;
reg = <0xf8002000 0x1000>;
};
timer@f8f00600 {
interrupt-parent = <0x1>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x2 0x4>;
};
usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "okay";
clocks = <0x2 0x1c>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
xlnx,phy-reset-gpio = <0x6 0x55 0x0>;
};
usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x2 0x1d>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog@f8005000 {
clocks = <0x2 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x1>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
};
aliases {
ethernet0 = "/amba/ethernet@e000b000";
serial0 = "/amba/serial@e0001000";
};
memory {
device_type = "memory";
reg = <0x0 0x20000000>;
};
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait";
linux,stdout-path = "/amba@0/uart@E0001000";
};
fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
/*
i2c@41600000 {
compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x3a 0x4>;
clocks = <0x2 0xf>;
clock-names = "pclk";
#size-cells = <0x0>;
#address-cells = <0x1>;
adv7511@39 {
compatible = "adi,adv7511";
reg = <0x39 0x3f>;
reg-names = "primary", "edid";
adi,input-depth = <0x8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <0x1>;
adi,input-justification = "right";
adi,clock-delay = <0x0>;
#sound-dai-cells = <0x0>;
linux,phandle = <0x14>;
phandle = <0x14>;
ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
endpoint {
remote-endpoint = <0xa>;
linux,phandle = <0xe>;
phandle = <0xe>;
};
};
port@1 {
reg = <0x1>;
};
};
};
adau1761@3b {
compatible = "adi,adau1761";
reg = <0x3b>;
clocks = <0xb>;
clock-names = "mclk";
#sound-dai-cells = <0x0>;
linux,phandle = <0x16>;
phandle = <0x16>;
};
};
dma@43000000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43000000 0x10000>;
#dma-cells = <0x1>;
interrupts = <0x0 0x3b 0x0>;
clocks = <0x2 0x10>;
linux,phandle = <0xc>;
phandle = <0xc>;
adi,channels {
#size-cells = <0x0>;
#address-cells = <0x1>;
dma-channel@0 {
reg = <0x0>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x0>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x1>;
};
};
};
axi-clkgen@79000000 {
compatible = "adi,axi-clkgen-2.00.a";
reg = <0x79000000 0x10000>;
#clock-cells = <0x0>;
clocks = <0x2 0x10>;
linux,phandle = <0xd>;
phandle = <0xd>;
};
axi_hdmi@70e00000 {
compatible = "adi,axi-hdmi-tx-1.00.a";
reg = <0x70e00000 0x10000>;
dmas = <0xc 0x0>;
dma-names = "video";
clocks = <0xd>;
port {
endpoint {
remote-endpoint = <0xe>;
linux,phandle = <0xa>;
phandle = <0xa>;
};
};
};
axi-spdif-tx@75c00000 {
compatible = "adi,axi-spdif-tx-1.00.a";
reg = <0x75c00000 0x1000>;
dmas = <0xf 0x0>;
dma-names = "tx";
clocks = <0x2 0xf 0xb>;
clock-names = "axi", "ref";
#sound-dai-cells = <0x0>;
linux,phandle = <0x13>;
phandle = <0x13>;
};
axi-i2s@77600000 {
compatible = "adi,axi-i2s-1.00.a";
reg = <0x77600000 0x1000>;
dmas = <0xf 0x1 0xf 0x2>;
dma-names = "tx", "rx";
clocks = <0x2 0xf 0xb>;
clock-names = "axi", "ref";
#sound-dai-cells = <0x0>;
linux,phandle = <0x15>;
phandle = <0x15>;
};
axi-sysid-0@45000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x45000000 0x10000>;
};*/
i2c@41620000 {
compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a";
reg = <0x41620000 0x10000>;
interrupt-parent = <0x1>;
interrupts = <0x0 0x37 0x4>;
clocks = <0x2 0xf>;
clock-names = "pclk";
#size-cells = <0x0>;
#address-cells = <0x1>;
ad7291@2f {
compatible = "adi,ad7291";
reg = <0x2f>;
};
eeprom@50 {
compatible = "at24,24c02";
reg = <0x50>;
};
};
// dma@7c400000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c400000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x39 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0x10>;
// phandle = <0x10>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x2>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x0>;
// };
// };
// };
// dma@7c420000 {
// compatible = "adi,axi-dmac-1.00.a";
// reg = <0x7c420000 0x10000>;
// #dma-cells = <0x1>;
// interrupts = <0x0 0x38 0x0>;
// clocks = <0x2 0x10>;
// linux,phandle = <0x12>;
// phandle = <0x12>;
// adi,channels {
// #size-cells = <0x0>;
// #address-cells = <0x1>;
// dma-channel@0 {
// reg = <0x0>;
// adi,source-bus-width = <0x40>;
// adi,source-bus-type = <0x0>;
// adi,destination-bus-width = <0x40>;
// adi,destination-bus-type = <0x2>;
// };
// };
// };
sdr: sdr {
compatible ="sdr,sdr";
dmas = <&rx_dma 1
&tx_dma 0>;
dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
} ;
axidmatest_1: axidmatest@1 {
compatible ="xlnx,axi-dma-test-1.00.a";
dmas = <&rx_dma 0
&rx_dma 1>;
dma-names = "axidma0", "axidma1";
} ;
tx_dma: dma@80400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 35 4 0 36 4>;
reg = <0x80400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 35 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
dma-channel@80400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 36 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
};
};
rx_dma: dma@80410000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
compatible = "xlnx,axi-dma-1.00.a";
//dma-coherent ;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <1>;
interrupts = <0 31 4 0 32 4>;
reg = <0x80410000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0xe>;
dma-channel@80410000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
interrupts = <0 31 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
dma-channel@80410030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 32 4>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x1>;
};
};
tx_intf_0: tx_intf@83c00000 {
clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
compatible = "sdr,tx_intf";
interrupt-names = "tx_itrpt";
interrupt-parent = <1>;
interrupts = <0 34 1>;
reg = <0x83c00000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
rx_intf_0: rx_intf@83c20000 {
clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
compatible = "sdr,rx_intf";
interrupt-names = "not_valid_anymore", "rx_pkt_intr";
interrupt-parent = <1>;
interrupts = <0 29 1 0 30 1>;
reg = <0x83c20000 0x10000>;
xlnx,s00-axi-addr-width = <0x7>;
xlnx,s00-axi-data-width = <0x20>;
};
openofdm_tx_0: openofdm_tx@83c10000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_tx";
reg = <0x83c10000 0x10000>;
};
openofdm_rx_0: openofdm_rx@83c30000 {
clock-names = "clk";
clocks = <0x2 0x11>;
compatible = "sdr,openofdm_rx";
reg = <0x83c30000 0x10000>;
};
xpu_0: xpu@83c40000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,xpu";
reg = <0x83c40000 0x10000>;
};
side_ch_0: side_ch@83c50000 {
clock-names = "s00_axi_aclk";
clocks = <0x2 0x11>;
compatible = "sdr,side_ch";
reg = <0x83c50000 0x10000>;
dmas = <&rx_dma 0
&tx_dma 1>;
dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
};
cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
// dmas = <0x10 0x0>;
// dma-names = "rx";
spibus-connected = <0x11>;
};
cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <0x11 0xd>;
clock-names = "sampl_clk";
// dmas = <0x12 0x0>;
// dma-names = "tx";
};
};
/*
audio_clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0xbb8000>;
linux,phandle = <0xb>;
phandle = <0xb>;
};
adv7511_hdmi_snd {
compatible = "simple-audio-card";
simple-audio-card,name = "HDMI monitor";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing = "Speaker", "TX";
simple-audio-card,dai-link@0 {
format = "spdif";
cpu {
sound-dai = <0x13>;
frame-master;
bitclock-master;
};
codec {
sound-dai = <0x14>;
};
};
};
zed_sound {
compatible = "simple-audio-card";
simple-audio-card,name = "ZED ADAU1761";
simple-audio-card,widgets = "Microphone", "Mic In", "Headphone", "Headphone Out", "Line", "Line In", "Line", "Line Out";
simple-audio-card,routing = "Line Out", "LOUT", "Line Out", "ROUT", "Headphone Out", "LHP", "Headphone Out", "RHP", "Mic In", "MICBIAS", "LINN", "Mic In", "RINN", "Mic In", "LAUX", "Line In", "RAUX", "Line In";
simple-audio-card,dai-link@0 {
format = "i2s";
cpu {
sound-dai = <0x15>;
frame-master;
bitclock-master;
};
codec {
sound-dai = <0x16>;
};
};
};
*/
leds {
compatible = "gpio-leds";
ld0 {
label = "ld0:red";
gpios = <0x6 0x49 0x0>;
};
ld1 {
label = "ld1:red";
gpios = <0x6 0x4a 0x0>;
};
ld2 {
label = "ld2:red";
gpios = <0x6 0x4b 0x0>;
};
ld3 {
label = "ld3:red";
gpios = <0x6 0x4c 0x0>;
};
ld4 {
label = "ld4:red";
gpios = <0x6 0x4d 0x0>;
};
ld5 {
label = "ld5:red";
gpios = <0x6 0x4e 0x0>;
};
ld6 {
label = "ld6:red";
gpios = <0x6 0x4f 0x0>;
};
ld7 {
label = "ld7:red";
gpios = <0x6 0x50 0x0>;
};
};
clocks {
clock@0 {
compatible = "fixed-clock";
clock-frequency = <0x2625a00>;
clock-output-names = "ad9361_ext_refclk";
#clock-cells = <0x0>;
linux,phandle = <0x5>;
phandle = <0x5>;
};
clock@1 {
compatible = "fixed-clock";
clock-frequency = <0x17d7840>;
clock-output-names = "refclk";
#clock-cells = <0x0>;
linux,phandle = <0x7>;
phandle = <0x7>;
};
};
};
================================================
FILE: kernel_boot/build_boot_bin.sh
================================================
#!/bin/bash
set -ex
HDF_FILE=$1
UBOOT_FILE=$2
BUILD_DIR=build_boot_bin
OUTPUT_DIR=output_boot_bin
usage () {
echo "usage: $0 system_top. u-boot.elf [output-archive]"
exit 1
}
depends () {
echo Xilinx $1 must be installed and in your PATH
echo try: source /opt/Xilinx/Vivado/201x.x/settings64.sh
exit 1
}
### Check command line parameters
echo $HDF_FILE | grep -q ".hdf\|.xsa" || usage
echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" -e "u-boot"|| usage
if [ ! -f $HDF_FILE ]; then
echo $HDF_FILE: File not found!
usage
fi
if [ ! -f $UBOOT_FILE ]; then
echo $UBOOT_FILE: File not found!
usage
fi
### Check for required Xilinx tools (xcst is equivalent with 'xsdk -batch')
command -v xsct >/dev/null 2>&1 || depends xsct
command -v bootgen >/dev/null 2>&1 || depends bootgen
rm -Rf $BUILD_DIR $OUTPUT_DIR
mkdir -p $OUTPUT_DIR
mkdir -p $BUILD_DIR
cp $HDF_FILE $BUILD_DIR/
cp $UBOOT_FILE $OUTPUT_DIR/u-boot.elf
cp $HDF_FILE $OUTPUT_DIR/
### Create create_fsbl_project.tcl file used by xsct to create the fsbl.
echo "hsi open_hw_design `basename $HDF_FILE`" > $BUILD_DIR/create_fsbl_project.tcl
echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl
### The fsbl creating flow is different starting with 2019.2 Xilinx version
if [[ "$HDF_FILE" =~ ".hdf" ]];then
echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl
echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl
echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl
echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl
echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl
FSBL_PATH="$BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf"
SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw_0/system_top.bit"
else
echo 'platform create -name hw0 -hw system_top.xsa -os standalone -out ./build/sdk -proc $cpu_name' >> $BUILD_DIR/create_fsbl_project.tcl
echo 'platform generate' >> $BUILD_DIR/create_fsbl_project.tcl
FSBL_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/fsbl.elf"
SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw0/hw/system_top.bit"
fi
### Create zynq.bif file used by bootgen
echo 'the_ROM_image:' > $OUTPUT_DIR/zynq.bif
echo '{' >> $OUTPUT_DIR/zynq.bif
echo '[bootloader] fsbl.elf' >> $OUTPUT_DIR/zynq.bif
echo 'system_top.bit' >> $OUTPUT_DIR/zynq.bif
echo 'u-boot.elf' >> $OUTPUT_DIR/zynq.bif
echo '}' >> $OUTPUT_DIR/zynq.bif
### Build fsbl.elf
(
cd $BUILD_DIR
xsct create_fsbl_project.tcl
)
### Copy fsbl and system_top.bit into the output folder
cp $FSBL_PATH $OUTPUT_DIR/fsbl.elf
cp $SYSTEM_TOP_BIT_PATH $OUTPUT_DIR/system_top.bit
### Build BOOT.BIN
(
cd $OUTPUT_DIR
bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w
)
### Optionally tar.gz the entire output folder with the name given in argument 3
if [ ${#3} -ne 0 ]; then
tar czvf $3.tar.gz $OUTPUT_DIR
fi
================================================
FILE: kernel_boot/build_zynqmp_boot_bin.sh
================================================
#!/bin/bash
set -ex
XSA_FILE=$1
UBOOT_FILE=$2
ATF_FILE=${3:-download}
BUILD_DIR=build_boot_bin
OUTPUT_DIR=output_boot_bin
usage () {
echo "usage: $0 filename.xsa u-boot.elf (download | bl31.elf | ) [output-archive]"
exit 1
}
depends () {
echo "Xilinx $1 must be installed and in your PATH"
echo "try: source /opt/Xilinx/Vivado/202x.x/settings64.sh"
exit 1
}
### Check command line parameters
echo $XSA_FILE | grep -q ".xsa" || usage
echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" -e "u-boot" || usage
if [ ! -f $XSA_FILE ]; then
echo $XSA_FILE: File not found!
usage
fi
if [ ! -f $UBOOT_FILE ]; then
echo $UBOOT_FILE: File not found!
usage
fi
### Check for required Xilinx tools (starting with 2019.2 there is no hsi anymore)
command -v xsct >/dev/null 2>&1 || depends xsct
command -v bootgen >/dev/null 2>&1 || depends bootgen
rm -Rf $BUILD_DIR $OUTPUT_DIR
mkdir -p $OUTPUT_DIR
mkdir -p $BUILD_DIR
# 2020.1 use bf72e4d494f3be10665b94c0e88766eb2096ef71
# 2021.2 use 799131a3b063f6f24f87baa74e46906c076aebcd
# 2022.2 use 5ebf70ea38e4626637568352b644acbffe3b13c1
# 2023.1 use c7385e021c0b95a025f2c78384d57224e0120401
# 2023.2 use 04013814718e870261f27256216cd7da3eda6a5d
tool_version=$(vitis -v | grep -o "Vitis v20[1-9][0-9]\.[0-9] (64-bit)" | grep -o "v20[1-9][0-9]\.[0-9]")
if [[ "$tool_version" != "v20"[1-9][0-9]"."[0-9] ]] ; then
echo "Could not determine Vitis version"
exit 1
fi
atf_version=xilinx-$tool_version
if [[ "$atf_version" == "xilinx-v2021.1" ]];then atf_version="xlnx_rebase_v2.4_2021.1";fi
if [[ "$atf_version" == "xilinx-v2021.1.1" ]];then atf_version="xlnx_rebase_v2.4_2021.1_update1";fi
if [[ "$atf_version" == "xilinx-v2021.2" ]];then atf_version="xilinx-v2021.2";fi
if [[ "$atf_version" == "xilinx-v2022.2" ]];then atf_version="xilinx-v2022.2";fi
if [[ "$atf_version" == "xilinx-v2023.1" ]];then atf_version="xilinx-v2023.1";fi
if [[ "$atf_version" == "xilinx-v2023.2" ]];then atf_version="xilinx-v2023.2";fi
if [[ "$4" == "uart1" ]];then console="cadence1";else console="cadence0";fi
### Check if ATF_FILE is .elf or path to arm-trusted-firmware
if [ "$ATF_FILE" != "" ] && [ -d $ATF_FILE ]; then
### Build arm-trusted-firmware bl31.elf
(
cd $ATF_FILE
make distclean
git checkout $atf_version
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console
)
cp $ATF_FILE/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf
elif [ "$ATF_FILE" == "download" ]; then
(
command -v git >/dev/null 2>&1 || depends git
cd $BUILD_DIR
git clone https://github.com/Xilinx/arm-trusted-firmware.git
cd arm-trusted-firmware
git checkout $atf_version
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console
)
cp $BUILD_DIR/arm-trusted-firmware/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf
else
echo $ATF_FILE | grep -q -e "bl31.elf" || usage
if [ ! -f $ATF_FILE ]; then
echo $ATF_FILE: File not found!
usage
fi
cp $ATF_FILE $OUTPUT_DIR/bl31.elf
fi
cp "$XSA_FILE" "$BUILD_DIR/"
cp "$UBOOT_FILE" "$OUTPUT_DIR/u-boot.elf"
cp "$XSA_FILE" "$OUTPUT_DIR/"
### Get basename of xsa and bit file
XSA_FILE_BASENAME="$(basename $XSA_FILE)"
XSA_FILE_BASENAME_WO_EXT="$(basename $XSA_FILE .xsa)"
BIT_FILE_BASENAME="$XSA_FILE_BASENAME_WO_EXT.bit"
### Create create_fsbl_project.tcl file used by xsct to create the fsbl.
echo "hsi open_hw_design $XSA_FILE_BASENAME" > $BUILD_DIR/create_fsbl_project.tcl
echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl
echo "platform create -name hw0 -hw $XSA_FILE_BASENAME -os standalone -out ./build/sdk -proc \$cpu_name" >> $BUILD_DIR/create_fsbl_project.tcl
echo 'platform generate' >> $BUILD_DIR/create_fsbl_project.tcl
FSBL_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/fsbl.elf"
SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw0/hw/$BIT_FILE_BASENAME"
PMUFW_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/pmufw.elf"
### Create zynq.bif file used by bootgen
echo "the_ROM_image:" > $OUTPUT_DIR/zynq.bif
echo "{" >> $OUTPUT_DIR/zynq.bif
echo "[bootloader,destination_cpu=a53-0] fsbl.elf" >> $OUTPUT_DIR/zynq.bif
echo "[pmufw_image] pmufw.elf" >> $OUTPUT_DIR/zynq.bif
echo "[destination_device=pl] $BIT_FILE_BASENAME" >> $OUTPUT_DIR/zynq.bif
echo "[destination_cpu=a53-0,exception_level=el-3,trustzone] bl31.elf" >> $OUTPUT_DIR/zynq.bif
echo "[destination_cpu=a53-0, exception_level=el-2] u-boot.elf" >> $OUTPUT_DIR/zynq.bif
echo "}" >> $OUTPUT_DIR/zynq.bif
### Build fsbl.elf & pmufw.elf
(
cd $BUILD_DIR
xsct create_fsbl_project.tcl
)
### Copy fsbl and $BIT_FILE_BASENAME into the output folder
cp "$FSBL_PATH" "$OUTPUT_DIR/fsbl.elf"
cp "$SYSTEM_TOP_BIT_PATH" "$OUTPUT_DIR/$BIT_FILE_BASENAME"
cp "$PMUFW_PATH" "$OUTPUT_DIR/pmufw.elf"
### Build BOOT.BIN
(
cd $OUTPUT_DIR
bootgen -arch zynqmp -image zynq.bif -o BOOT.BIN -w
)
### Optionally tar.gz the entire output folder with the name given in argument 4/5
if [[ ( $4 == "uart"* && ${#5} -ne 0 ) ]]; then
tar czvf $5.tar.gz $OUTPUT_DIR
fi
if [[ ( ${#4} -ne 0 && $4 != "uart"* && ${#5} -eq 0 ) ]]; then
tar czvf $4.tar.gz $OUTPUT_DIR
fi
================================================
FILE: kernel_boot/kernel_config
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 5.15.36 Kernel Configuration
#
CONFIG_KERNEL_ALL_ADI_DRIVERS=y
CONFIG_CLK_ALL_ADI_DRIVERS=y
CONFIG_HWMON_ALL_ADI_DRIVERS=y
CONFIG_IIO_ALL_ADI_DRIVERS=y
CONFIG_INPUT_ALL_ADI_DRIVERS=y
CONFIG_MEDIA_ALL_ADI_DRIVERS=y
CONFIG_USB_ALL_ADI_DRIVERS=y
CONFIG_SND_SOC_ALL_ADI_CODECS=y
CONFIG_CC_VERSION_TEXT="arm-xilinx-linux-gnueabi-gcc.real (GCC) 10.2.0"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=100200
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=23500
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=23500
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
# CONFIG_KERNEL_LZ4 is not set
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_USELIB=y
# CONFIG_AUDIT is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem
CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
#
# BPF subsystem
#
# CONFIG_BPF_SYSCALL is not set
# CONFIG_BPF_JIT is not set
CONFIG_USERMODE_DRIVER=y
# end of BPF subsystem
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y
# CONFIG_SCHED_CORE is not set
#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting
CONFIG_CPU_ISOLATION=y
#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=15
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y
#
# Scheduler features
#
# end of Scheduler features
CONFIG_CGROUPS=y
# CONFIG_MEMCG is not set
# CONFIG_BLK_CGROUP is not set
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CGROUP_PIDS is not set
# CONFIG_CGROUP_RDMA is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CPUSETS is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_PERF is not set
# CONFIG_CGROUP_MISC is not set
# CONFIG_CGROUP_DEBUG is not set
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
CONFIG_RD_ZSTD=y
# CONFIG_BOOT_CONFIG is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_HAVE_FUTEX_CMPXCHG=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
# CONFIG_PC104 is not set
#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
CONFIG_SYSTEM_DATA_VERIFICATION=y
# CONFIG_PROFILING is not set
# end of General setup
CONFIG_ARM=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_GENERIC_BUG=y
CONFIG_PGTABLE_LEVELS=2
#
# System Type
#
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_BITS_MAX=16
CONFIG_ARCH_MULTIPLATFORM=y
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C24XX is not set
# CONFIG_ARCH_OMAP1 is not set
#
# Multiple platform selection
#
#
# CPU Core family selection
#
# CONFIG_ARCH_MULTI_V6 is not set
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MULTI_V6_V7=y
# end of Multiple platform selection
# CONFIG_ARCH_VIRT is not set
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_ARTPEC is not set
# CONFIG_ARCH_ASPEED is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_DIGICOLOR is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_HIGHBANK is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_KEYSTONE is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MILBEAUT is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_MSTARV7 is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NPCM is not set
#
# TI OMAP/AM/DM/DRA Family
#
# CONFIG_ARCH_OMAP3 is not set
# CONFIG_ARCH_OMAP4 is not set
# CONFIG_SOC_OMAP5 is not set
# CONFIG_SOC_AM33XX is not set
# CONFIG_SOC_AM43XX is not set
# CONFIG_SOC_DRA7XX is not set
# end of TI OMAP/AM/DM/DRA Family
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_RDA is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_PLAT_SPEAR is not set
# CONFIG_ARCH_STI is not set
# CONFIG_ARCH_STM32 is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_WM8850 is not set
CONFIG_ARCH_ZYNQ=y
#
# Xilinx Specific Options
#
CONFIG_XILINX_PREFETCH=y
# CONFIG_XILINX_RESET_CODE is not set
# end of Xilinx Specific Options
#
# Processor Type
#
CONFIG_CPU_V7=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
# CONFIG_ARM_LPAE is not set
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
CONFIG_ARM_VIRT_EXT=y
CONFIG_SWP_EMULATE=y
# CONFIG_CPU_BIG_ENDIAN is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_CPU_SPECTRE=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
# CONFIG_HARDEN_BRANCH_HISTORY is not set
CONFIG_KUSER_HELPERS=y
# CONFIG_VDSO is not set
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_CACHE_L2X0=y
# CONFIG_CACHE_L2X0_PMU is not set
CONFIG_PL310_ERRATA_588369=y
CONFIG_PL310_ERRATA_727915=y
# CONFIG_PL310_ERRATA_753970 is not set
CONFIG_PL310_ERRATA_769419=y
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
CONFIG_DEBUG_ALIGN_RODATA=y
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_643719 is not set
# CONFIG_ARM_ERRATA_720789 is not set
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_754327=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_ARM_ERRATA_775420=y
# CONFIG_ARM_ERRATA_798181 is not set
# CONFIG_ARM_ERRATA_773022 is not set
# CONFIG_ARM_ERRATA_818325_852422 is not set
# CONFIG_ARM_ERRATA_821420 is not set
# CONFIG_ARM_ERRATA_825619 is not set
# CONFIG_ARM_ERRATA_857271 is not set
# CONFIG_ARM_ERRATA_852421 is not set
# CONFIG_ARM_ERRATA_852423 is not set
# CONFIG_ARM_ERRATA_857272 is not set
# end of System Type
#
# Bus support
#
# CONFIG_ARM_ERRATA_814220 is not set
# end of Bus support
#
# Kernel Features
#
CONFIG_HAVE_SMP=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_ARM_CPU_TOPOLOGY=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_SMT=y
CONFIG_HAVE_ARM_SCU=y
# CONFIG_HAVE_ARM_ARCH_TIMER is not set
CONFIG_HAVE_ARM_TWD=y
# CONFIG_MCPM is not set
# CONFIG_BIG_LITTLE is not set
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_3G_OPT is not set
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_NR_CPUS=4
CONFIG_HOTPLUG_CPU=y
# CONFIG_ARM_PSCI is not set
CONFIG_ARCH_NR_GPIO=1024
CONFIG_HZ_FIXED=0
CONFIG_HZ_100=y
# CONFIG_HZ_200 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_500 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
# CONFIG_THUMB2_KERNEL is not set
CONFIG_ARM_PATCH_IDIV=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_CPU_SW_DOMAIN_PAN=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ARM_MODULE_PLTS=y
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_XEN is not set
# end of Kernel Features
#
# Boot options
#
CONFIG_USE_OF=y
CONFIG_ATAGS=y
# CONFIG_DEPRECATED_PARAM_STRUCT is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
# CONFIG_ARM_APPENDED_DTB is not set
CONFIG_CMDLINE="console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_EXTEND is not set
# CONFIG_CMDLINE_FORCE is not set
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_AUTO_ZRELADDR=y
# CONFIG_EFI is not set
# end of Boot options
#
# CPU Power Management
#
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
# end of CPU Frequency scaling
#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
#
# ARM CPU Idle Drivers
#
# CONFIG_ARM_CPUIDLE is not set
CONFIG_ARM_ZYNQ_CPUIDLE=y
# end of ARM CPU Idle Drivers
# end of CPU Idle
# end of CPU Power Management
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_NEON=y
# CONFIG_KERNEL_MODE_NEON is not set
# end of Floating point emulation
#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
# CONFIG_APM_EMULATION is not set
CONFIG_PM_CLK=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_CPU_PM=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
# end of Power management options
# CONFIG_ARM_CRYPTO is not set
CONFIG_AS_VFP_VMRS_FPINST=y
#
# General architecture-dependent options
#
# CONFIG_KPROBES is not set
# CONFIG_JUMP_LABEL is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=8
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_HAVE_ARCH_PFN_VALID=y
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling
CONFIG_HAVE_GCC_PLUGINS=y
# CONFIG_GCC_PLUGINS is not set
# end of General architecture-dependent options
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
# CONFIG_BLK_DEV_ZONED is not set
# CONFIG_BLK_WBT is not set
CONFIG_BLK_DEBUG_FS=y
# CONFIG_BLK_SED_OPAL is not set
# CONFIG_BLK_INLINE_ENCRYPTION is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_EFI_PARTITION=y
# end of Partition Types
CONFIG_BLK_PM=y
#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
# CONFIG_IOSCHED_BFQ is not set
# end of IO Schedulers
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_FREEZER=y
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_ELF_FDPIC is not set
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
CONFIG_ARCH_HAS_BINFMT_FLAT=y
# CONFIG_BINFMT_FLAT is not set
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
# CONFIG_BINFMT_MISC is not set
CONFIG_COREDUMP=y
# end of Executable file formats
#
# Memory Management options
#
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_COMPACTION is not set
# CONFIG_PAGE_REPORTING is not set
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_BOUNCE=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
# CONFIG_CLEANCACHE is not set
# CONFIG_FRONTSWAP is not set
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
# CONFIG_ZPOOL is not set
# CONFIG_ZSMALLOC is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_IDLE_PAGE_TRACKING is not set
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
CONFIG_KMAP_LOCAL=y
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options
CONFIG_NET=y
CONFIG_NET_INGRESS=y
CONFIG_SKB_EXTENSIONS=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_TLS is not set
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_INTERFACE is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=y
# CONFIG_NET_IPGRE_DEMUX is not set
CONFIG_NET_IP_TUNNEL=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
# CONFIG_IP_PIMSM_V1 is not set
# CONFIG_IP_PIMSM_V2 is not set
# CONFIG_SYN_COOKIES is not set
CONFIG_NET_IPVTI=y
# CONFIG_NET_FOU is not set
# CONFIG_NET_FOU_IP_TUNNELS is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_INET_UDP_DIAG is not set
# CONFIG_INET_RAW_DIAG is not set
# CONFIG_INET_DIAG_DESTROY is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
CONFIG_IPV6_ILA=y
# CONFIG_IPV6_VTI is not set
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
# CONFIG_IPV6_TUNNEL is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_IPV6_MROUTE is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
# CONFIG_BRIDGE_NETFILTER is not set
#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
# CONFIG_NETFILTER_NETLINK_ACCT is not set
# CONFIG_NETFILTER_NETLINK_QUEUE is not set
CONFIG_NETFILTER_NETLINK_LOG=y
# CONFIG_NETFILTER_NETLINK_OSF is not set
CONFIG_NF_CONNTRACK=m
CONFIG_NF_LOG_SYSLOG=y
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_ZONES is not set
CONFIG_NF_CONNTRACK_PROCFS=y
# CONFIG_NF_CONNTRACK_EVENTS is not set
# CONFIG_NF_CONNTRACK_TIMEOUT is not set
# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
# CONFIG_NF_CONNTRACK_LABELS is not set
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
# CONFIG_NF_CONNTRACK_AMANDA is not set
# CONFIG_NF_CONNTRACK_FTP is not set
# CONFIG_NF_CONNTRACK_H323 is not set
# CONFIG_NF_CONNTRACK_IRC is not set
# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
# CONFIG_NF_CONNTRACK_SNMP is not set
# CONFIG_NF_CONNTRACK_PPTP is not set
# CONFIG_NF_CONNTRACK_SANE is not set
# CONFIG_NF_CONNTRACK_SIP is not set
# CONFIG_NF_CONNTRACK_TFTP is not set
CONFIG_NF_CT_NETLINK=m
# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set
# CONFIG_NF_NAT is not set
# CONFIG_NF_TABLES is not set
CONFIG_NETFILTER_XTABLES=y
#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=m
#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y
# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
# CONFIG_NETFILTER_XT_TARGET_HL is not set
# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
# CONFIG_NETFILTER_XT_TARGET_LED is not set
CONFIG_NETFILTER_XT_TARGET_LOG=y
# CONFIG_NETFILTER_XT_TARGET_MARK is not set
# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
# CONFIG_NETFILTER_XT_TARGET_TEE is not set
# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
#
# Xtables matches
#
# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
# CONFIG_NETFILTER_XT_MATCH_BPF is not set
# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set
# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set
# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
# CONFIG_NETFILTER_XT_MATCH_CPU is not set
# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
# CONFIG_NETFILTER_XT_MATCH_ECN is not set
# CONFIG_NETFILTER_XT_MATCH_ESP is not set
# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
# CONFIG_NETFILTER_XT_MATCH_HL is not set
# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
# CONFIG_NETFILTER_XT_MATCH_MARK is not set
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
# CONFIG_NETFILTER_XT_MATCH_OSF is not set
# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
# CONFIG_NETFILTER_XT_MATCH_REALM is not set
# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
CONFIG_NETFILTER_XT_MATCH_STATE=m
# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
# CONFIG_NETFILTER_XT_MATCH_STRING is not set
# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
# CONFIG_NETFILTER_XT_MATCH_TIME is not set
# CONFIG_NETFILTER_XT_MATCH_U32 is not set
# end of Core Netfilter Configuration
# CONFIG_IP_SET is not set
# CONFIG_IP_VS is not set
#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=m
# CONFIG_NF_SOCKET_IPV4 is not set
# CONFIG_NF_TPROXY_IPV4 is not set
# CONFIG_NF_DUP_IPV4 is not set
# CONFIG_NF_LOG_ARP is not set
# CONFIG_NF_LOG_IPV4 is not set
CONFIG_NF_REJECT_IPV4=y
CONFIG_IP_NF_IPTABLES=y
# CONFIG_IP_NF_MATCH_AH is not set
# CONFIG_IP_NF_MATCH_ECN is not set
# CONFIG_IP_NF_MATCH_RPFILTER is not set
# CONFIG_IP_NF_MATCH_TTL is not set
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
# CONFIG_IP_NF_TARGET_SYNPROXY is not set
# CONFIG_IP_NF_NAT is not set
CONFIG_IP_NF_MANGLE=y
# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
# CONFIG_IP_NF_TARGET_ECN is not set
# CONFIG_IP_NF_TARGET_TTL is not set
# CONFIG_IP_NF_RAW is not set
# CONFIG_IP_NF_ARPTABLES is not set
# end of IP: Netfilter Configuration
#
# IPv6: Netfilter Configuration
#
# CONFIG_NF_SOCKET_IPV6 is not set
# CONFIG_NF_TPROXY_IPV6 is not set
# CONFIG_NF_DUP_IPV6 is not set
CONFIG_NF_REJECT_IPV6=y
CONFIG_NF_LOG_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
# CONFIG_IP6_NF_MATCH_AH is not set
# CONFIG_IP6_NF_MATCH_EUI64 is not set
# CONFIG_IP6_NF_MATCH_FRAG is not set
# CONFIG_IP6_NF_MATCH_OPTS is not set
# CONFIG_IP6_NF_MATCH_HL is not set
# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
# CONFIG_IP6_NF_MATCH_MH is not set
# CONFIG_IP6_NF_MATCH_RPFILTER is not set
# CONFIG_IP6_NF_MATCH_RT is not set
# CONFIG_IP6_NF_MATCH_SRH is not set
# CONFIG_IP6_NF_TARGET_HL is not set
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
# CONFIG_IP6_NF_TARGET_SYNPROXY is not set
CONFIG_IP6_NF_MANGLE=y
# CONFIG_IP6_NF_RAW is not set
# CONFIG_IP6_NF_NAT is not set
# end of IPv6: Netfilter Configuration
CONFIG_NF_DEFRAG_IPV6=m
# CONFIG_NF_CONNTRACK_BRIDGE is not set
CONFIG_BRIDGE_NF_EBTABLES=y
# CONFIG_BRIDGE_EBT_BROUTE is not set
CONFIG_BRIDGE_EBT_T_FILTER=y
CONFIG_BRIDGE_EBT_T_NAT=y
# CONFIG_BRIDGE_EBT_802_3 is not set
# CONFIG_BRIDGE_EBT_AMONG is not set
# CONFIG_BRIDGE_EBT_ARP is not set
# CONFIG_BRIDGE_EBT_IP is not set
# CONFIG_BRIDGE_EBT_IP6 is not set
# CONFIG_BRIDGE_EBT_LIMIT is not set
# CONFIG_BRIDGE_EBT_MARK is not set
# CONFIG_BRIDGE_EBT_PKTTYPE is not set
# CONFIG_BRIDGE_EBT_STP is not set
# CONFIG_BRIDGE_EBT_VLAN is not set
# CONFIG_BRIDGE_EBT_ARPREPLY is not set
# CONFIG_BRIDGE_EBT_DNAT is not set
CONFIG_BRIDGE_EBT_MARK_T=y
# CONFIG_BRIDGE_EBT_REDIRECT is not set
# CONFIG_BRIDGE_EBT_SNAT is not set
# CONFIG_BRIDGE_EBT_LOG is not set
# CONFIG_BRIDGE_EBT_NFLOG is not set
CONFIG_BPFILTER=y
CONFIG_BPFILTER_UMH=m
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
CONFIG_STP=y
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
# CONFIG_BRIDGE_MRP is not set
# CONFIG_BRIDGE_CFM is not set
CONFIG_NET_DSA=y
# CONFIG_NET_DSA_TAG_AR9331 is not set
# CONFIG_NET_DSA_TAG_BRCM is not set
# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set
# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set
# CONFIG_NET_DSA_TAG_HELLCREEK is not set
# CONFIG_NET_DSA_TAG_GSWIP is not set
# CONFIG_NET_DSA_TAG_DSA is not set
# CONFIG_NET_DSA_TAG_EDSA is not set
# CONFIG_NET_DSA_TAG_MTK is not set
# CONFIG_NET_DSA_TAG_KSZ is not set
# CONFIG_NET_DSA_TAG_RTL4_A is not set
# CONFIG_NET_DSA_TAG_OCELOT is not set
# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
# CONFIG_NET_DSA_TAG_QCA is not set
# CONFIG_NET_DSA_TAG_LAN9303 is not set
# CONFIG_NET_DSA_TAG_SJA1105 is not set
# CONFIG_NET_DSA_TAG_TRAILER is not set
# CONFIG_NET_DSA_TAG_XRS700X is not set
CONFIG_VLAN_8021Q=m
# CONFIG_VLAN_8021Q_GVRP is not set
# CONFIG_VLAN_8021Q_MVRP is not set
# CONFIG_DECNET is not set
CONFIG_LLC=y
# CONFIG_LLC2 is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_6LOWPAN is not set
CONFIG_IEEE802154=y
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=y
CONFIG_MAC802154=y
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=y
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
# CONFIG_BATMAN_ADV_NC is not set
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
# CONFIG_NET_L3_MASTER_DEV is not set
# CONFIG_QRTR is not set
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_NET_FLOW_LIMIT=y
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# end of Network testing
# end of Networking options
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
# CONFIG_MCTP is not set
CONFIG_WIRELESS=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_CFG80211=y
CONFIG_NL80211_TESTMODE=y
CONFIG_CFG80211_DEVELOPER_WARNINGS=y
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set
# CONFIG_CFG80211_REG_RELAX_NO_IR is not set
CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_DEBUGFS=y
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_MAC80211=y
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_MAC80211_DEBUGFS=y
CONFIG_MAC80211_MESSAGE_TRACING=y
CONFIG_MAC80211_DEBUG_MENU=y
# CONFIG_MAC80211_NOINLINE is not set
CONFIG_MAC80211_VERBOSE_DEBUG=y
CONFIG_MAC80211_MLME_DEBUG=y
CONFIG_MAC80211_STA_DEBUG=y
CONFIG_MAC80211_HT_DEBUG=y
# CONFIG_MAC80211_OCB_DEBUG is not set
# CONFIG_MAC80211_IBSS_DEBUG is not set
CONFIG_MAC80211_PS_DEBUG=y
# CONFIG_MAC80211_MPL_DEBUG is not set
# CONFIG_MAC80211_MPATH_DEBUG is not set
# CONFIG_MAC80211_MHWMP_DEBUG is not set
# CONFIG_MAC80211_MESH_SYNC_DEBUG is not set
# CONFIG_MAC80211_MESH_CSA_DEBUG is not set
# CONFIG_MAC80211_MESH_PS_DEBUG is not set
# CONFIG_MAC80211_TDLS_DEBUG is not set
CONFIG_MAC80211_DEBUG_COUNTERS=y
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
# CONFIG_NET_IFE is not set
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_DEVLINK=y
# CONFIG_FAILOVER is not set
CONFIG_ETHTOOL_NETLINK=y
#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
# CONFIG_PCI is not set
# CONFIG_PCCARD is not set
#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_EXTRA_FIRMWARE="ad9467_intbypass_ad9517.stp ad9517.stp ad9517_fmcomms6.stp adau1761.bin imageon_edid.bin pzsdr-fmc-ad9517.stp Mykonos_M3.bin TaliseStream.bin TaliseTDDArmFirmware.bin TaliseTxArmFirmware.bin TaliseRxArmFirmware.bin Navassa_EvaluationFw.bin RxGainTable.csv RxGainTable_GainCompensated.csv ORxGainTable.csv TxAttenTable.csv Navassa_Stream.bin Navassa_CMOS_profile.json Navassa_LVDS_profile.json Navassa_CMOS_profile_adrv9003.json Navassa_LVDS_profile_adrv9003.json"
CONFIG_EXTRA_FIRMWARE_DIR="./firmware"
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
CONFIG_FW_CACHE=y
# end of Firmware loader
CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options
#
# Bus devices
#
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
# CONFIG_VEXPRESS_CONFIG is not set
# CONFIG_MHI_BUS is not set
# end of Bus devices
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
#
# Firmware Drivers
#
#
# ARM System Control and Management Interface Protocol
#
# CONFIG_ARM_SCMI_PROTOCOL is not set
# end of ARM System Control and Management Interface Protocol
# CONFIG_FIRMWARE_MEMMAP is not set
# CONFIG_FW_CFG_SYSFS is not set
# CONFIG_TRUSTED_FOUNDATIONS is not set
# CONFIG_GOOGLE_FIRMWARE is not set
CONFIG_HAVE_ARM_SMCCC=y
#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers
# CONFIG_GNSS is not set
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set
#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers
#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
# CONFIG_MTD_PHYSMAP_COMPAT is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PHYSMAP_VERSATILE is not set
# CONFIG_MTD_PHYSMAP_GEMINI is not set
# CONFIG_MTD_PHYSMAP_IXP4XX is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers
#
# NAND
#
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set
#
# ECC engine support
#
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
# end of ECC engine support
# end of NAND
#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# CONFIG_MTD_LPDDR2_NVM is not set
# end of LPDDR & LPDDR2 PCM memory drivers
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
# CONFIG_MTD_UBI is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_CONFIGFS=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_BLK_DEV_RBD is not set
#
# NVME Support
#
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TCP is not set
# CONFIG_NVME_TARGET is not set
# end of NVME Support
#
# Misc devices
#
CONFIG_AD525X_DPOT=y
CONFIG_AD525X_DPOT_I2C=y
CONFIG_AD525X_DPOT_SPI=y
CONFIG_ADI_AXI_DATA_OFFLOAD=y
CONFIG_ADI_AXI_TDD=y
# CONFIG_DUMMY_IRQ is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
# CONFIG_SRAM is not set
# CONFIG_XILINX_SDFEC is not set
# CONFIG_XILINX_FLEX_PM is not set
# CONFIG_XILINX_TRAFGEN is not set
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_XILINX_JESD204B is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support
#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
#
# MathWorks IP Drivers
#
CONFIG_MATHWORKS_IP_CORE=y
CONFIG_MWIPCORE=y
CONFIG_MWIPCORE_DMA_STREAMING=y
CONFIG_MWIPCORE_IIO_STREAMING=y
CONFIG_MWIPCORE_IIO_MM=y
CONFIG_MWIPCORE_IIO_SHAREDMEM=y
CONFIG_MATHWORKS_GENERIC_OF=y
# end of MathWorks IP Drivers
# CONFIG_ECHO is not set
# CONFIG_MISC_RTSX_USB is not set
# CONFIG_PVPANIC is not set
# end of Misc devices
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_BLK_DEV_SR is not set
CONFIG_CHR_DEV_SG=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_DH is not set
# end of SCSI device support
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_TARGET_CORE is not set
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_WIREGUARD is not set
# CONFIG_EQUALIZER is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_IPVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_GENEVE is not set
# CONFIG_BAREUDP is not set
# CONFIG_GTP is not set
CONFIG_MACSEC=y
# CONFIG_NETCONSOLE is not set
CONFIG_TUN=y
# CONFIG_TUN_VNET_CROSS_LE is not set
# CONFIG_VETH is not set
# CONFIG_NLMON is not set
#
# Distributed Switch Architecture drivers
#
# CONFIG_B53 is not set
# CONFIG_NET_DSA_BCM_SF2 is not set
# CONFIG_NET_DSA_LOOP is not set
# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
# CONFIG_NET_DSA_MT7530 is not set
# CONFIG_NET_DSA_MV88E6060 is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set
# CONFIG_NET_DSA_MV88E6XXX is not set
# CONFIG_NET_DSA_MSCC_SEVILLE is not set
# CONFIG_NET_DSA_AR9331 is not set
# CONFIG_NET_DSA_SJA1105 is not set
# CONFIG_NET_DSA_XRS700X_I2C is not set
# CONFIG_NET_DSA_XRS700X_MDIO is not set
# CONFIG_NET_DSA_QCA8K is not set
# CONFIG_NET_DSA_REALTEK_SMI is not set
# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
# end of Distributed Switch Architecture drivers
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_ALACRITECH=y
# CONFIG_ALTERA_TSE is not set
CONFIG_NET_VENDOR_AMAZON=y
CONFIG_NET_VENDOR_AQUANTIA=y
CONFIG_NET_VENDOR_ARC=y
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_NET_VENDOR_CADENCE=y
CONFIG_MACB=y
CONFIG_MACB_USE_HWSTAMP=y
CONFIG_NET_VENDOR_CAVIUM=y
# CONFIG_NET_VENDOR_CIRRUS is not set
CONFIG_NET_VENDOR_CORTINA=y
# CONFIG_GEMINI_ETHERNET is not set
# CONFIG_DM9000 is not set
# CONFIG_DNET is not set
CONFIG_NET_VENDOR_EZCHIP=y
# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
# CONFIG_NET_VENDOR_FARADAY is not set
CONFIG_NET_VENDOR_GOOGLE=y
CONFIG_NET_VENDOR_HISILICON=y
# CONFIG_HIX5HD2_GMAC is not set
# CONFIG_HISI_FEMAC is not set
# CONFIG_HIP04_ETH is not set
# CONFIG_HNS_DSAF is not set
# CONFIG_HNS_ENET is not set
CONFIG_NET_VENDOR_HUAWEI=y
# CONFIG_NET_VENDOR_INTEL is not set
CONFIG_NET_VENDOR_ADI=y
CONFIG_ADIN1110=y
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_NET_VENDOR_MELLANOX=y
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
CONFIG_NET_VENDOR_MICROSEMI=y
# CONFIG_MSCC_OCELOT_SWITCH is not set
CONFIG_NET_VENDOR_MICROSOFT=y
CONFIG_NET_VENDOR_NI=y
# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_ETHOC is not set
CONFIG_NET_VENDOR_PENSANDO=y
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCOM_EMAC is not set
# CONFIG_RMNET is not set
CONFIG_NET_VENDOR_RENESAS=y
CONFIG_NET_VENDOR_ROCKER=y
CONFIG_NET_VENDOR_SAMSUNG=y
# CONFIG_SXGBE_ETH is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_NET_VENDOR_SOLARFLARE=y
# CONFIG_NET_VENDOR_SMSC is not set
CONFIG_NET_VENDOR_SOCIONEXT=y
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NET_VENDOR_XILINX=y
# CONFIG_XILINX_EMACLITE is not set
# CONFIG_XILINX_AXI_EMAC is not set
# CONFIG_XILINX_LL_TEMAC is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set
#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
CONFIG_ADIN_PHY=y
CONFIG_ADIN1100_PHY=y
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=y
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
CONFIG_MARVELL_PHY=y
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
# CONFIG_MEDIATEK_GE_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_MICROCHIP_PHY is not set
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_MOTORCOMM_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_RENESAS_PHY is not set
# CONFIG_ROCKCHIP_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_PHY is not set
CONFIG_XILINX_GMII2RGMII=y
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_BITBANG=y
# CONFIG_MDIO_BCM_UNIMAC is not set
# CONFIG_MDIO_GPIO is not set
# CONFIG_MDIO_HISI_FEMAC is not set
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_IPQ4019 is not set
# CONFIG_MDIO_IPQ8064 is not set
#
# MDIO Multiplexers
#
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
#
# PCS device drivers
#
# CONFIG_PCS_XPCS is not set
# end of PCS device drivers
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
CONFIG_USB_NET_DRIVERS=y
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_LAN78XX is not set
CONFIG_USB_USBNET=y
CONFIG_USB_NET_AX8817X=y
CONFIG_USB_NET_AX88179_178A=y
CONFIG_USB_NET_CDCETHER=y
# CONFIG_USB_NET_CDC_EEM is not set
CONFIG_USB_NET_CDC_NCM=y
# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
# CONFIG_USB_NET_CDC_MBIM is not set
# CONFIG_USB_NET_DM9601 is not set
# CONFIG_USB_NET_SR9700 is not set
# CONFIG_USB_NET_SR9800 is not set
# CONFIG_USB_NET_SMSC75XX is not set
# CONFIG_USB_NET_SMSC95XX is not set
# CONFIG_USB_NET_GL620A is not set
CONFIG_USB_NET_NET1080=y
# CONFIG_USB_NET_PLUSB is not set
# CONFIG_USB_NET_MCS7830 is not set
# CONFIG_USB_NET_RNDIS_HOST is not set
CONFIG_USB_NET_CDC_SUBSET_ENABLE=y
CONFIG_USB_NET_CDC_SUBSET=y
# CONFIG_USB_ALI_M5632 is not set
# CONFIG_USB_AN2720 is not set
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
# CONFIG_USB_EPSON2888 is not set
# CONFIG_USB_KC2190 is not set
CONFIG_USB_NET_ZAURUS=y
# CONFIG_USB_NET_CX82310_ETH is not set
# CONFIG_USB_NET_KALMIA is not set
# CONFIG_USB_NET_QMI_WWAN is not set
# CONFIG_USB_NET_INT51X1 is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_USB_SIERRA_NET is not set
# CONFIG_USB_VL600 is not set
# CONFIG_USB_NET_CH9200 is not set
# CONFIG_USB_NET_AQC111 is not set
# CONFIG_USB_RTL8153_ECM is not set
# CONFIG_WLAN is not set
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=y
# CONFIG_IEEE802154_FAKELB is not set
# CONFIG_IEEE802154_AT86RF230 is not set
# CONFIG_IEEE802154_MRF24J40 is not set
# CONFIG_IEEE802154_CC2520 is not set
# CONFIG_IEEE802154_ATUSB is not set
CONFIG_IEEE802154_ADF7242=y
# CONFIG_IEEE802154_CA8210 is not set
# CONFIG_IEEE802154_MCR20A is not set
# CONFIG_IEEE802154_HWSIM is not set
#
# Wireless WAN
#
# CONFIG_WWAN is not set
# end of Wireless WAN
# CONFIG_NETDEVSIM is not set
# CONFIG_NET_FAILOVER is not set
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_SPARSEKMAP=y
# CONFIG_INPUT_MATRIXKMAP is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
CONFIG_KEYBOARD_ADP5520=y
CONFIG_KEYBOARD_ADP5588=y
CONFIG_KEYBOARD_ADP5589=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_MOUSE_SYNAPTICS_USB is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_AD7877=y
CONFIG_TOUCHSCREEN_AD7879=y
CONFIG_TOUCHSCREEN_AD7879_I2C=y
CONFIG_TOUCHSCREEN_AD7879_SPI=y
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_ILITEK is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MSG2638 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AD714X=y
CONFIG_INPUT_AD714X_I2C=y
CONFIG_INPUT_AD714X_SPI=y
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MMA8450 is not set
# CONFIG_INPUT_GPIO_BEEPER is not set
# CONFIG_INPUT_GPIO_DECODER is not set
# CONFIG_INPUT_GPIO_VIBRA is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
# CONFIG_INPUT_UINPUT is not set
CONFIG_INPUT_PCF8574=y
# CONFIG_INPUT_PWM_BEEPER is not set
# CONFIG_INPUT_PWM_VIBRA is not set
CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
# CONFIG_RMI4_CORE is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_AMBAKMI is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
# CONFIG_GAMEPORT is not set
# end of Hardware I/O ports
# end of Input device support
#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LDISC_AUTOLOAD=y
#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_AMBA_PL010 is not set
# CONFIG_SERIAL_AMBA_PL011 is not set
# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_BCM63XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
CONFIG_SERIAL_XILINX_PS_UART=y
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_ST_ASC is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NULL_TTY is not set
# CONFIG_HVC_DCC is not set
# CONFIG_SERIAL_DEV_BUS is not set
# CONFIG_TTY_PRINTK is not set
# CONFIG_VIRTIO_CONSOLE is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
CONFIG_DEVMEM=y
# CONFIG_TCG_TPM is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
CONFIG_AXI_INTR_MONITOR=y
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
# end of Character devices
#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
#
# Multiplexer I2C Chip support
#
# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
# CONFIG_I2C_MUX_GPIO is not set
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=y
# CONFIG_I2C_MUX_PCA9541 is not set
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_I2C_MUX_PINCTRL is not set
# CONFIG_I2C_MUX_REG is not set
# CONFIG_I2C_DEMUX_PINCTRL is not set
# CONFIG_I2C_MUX_MLXCPLD is not set
# end of Multiplexer I2C Chip support
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y
#
# I2C Hardware Bus support
#
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_CADENCE=y
# CONFIG_I2C_CBUS_GPIO is not set
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_RK3X is not set
# CONFIG_I2C_SIMTEC is not set
CONFIG_I2C_XILINX=y
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_VIRTIO is not set
# end of I2C Hardware Bus support
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_SLAVE is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support
# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
CONFIG_SPI_AXI_SPI_ENGINE=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_CADENCE=y
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_ROCKCHIP is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_MXIC is not set
CONFIG_SPI_XCOMM=y
CONFIG_SPI_AD9250FMC=y
CONFIG_SPI_XILINX=y
CONFIG_SPI_ZYNQ_QSPI=y
# CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPI_AMD is not set
#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set
#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
# CONFIG_NTP_PPS is not set
#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set
#
# PPS generators support
#
#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
# CONFIG_DP83640_PHY is not set
# CONFIG_PTP_1588_CLOCK_INES is not set
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_XILINX is not set
# end of PTP clock support
CONFIG_PINCTRL=y
CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_MCP23S08 is not set
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_SX150X is not set
# CONFIG_PINCTRL_STMFX is not set
CONFIG_PINCTRL_ZYNQ=y
# CONFIG_PINCTRL_OCELOT is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
# CONFIG_GPIO_GENERIC_PLATFORM is not set
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
# CONFIG_GPIO_MPC8XXX is not set
# CONFIG_GPIO_PL061 is not set
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
# CONFIG_GPIO_SIFIVE is not set
# CONFIG_GPIO_SYSCON is not set
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_ZEVIO is not set
CONFIG_GPIO_ZYNQ=y
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers
#
# I2C GPIO expanders
#
CONFIG_GPIO_ADP5588=y
CONFIG_GPIO_ADP5588_IRQ=y
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
CONFIG_GPIO_PCA953X=y
# CONFIG_GPIO_PCA953X_IRQ is not set
# CONFIG_GPIO_PCA9570 is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_SLG7XL45106 is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders
#
# MFD GPIO expanders
#
CONFIG_GPIO_ADP5520=y
# CONFIG_HTC_EGPIO is not set
# end of MFD GPIO expanders
#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
CONFIG_GPIO_ADI_DAQ1=y
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders
#
# USB GPIO expanders
#
# end of USB GPIO expanders
#
# Virtual GPIO drivers
#
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
# end of Virtual GPIO drivers
# CONFIG_W1 is not set
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMKONA is not set
# CONFIG_POWER_RESET_BRCMSTB is not set
CONFIG_POWER_RESET_GPIO=y
# CONFIG_POWER_RESET_GPIO_RESTART is not set
CONFIG_POWER_RESET_LTC2952=y
# CONFIG_POWER_RESET_REGULATOR is not set
CONFIG_POWER_RESET_RESTART=y
# CONFIG_POWER_RESET_VERSATILE is not set
# CONFIG_POWER_RESET_SYSCON is not set
# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
# CONFIG_SYSCON_REBOOT_MODE is not set
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_TEST_POWER is not set
CONFIG_CHARGER_ADP5061=y
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
CONFIG_CHARGER_LT3651=y
CONFIG_CHARGER_LTC4162L=y
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_BQ256XX is not set
# CONFIG_CHARGER_SMB347 is not set
CONFIG_BATTERY_GAUGE_LTC2941=y
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Native drivers
#
CONFIG_SENSORS_AD7314=y
CONFIG_SENSORS_AD7414=y
CONFIG_SENSORS_AD7418=y
CONFIG_SENSORS_ADM1021=y
CONFIG_SENSORS_ADM1025=y
CONFIG_SENSORS_ADM1026=y
CONFIG_SENSORS_ADM1029=y
CONFIG_SENSORS_ADM1031=y
CONFIG_SENSORS_ADM1177=y
CONFIG_SENSORS_ADM9240=y
CONFIG_SENSORS_ADT7X10=y
CONFIG_SENSORS_ADT7310=y
CONFIG_SENSORS_ADT7410=y
CONFIG_SENSORS_ADT7411=y
CONFIG_SENSORS_ADT7462=y
CONFIG_SENSORS_ADT7470=y
CONFIG_SENSORS_ADT7475=y
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
CONFIG_SENSORS_AXI_FAN_CONTROL=y
# CONFIG_SENSORS_ASPEED is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
# CONFIG_SENSORS_GPIO_FAN is not set
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IIO_HWMON is not set
# CONFIG_SENSORS_IT87 is not set
CONFIG_SENSORS_JC42=y
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
CONFIG_SENSORS_LTC2945=y
CONFIG_SENSORS_LTC2947=y
CONFIG_SENSORS_LTC2947_I2C=y
CONFIG_SENSORS_LTC2947_SPI=y
CONFIG_SENSORS_LTC2990=y
CONFIG_SENSORS_LTC2992=y
CONFIG_SENSORS_LTC4151=y
CONFIG_SENSORS_LTC4215=y
CONFIG_SENSORS_LTC4222=y
CONFIG_SENSORS_LTC4245=y
CONFIG_SENSORS_LTC4260=y
CONFIG_SENSORS_LTC4261=y
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
CONFIG_MAX31827=y
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
CONFIG_SENSORS_LM87=y
CONFIG_SENSORS_LM90=y
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_PCF8591 is not set
CONFIG_PMBUS=y
CONFIG_SENSORS_PMBUS=y
CONFIG_SENSORS_ADM1266=y
CONFIG_SENSORS_ADM1275=y
# CONFIG_SENSORS_BEL_PFE is not set
# CONFIG_SENSORS_BPA_RS600 is not set
# CONFIG_SENSORS_FSP_3Y is not set
# CONFIG_SENSORS_IBM_CFFPS is not set
# CONFIG_SENSORS_DPS920AB is not set
# CONFIG_SENSORS_INSPUR_IPSPS is not set
# CONFIG_SENSORS_IR35221 is not set
# CONFIG_SENSORS_IR36021 is not set
# CONFIG_SENSORS_IR38064 is not set
# CONFIG_SENSORS_IRPS5401 is not set
# CONFIG_SENSORS_ISL68137 is not set
# CONFIG_SENSORS_LM25066 is not set
CONFIG_SENSORS_LTC2978=y
CONFIG_SENSORS_LTC2978_REGULATOR=y
CONFIG_SENSORS_LTC3815=y
# CONFIG_SENSORS_MAX15301 is not set
# CONFIG_SENSORS_MAX16064 is not set
# CONFIG_SENSORS_MAX16601 is not set
# CONFIG_SENSORS_MAX20730 is not set
# CONFIG_SENSORS_MAX20751 is not set
# CONFIG_SENSORS_MAX31785 is not set
# CONFIG_SENSORS_MAX34440 is not set
# CONFIG_SENSORS_MAX8688 is not set
# CONFIG_SENSORS_MP2888 is not set
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_PIM4328 is not set
# CONFIG_SENSORS_PM6764TR is not set
# CONFIG_SENSORS_PXE1610 is not set
# CONFIG_SENSORS_Q54SJ108A2 is not set
# CONFIG_SENSORS_STPDDC60 is not set
# CONFIG_SENSORS_TPS40422 is not set
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_TPS544 is not set
CONFIG_SENSORS_UCD9000=y
CONFIG_SENSORS_UCD9200=y
# CONFIG_SENSORS_XDPE122 is not set
# CONFIG_SENSORS_ZL6100 is not set
# CONFIG_SENSORS_PWM_FAN is not set
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHT4x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
# CONFIG_THERMAL_WRITABLE_TRIPS is not set
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_CPU_THERMAL is not set
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_THERMAL_MMIO is not set
# CONFIG_GENERIC_ADC_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_GPIO_WATCHDOG is not set
CONFIG_XILINX_WATCHDOG=y
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
CONFIG_CADENCE_WATCHDOG=y
# CONFIG_FTWDT010_WATCHDOG is not set
# CONFIG_DW_WATCHDOG is not set
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_MEN_A21_WDT is not set
#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
# CONFIG_BCMA is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
CONFIG_PMIC_ADP5520=y
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_PM8XXX is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_RK808 is not set
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
CONFIG_REGULATOR_AD5398=y
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_FAN53880 is not set
# CONFIG_REGULATOR_GPIO is not set
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
CONFIG_REGULATOR_LTC3589=y
CONFIG_REGULATOR_LTC3676=y
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_PCA9450 is not set
# CONFIG_REGULATOR_PF8X00 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
# CONFIG_REGULATOR_PWM is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_REGULATOR_VCTRL is not set
# CONFIG_RC_CORE is not set
CONFIG_CEC_CORE=y
CONFIG_MEDIA_CEC_SUPPORT=y
# CONFIG_CEC_CH7322 is not set
# CONFIG_CEC_GPIO is not set
# CONFIG_USB_PULSE8_CEC is not set
# CONFIG_USB_RAINSHADOW_CEC is not set
CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_SUPPORT_FILTER is not set
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types
#
# Media core support
#
CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=y
# end of Media core support
#
# Video4Linux options
#
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
# end of Video4Linux options
#
# Media controller options
#
# CONFIG_MEDIA_CONTROLLER_DVB is not set
# end of Media controller options
#
# Digital TV options
#
# CONFIG_DVB_MMAP is not set
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=16
CONFIG_DVB_DYNAMIC_MINORS=y
# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
# CONFIG_DVB_ULE_DEBUG is not set
# end of Digital TV options
#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y
#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=y
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
CONFIG_USB_GSPCA=y
# CONFIG_USB_M5602 is not set
# CONFIG_USB_STV06XX is not set
# CONFIG_USB_GL860 is not set
# CONFIG_USB_GSPCA_BENQ is not set
# CONFIG_USB_GSPCA_CONEX is not set
# CONFIG_USB_GSPCA_CPIA1 is not set
# CONFIG_USB_GSPCA_DTCS033 is not set
# CONFIG_USB_GSPCA_ETOMS is not set
# CONFIG_USB_GSPCA_FINEPIX is not set
# CONFIG_USB_GSPCA_JEILINJ is not set
# CONFIG_USB_GSPCA_JL2005BCD is not set
# CONFIG_USB_GSPCA_KINECT is not set
# CONFIG_USB_GSPCA_KONICA is not set
# CONFIG_USB_GSPCA_MARS is not set
# CONFIG_USB_GSPCA_MR97310A is not set
# CONFIG_USB_GSPCA_NW80X is not set
# CONFIG_USB_GSPCA_OV519 is not set
# CONFIG_USB_GSPCA_OV534 is not set
# CONFIG_USB_GSPCA_OV534_9 is not set
# CONFIG_USB_GSPCA_PAC207 is not set
# CONFIG_USB_GSPCA_PAC7302 is not set
# CONFIG_USB_GSPCA_PAC7311 is not set
# CONFIG_USB_GSPCA_SE401 is not set
# CONFIG_USB_GSPCA_SN9C2028 is not set
# CONFIG_USB_GSPCA_SN9C20X is not set
# CONFIG_USB_GSPCA_SONIXB is not set
# CONFIG_USB_GSPCA_SONIXJ is not set
# CONFIG_USB_GSPCA_SPCA500 is not set
# CONFIG_USB_GSPCA_SPCA501 is not set
# CONFIG_USB_GSPCA_SPCA505 is not set
# CONFIG_USB_GSPCA_SPCA506 is not set
# CONFIG_USB_GSPCA_SPCA508 is not set
# CONFIG_USB_GSPCA_SPCA561 is not set
# CONFIG_USB_GSPCA_SPCA1528 is not set
# CONFIG_USB_GSPCA_SQ905 is not set
# CONFIG_USB_GSPCA_SQ905C is not set
# CONFIG_USB_GSPCA_SQ930X is not set
# CONFIG_USB_GSPCA_STK014 is not set
# CONFIG_USB_GSPCA_STK1135 is not set
# CONFIG_USB_GSPCA_STV0680 is not set
# CONFIG_USB_GSPCA_SUNPLUS is not set
# CONFIG_USB_GSPCA_T613 is not set
# CONFIG_USB_GSPCA_TOPRO is not set
# CONFIG_USB_GSPCA_TOUPTEK is not set
# CONFIG_USB_GSPCA_TV8532 is not set
# CONFIG_USB_GSPCA_VC032X is not set
# CONFIG_USB_GSPCA_VICAM is not set
# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
# CONFIG_USB_GSPCA_ZC3XX is not set
# CONFIG_USB_PWC is not set
# CONFIG_VIDEO_CPIA2 is not set
# CONFIG_USB_ZR364XX is not set
# CONFIG_USB_STKWEBCAM is not set
# CONFIG_USB_S2255 is not set
# CONFIG_VIDEO_USBTV is not set
#
# Analog TV USB devices
#
# CONFIG_VIDEO_PVRUSB2 is not set
# CONFIG_VIDEO_HDPVR is not set
# CONFIG_VIDEO_STK1160_COMMON is not set
# CONFIG_VIDEO_GO7007 is not set
#
# Analog/digital TV USB devices
#
# CONFIG_VIDEO_AU0828 is not set
# CONFIG_VIDEO_CX231XX is not set
#
# Digital TV USB devices
#
# CONFIG_DVB_USB_V2 is not set
# CONFIG_SMS_USB_DRV is not set
# CONFIG_DVB_B2C2_FLEXCOP_USB is not set
# CONFIG_DVB_AS102 is not set
#
# Webcam, TV (analog/digital) USB devices
#
# CONFIG_VIDEO_EM28XX is not set
#
# Software defined radio USB devices
#
# CONFIG_USB_AIRSPY is not set
# CONFIG_USB_HACKRF is not set
# CONFIG_USB_MSI2500 is not set
CONFIG_RADIO_ADAPTERS=y
# CONFIG_RADIO_SI470X is not set
# CONFIG_RADIO_SI4713 is not set
# CONFIG_USB_MR800 is not set
# CONFIG_USB_DSBR is not set
# CONFIG_RADIO_SHARK is not set
# CONFIG_RADIO_SHARK2 is not set
# CONFIG_USB_KEENE is not set
# CONFIG_USB_RAREMONO is not set
# CONFIG_USB_MA901 is not set
# CONFIG_RADIO_TEA5764 is not set
# CONFIG_RADIO_SAA7706H is not set
# CONFIG_RADIO_TEF6862 is not set
# CONFIG_RADIO_WL1273 is not set
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_VIDEO_CADENCE is not set
# CONFIG_VIDEO_ASPEED is not set
# CONFIG_VIDEO_MUX is not set
CONFIG_VIDEO_AXI_HDMI_RX=y
# CONFIG_VIDEO_IMAGEON_BRIDGE is not set
# CONFIG_VIDEO_XILINX is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
CONFIG_ADI_AXI_VIDEO_FRAME_BUFFER=y
# CONFIG_DVB_PLATFORM_DRIVERS is not set
# CONFIG_SDR_PLATFORM_DRIVERS is not set
#
# MMC/SDIO DVB adapters
#
# CONFIG_SMS_SDIO_DRV is not set
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_DVB_TEST_DRIVERS is not set
# end of Media drivers
#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y
#
# Audio decoders, processors and mixers
#
# CONFIG_VIDEO_TVAUDIO is not set
# CONFIG_VIDEO_TDA7432 is not set
# CONFIG_VIDEO_TDA9840 is not set
# CONFIG_VIDEO_TDA1997X is not set
# CONFIG_VIDEO_TEA6415C is not set
# CONFIG_VIDEO_TEA6420 is not set
# CONFIG_VIDEO_MSP3400 is not set
# CONFIG_VIDEO_CS3308 is not set
# CONFIG_VIDEO_CS5345 is not set
# CONFIG_VIDEO_CS53L32A is not set
# CONFIG_VIDEO_TLV320AIC23B is not set
# CONFIG_VIDEO_UDA1342 is not set
# CONFIG_VIDEO_WM8775 is not set
# CONFIG_VIDEO_WM8739 is not set
# CONFIG_VIDEO_VP27SMPX is not set
# CONFIG_VIDEO_SONY_BTF_MPX is not set
# end of Audio decoders, processors and mixers
#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set
# end of RDS decoders
#
# Video decoders
#
CONFIG_VIDEO_ADV7180=y
CONFIG_VIDEO_ADV7183=y
CONFIG_VIDEO_ADV748X=y
CONFIG_VIDEO_ADV7604=y
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=y
CONFIG_VIDEO_ADV7842_CEC=y
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_SAA7110 is not set
# CONFIG_VIDEO_SAA711X is not set
# CONFIG_VIDEO_TC358743 is not set
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
# CONFIG_VIDEO_TVP7002 is not set
# CONFIG_VIDEO_TW2804 is not set
# CONFIG_VIDEO_TW9903 is not set
# CONFIG_VIDEO_TW9906 is not set
# CONFIG_VIDEO_TW9910 is not set
# CONFIG_VIDEO_VPX3220 is not set
# CONFIG_VIDEO_MAX9286 is not set
#
# Video and audio decoders
#
# CONFIG_VIDEO_SAA717X is not set
# CONFIG_VIDEO_CX25840 is not set
# end of Video decoders
#
# Video encoders
#
# CONFIG_VIDEO_SAA7127 is not set
# CONFIG_VIDEO_SAA7185 is not set
CONFIG_VIDEO_ADV7170=y
CONFIG_VIDEO_ADV7175=y
CONFIG_VIDEO_ADV7343=y
CONFIG_VIDEO_ADV7393=y
CONFIG_VIDEO_AD9389B=y
# CONFIG_VIDEO_AK881X is not set
# CONFIG_VIDEO_THS8200 is not set
# end of Video encoders
#
# Video improvement chips
#
# CONFIG_VIDEO_UPD64031A is not set
# CONFIG_VIDEO_UPD64083 is not set
# end of Video improvement chips
# CONFIG_VIDEO_AP1302 is not set
#
# Audio/Video compression chips
#
# CONFIG_VIDEO_SAA6752HS is not set
# end of Audio/Video compression chips
#
# SDR tuner chips
#
# CONFIG_SDR_MAX2175 is not set
# end of SDR tuner chips
#
# Miscellaneous helper chips
#
# CONFIG_VIDEO_THS7303 is not set
# CONFIG_VIDEO_M52790 is not set
# CONFIG_VIDEO_I2C is not set
# CONFIG_VIDEO_ST_MIPID02 is not set
# end of Miscellaneous helper chips
#
# Camera sensor devices
#
CONFIG_VIDEO_ADDI9036=y
# CONFIG_VIDEO_HI556 is not set
# CONFIG_VIDEO_IMX208 is not set
# CONFIG_VIDEO_IMX214 is not set
# CONFIG_VIDEO_IMX219 is not set
# CONFIG_VIDEO_IMX258 is not set
# CONFIG_VIDEO_IMX274 is not set
# CONFIG_VIDEO_IMX290 is not set
# CONFIG_VIDEO_IMX319 is not set
# CONFIG_VIDEO_IMX334 is not set
# CONFIG_VIDEO_IMX335 is not set
# CONFIG_VIDEO_IMX355 is not set
# CONFIG_VIDEO_IMX412 is not set
# CONFIG_VIDEO_OV02A10 is not set
# CONFIG_VIDEO_OV2640 is not set
# CONFIG_VIDEO_OV2659 is not set
# CONFIG_VIDEO_OV2680 is not set
# CONFIG_VIDEO_OV2685 is not set
# CONFIG_VIDEO_OV5640 is not set
# CONFIG_VIDEO_OV5645 is not set
# CONFIG_VIDEO_OV5647 is not set
# CONFIG_VIDEO_OV5648 is not set
# CONFIG_VIDEO_OV6650 is not set
# CONFIG_VIDEO_OV5670 is not set
# CONFIG_VIDEO_OV5675 is not set
# CONFIG_VIDEO_OV5695 is not set
# CONFIG_VIDEO_OV7251 is not set
# CONFIG_VIDEO_OV772X is not set
# CONFIG_VIDEO_OV7640 is not set
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_OV7740 is not set
# CONFIG_VIDEO_OV8856 is not set
# CONFIG_VIDEO_OV8865 is not set
# CONFIG_VIDEO_OV9282 is not set
# CONFIG_VIDEO_OV9640 is not set
# CONFIG_VIDEO_OV9650 is not set
# CONFIG_VIDEO_OV13858 is not set
# CONFIG_VIDEO_VS6624 is not set
# CONFIG_VIDEO_MT9M001 is not set
# CONFIG_VIDEO_MT9M032 is not set
# CONFIG_VIDEO_MT9M111 is not set
# CONFIG_VIDEO_MT9P031 is not set
# CONFIG_VIDEO_MT9T001 is not set
# CONFIG_VIDEO_MT9T112 is not set
# CONFIG_VIDEO_MT9V011 is not set
# CONFIG_VIDEO_MT9V032 is not set
# CONFIG_VIDEO_MT9V111 is not set
# CONFIG_VIDEO_SR030PC30 is not set
# CONFIG_VIDEO_NOON010PC30 is not set
# CONFIG_VIDEO_M5MOLS is not set
# CONFIG_VIDEO_RDACM20 is not set
# CONFIG_VIDEO_RDACM21 is not set
# CONFIG_VIDEO_RJ54N1 is not set
# CONFIG_VIDEO_S5K6AA is not set
# CONFIG_VIDEO_S5K6A3 is not set
# CONFIG_VIDEO_S5K4ECGX is not set
# CONFIG_VIDEO_S5K5BAF is not set
# CONFIG_VIDEO_CCS is not set
# CONFIG_VIDEO_ET8EK8 is not set
# CONFIG_VIDEO_S5C73M3 is not set
# end of Camera sensor devices
#
# Lens drivers
#
# CONFIG_VIDEO_AD5820 is not set
# CONFIG_VIDEO_AK7375 is not set
# CONFIG_VIDEO_DW9714 is not set
# CONFIG_VIDEO_DW9768 is not set
# CONFIG_VIDEO_DW9807_VCM is not set
# end of Lens drivers
#
# Flash devices
#
CONFIG_VIDEO_ADP1653=y
# CONFIG_VIDEO_LM3560 is not set
# CONFIG_VIDEO_LM3646 is not set
# end of Flash devices
#
# SPI helper chips
#
# CONFIG_VIDEO_GS1662 is not set
# end of SPI helper chips
#
# Media SPI Adapters
#
CONFIG_CXD2880_SPI_DRV=m
# end of Media SPI Adapters
CONFIG_MEDIA_TUNER=y
#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA827X=m
CONFIG_MEDIA_TUNER_TDA18271=m
CONFIG_MEDIA_TUNER_TDA9887=m
CONFIG_MEDIA_TUNER_TEA5761=m
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_MSI001=m
CONFIG_MEDIA_TUNER_MT20XX=m
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC5000=m
CONFIG_MEDIA_TUNER_XC4000=m
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_MC44S803=m
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_TDA18218=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_IT913X=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
# end of Customize TV tuners
#
# Customise DVB Frontends
#
#
# Multistandard (satellite) frontends
#
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
CONFIG_DVB_STV6110x=m
CONFIG_DVB_STV6111=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_M88DS3103=m
#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
CONFIG_DVB_TDA18271C2DD=m
CONFIG_DVB_SI2165=m
CONFIG_DVB_MN88472=m
CONFIG_DVB_MN88473=m
#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_MT312=m
CONFIG_DVB_ZL10036=m
CONFIG_DVB_ZL10039=m
CONFIG_DVB_S5H1420=m
CONFIG_DVB_STV0288=m
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV6110=m
CONFIG_DVB_STV0900=m
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA10086=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_VES1X93=m
CONFIG_DVB_TUNER_ITD1000=m
CONFIG_DVB_TUNER_CX24113=m
CONFIG_DVB_TDA826X=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_CX24116=m
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
CONFIG_DVB_SI21XX=m
CONFIG_DVB_TS2020=m
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_TDA10071=m
#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_SP887X=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=m
CONFIG_DVB_S5H1432=m
CONFIG_DVB_DRXD=m
CONFIG_DVB_L64781=m
CONFIG_DVB_TDA1004X=m
CONFIG_DVB_NXT6000=m
CONFIG_DVB_MT352=m
CONFIG_DVB_ZL10353=m
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
CONFIG_DVB_DIB9000=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_AF9013=m
CONFIG_DVB_EC100=m
CONFIG_DVB_STV0367=m
CONFIG_DVB_CXD2820R=m
CONFIG_DVB_CXD2841ER=m
CONFIG_DVB_RTL2830=m
CONFIG_DVB_RTL2832=m
CONFIG_DVB_RTL2832_SDR=m
CONFIG_DVB_SI2168=m
CONFIG_DVB_ZD1301_DEMOD=m
CONFIG_DVB_CXD2880=m
#
# DVB-C (cable) frontends
#
CONFIG_DVB_VES1820=m
CONFIG_DVB_TDA10021=m
CONFIG_DVB_TDA10023=m
CONFIG_DVB_STV0297=m
#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_BCM3510=m
CONFIG_DVB_LGDT330X=m
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
CONFIG_DVB_LG2160=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
CONFIG_DVB_S5H1411=m
CONFIG_DVB_MXL692=m
#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_S921=m
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m
#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
CONFIG_DVB_TC90522=m
CONFIG_DVB_MN88443X=m
#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=m
CONFIG_DVB_TUNER_DIB0070=m
CONFIG_DVB_TUNER_DIB0090=m
#
# SEC control devices for DVB-S
#
CONFIG_DVB_DRX39XYJ=m
CONFIG_DVB_LNBH25=m
CONFIG_DVB_LNBH29=m
CONFIG_DVB_LNBP21=m
CONFIG_DVB_LNBP22=m
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_A8293=m
CONFIG_DVB_LGS8GL5=m
CONFIG_DVB_LGS8GXX=m
CONFIG_DVB_ATBM8830=m
CONFIG_DVB_TDA665x=m
CONFIG_DVB_IX2505V=m
CONFIG_DVB_M88RS2000=m
CONFIG_DVB_AF9033=m
CONFIG_DVB_HORUS3A=m
CONFIG_DVB_ASCOT2E=m
CONFIG_DVB_HELENE=m
#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=m
CONFIG_DVB_SP2=m
# end of Customise DVB Frontends
#
# Tools to develop new frontends
#
# CONFIG_DVB_DUMMY_FE is not set
# end of Media ancillary drivers
#
# Graphics support
#
# CONFIG_IMX_IPUV3_CORE is not set
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y
#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips
#
# ARM devices
#
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices
CONFIG_DRM_ADI_AXI_HDMI=y
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
# CONFIG_DRM_EXYNOS is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_ARMADA is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_OMAP is not set
# CONFIG_DRM_TILCDC is not set
# CONFIG_DRM_VIRTIO_GPU is not set
# CONFIG_DRM_FSL_DCU is not set
# CONFIG_DRM_STM is not set
CONFIG_DRM_PANEL=y
#
# Display Panels
#
# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
# CONFIG_DRM_PANEL_DSI_CM is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_SIMPLE is not set
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y
#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
CONFIG_DRM_I2C_ADV7511=y
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_I2C_ADV7511_CEC=y
# CONFIG_DRM_CDNS_MHDP8546 is not set
# end of Display Interface Bridges
# CONFIG_DRM_STI is not set
# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_TVE200 is not set
# CONFIG_DRM_LIMA is not set
# CONFIG_DRM_PANFROST is not set
# CONFIG_DRM_MCDE is not set
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_XLNX is not set
# CONFIG_DRM_GUD is not set
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=y
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_ALTERA_VIP is not set
# CONFIG_FB_ARMCLCD is not set
# CONFIG_FB_UVESA is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_XILINX is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
# end of Frame buffer Devices
#
# Backlight & LCD device support
#
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_PWM is not set
# CONFIG_BACKLIGHT_QCOM_WLED is not set
CONFIG_BACKLIGHT_ADP5520=y
CONFIG_BACKLIGHT_ADP8860=y
CONFIG_BACKLIGHT_ADP8870=y
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_LED is not set
# end of Backlight & LCD device support
CONFIG_HDMI=y
#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
# CONFIG_SND_HRTIMER is not set
# CONFIG_SND_DYNAMIC_MINORS is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_DRIVERS is not set
#
# HD-Audio
#
# end of HD-Audio
CONFIG_SND_HDA_PREALLOC_SIZE=64
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_USB_6FIRE is not set
# CONFIG_SND_USB_HIFACE is not set
# CONFIG_SND_BCD2000 is not set
# CONFIG_SND_USB_POD is not set
# CONFIG_SND_USB_PODHD is not set
# CONFIG_SND_USB_TONEPORT is not set
# CONFIG_SND_USB_VARIAX is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_SOC_ADI=y
CONFIG_SND_SOC_ADI_AXI_I2S=y
CONFIG_SND_SOC_ADI_AXI_SPDIF=y
CONFIG_SND_SOC_ADRV936X_BOX=y
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
# CONFIG_SND_DESIGNWARE_I2S is not set
#
# SoC Audio for Freescale CPUs
#
#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_FSL_XCVR is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs
# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support
# CONFIG_SND_SOC_XILINX_DP is not set
# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y
#
# CODEC drivers
#
# CONFIG_SND_SOC_AC97_CODEC is not set
CONFIG_SND_SOC_AD1836=y
CONFIG_SND_SOC_AD193X=y
CONFIG_SND_SOC_AD193X_SPI=y
CONFIG_SND_SOC_AD193X_I2C=y
# CONFIG_SND_SOC_AD1980 is not set
CONFIG_SND_SOC_AD73311=y
CONFIG_SND_SOC_ADAU_UTILS=y
CONFIG_SND_SOC_ADAU1372=y
CONFIG_SND_SOC_ADAU1372_I2C=y
CONFIG_SND_SOC_ADAU1372_SPI=y
CONFIG_SND_SOC_ADAU1373=y
CONFIG_SND_SOC_ADAU1701=y
CONFIG_SND_SOC_ADAU17X1=y
CONFIG_SND_SOC_ADAU1761=y
CONFIG_SND_SOC_ADAU1761_I2C=y
CONFIG_SND_SOC_ADAU1761_SPI=y
CONFIG_SND_SOC_ADAU1781=y
CONFIG_SND_SOC_ADAU1781_I2C=y
CONFIG_SND_SOC_ADAU1781_SPI=y
CONFIG_SND_SOC_ADAU1977=y
CONFIG_SND_SOC_ADAU1977_SPI=y
CONFIG_SND_SOC_ADAU1977_I2C=y
CONFIG_SND_SOC_ADAU7002=y
CONFIG_SND_SOC_ADAU7118=y
CONFIG_SND_SOC_ADAU7118_HW=y
CONFIG_SND_SOC_ADAU7118_I2C=y
CONFIG_SND_SOC_ADAV80X=y
CONFIG_SND_SOC_ADAV801=y
CONFIG_SND_SOC_ADAV803=y
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4118 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_BD28623 is not set
# CONFIG_SND_SOC_BT_SCO is not set
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS35L36 is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4341 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
# CONFIG_SND_SOC_CX2072X is not set
# CONFIG_SND_SOC_DA7213 is not set
# CONFIG_SND_SOC_DMIC is not set
CONFIG_SND_SOC_HDMI_CODEC=y
# CONFIG_SND_SOC_ES7134 is not set
# CONFIG_SND_SOC_ES7241 is not set
# CONFIG_SND_SOC_ES8316 is not set
# CONFIG_SND_SOC_ES8328_I2C is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_GTM601 is not set
# CONFIG_SND_SOC_ICS43432 is not set
# CONFIG_SND_SOC_INNO_RK3036 is not set
# CONFIG_SND_SOC_MAX98088 is not set
# CONFIG_SND_SOC_MAX98357A is not set
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
# CONFIG_SND_SOC_MAX98927 is not set
# CONFIG_SND_SOC_MAX98373_I2C is not set
# CONFIG_SND_SOC_MAX98390 is not set
# CONFIG_SND_SOC_MAX9860 is not set
# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_I2C is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_I2C is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM5102A is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3328 is not set
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
# CONFIG_SND_SOC_RT5640 is not set
# CONFIG_SND_SOC_RT5659 is not set
# CONFIG_SND_SOC_SGTL5000 is not set
CONFIG_SND_SOC_SIGMADSP=y
CONFIG_SND_SOC_SIGMADSP_I2C=y
CONFIG_SND_SOC_SIGMADSP_REGMAP=y
# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set
# CONFIG_SND_SOC_SIMPLE_MUX is not set
# CONFIG_SND_SOC_SPDIF is not set
CONFIG_SND_SOC_SSM2305=y
CONFIG_SND_SOC_SSM2518=y
CONFIG_SND_SOC_SSM2602=y
CONFIG_SND_SOC_SSM2602_SPI=y
CONFIG_SND_SOC_SSM2602_I2C=y
CONFIG_SND_SOC_SSM4567=y
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TFA989X is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
# CONFIG_SND_SOC_TLV320ADCX140 is not set
CONFIG_SND_SOC_TS3A227E=y
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_UDA1334 is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731 is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
# CONFIG_SND_SOC_WM8904 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_MT6358 is not set
# CONFIG_SND_SOC_MT6660 is not set
# CONFIG_SND_SOC_NAU8315 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8822 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
# end of CODEC drivers
CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
# CONFIG_SND_AUDIO_GRAPH_CARD is not set
#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
CONFIG_HIDRAW=y
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y
#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
# CONFIG_HID_ACCUTOUCH is not set
CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=y
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_ASUS is not set
# CONFIG_HID_AUREAL is not set
CONFIG_HID_BELKIN=y
# CONFIG_HID_BETOP_FF is not set
# CONFIG_HID_BIGBEN_FF is not set
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_COUGAR is not set
# CONFIG_HID_MACALLY is not set
CONFIG_HID_PRODIKEYS=y
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CP2112 is not set
# CONFIG_HID_CREATIVE_SB0540 is not set
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
# CONFIG_DRAGONRISE_FF is not set
CONFIG_HID_EMS_FF=y
# CONFIG_HID_ELAN is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_ELO is not set
CONFIG_HID_EZKEY=y
# CONFIG_HID_FT260 is not set
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
CONFIG_HID_HOLTEK=y
CONFIG_HOLTEK_FF=y
# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_GT683R is not set
CONFIG_HID_KEYTOUCH=y
CONFIG_HID_KYE=y
CONFIG_HID_UCLOGIC=y
CONFIG_HID_WALTOP=y
# CONFIG_HID_VIEWSONIC is not set
CONFIG_HID_GYRATION=y
# CONFIG_HID_ICADE is not set
# CONFIG_HID_ITE is not set
# CONFIG_HID_JABRA is not set
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
# CONFIG_HID_LED is not set
# CONFIG_HID_LENOVO is not set
CONFIG_HID_LOGITECH=y
CONFIG_HID_LOGITECH_DJ=y
CONFIG_HID_LOGITECH_HIDPP=y
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MALTRON is not set
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_REDRAGON is not set
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_MULTITOUCH=y
# CONFIG_HID_NTI is not set
CONFIG_HID_NTRIG=y
CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
# CONFIG_HID_PENMOUNT is not set
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
CONFIG_HID_PICOLCD_FB=y
# CONFIG_HID_PICOLCD_BACKLIGHT is not set
# CONFIG_HID_PICOLCD_LEDS is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PLAYSTATION is not set
CONFIG_HID_PRIMAX=y
# CONFIG_HID_RETRODE is not set
CONFIG_HID_ROCCAT=y
# CONFIG_HID_SAITEK is not set
CONFIG_HID_SAMSUNG=y
# CONFIG_HID_SEMITEK is not set
CONFIG_HID_SONY=y
# CONFIG_SONY_FF is not set
CONFIG_HID_SPEEDLINK=y
# CONFIG_HID_STEAM is not set
# CONFIG_HID_STEELSERIES is not set
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_RMI is not set
CONFIG_HID_GREENASIA=y
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=y
CONFIG_SMARTJOYPLUS_FF=y
# CONFIG_HID_TIVO is not set
CONFIG_HID_TOPSEED=y
# CONFIG_HID_THINGM is not set
CONFIG_HID_THRUSTMASTER=y
CONFIG_THRUSTMASTER_FF=y
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
CONFIG_HID_ZEROPLUS=y
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=y
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_ALPS is not set
# CONFIG_HID_MCP2221 is not set
# end of Special HID drivers
#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
CONFIG_USB_HIDDEV=y
# end of USB HID support
#
# I2C HID support
#
# CONFIG_I2C_HID_OF is not set
# CONFIG_I2C_HID_OF_GOODIX is not set
# end of I2C HID support
# end of HID support
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
# CONFIG_USB_LED_TRIG is not set
CONFIG_USB_ULPI_BUS=y
# CONFIG_USB_CONN_GPIO is not set
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
# CONFIG_USB_OTG_FSM is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
# CONFIG_USB_MON is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
# CONFIG_USB_EHCI_FSL is not set
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_FOTG210_HCD is not set
# CONFIG_USB_MAX3421_HCD is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_TEST_MODE is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_REALTEK is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_STORAGE_ENE_UB6250 is not set
CONFIG_USB_UAS=y
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USBIP_CORE is not set
# CONFIG_USB_CDNS_SUPPORT is not set
# CONFIG_USB_MUSB_HDRC is not set
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_ULPI is not set
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y
#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set
#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_MSM=y
CONFIG_USB_CHIPIDEA_IMX=y
CONFIG_USB_CHIPIDEA_GENERIC=y
CONFIG_USB_CHIPIDEA_TEGRA=y
# CONFIG_USB_ISP1760 is not set
#
# USB port drivers
#
CONFIG_USB_SERIAL=y
# CONFIG_USB_SERIAL_CONSOLE is not set
CONFIG_USB_SERIAL_GENERIC=y
# CONFIG_USB_SERIAL_SIMPLE is not set
# CONFIG_USB_SERIAL_AIRCABLE is not set
# CONFIG_USB_SERIAL_ARK3116 is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_CH341 is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_CP210X is not set
# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
# CONFIG_USB_SERIAL_EMPEG is not set
CONFIG_USB_SERIAL_FTDI_SIO=y
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_IPAQ is not set
# CONFIG_USB_SERIAL_IR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
# CONFIG_USB_SERIAL_F81232 is not set
# CONFIG_USB_SERIAL_F8153X is not set
# CONFIG_USB_SERIAL_GARMIN is not set
# CONFIG_USB_SERIAL_IPW is not set
# CONFIG_USB_SERIAL_IUU is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KLSI is not set
# CONFIG_USB_SERIAL_KOBIL_SCT is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_METRO is not set
# CONFIG_USB_SERIAL_MOS7720 is not set
# CONFIG_USB_SERIAL_MOS7840 is not set
# CONFIG_USB_SERIAL_MXUPORT is not set
# CONFIG_USB_SERIAL_NAVMAN is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_OTI6858 is not set
# CONFIG_USB_SERIAL_QCAUX is not set
# CONFIG_USB_SERIAL_QUALCOMM is not set
# CONFIG_USB_SERIAL_SPCP8X5 is not set
# CONFIG_USB_SERIAL_SAFE is not set
# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
# CONFIG_USB_SERIAL_SYMBOL is not set
# CONFIG_USB_SERIAL_TI is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OPTION is not set
# CONFIG_USB_SERIAL_OMNINET is not set
# CONFIG_USB_SERIAL_OPTICON is not set
# CONFIG_USB_SERIAL_XSENS_MT is not set
# CONFIG_USB_SERIAL_WISHBONE is not set
# CONFIG_USB_SERIAL_SSU100 is not set
# CONFIG_USB_SERIAL_QT2 is not set
CONFIG_USB_SERIAL_UPD78F0730=y
# CONFIG_USB_SERIAL_XR is not set
# CONFIG_USB_SERIAL_DEBUG is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_APPLE_MFI_FASTCHARGE is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_USB2244 is not set
# CONFIG_USB_USB5744 is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_LINK_LAYER_TEST is not set
#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
# CONFIG_AM335X_PHY_USB is not set
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set
#
# USB Peripheral Controller
#
# CONFIG_USB_FUSB300 is not set
# CONFIG_USB_FOTG210_UDC is not set
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_NET2272 is not set
CONFIG_USB_GADGET_XILINX=y
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_NCM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_SUBSET=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_FS=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
# CONFIG_USB_CONFIGFS_OBEX is not set
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
CONFIG_USB_CONFIGFS_F_FS=y
# CONFIG_USB_CONFIGFS_F_UAC1 is not set
# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
# CONFIG_USB_CONFIGFS_F_UAC2 is not set
# CONFIG_USB_CONFIGFS_F_MIDI is not set
# CONFIG_USB_CONFIGFS_F_HID is not set
# CONFIG_USB_CONFIGFS_F_UVC is not set
# CONFIG_USB_CONFIGFS_F_PRINTER is not set
#
# USB Gadget precomposed configurations
#
# CONFIG_USB_ZERO is not set
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_G_NCM is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FUNCTIONFS is not set
# CONFIG_USB_MASS_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_CDC_COMPOSITE is not set
# CONFIG_USB_G_ACM_MS is not set
# CONFIG_USB_G_MULTI is not set
# CONFIG_USB_G_HID is not set
# CONFIG_USB_G_DBGP is not set
# CONFIG_USB_G_WEBCAM is not set
# CONFIG_USB_RAW_GADGET is not set
# end of USB Gadget precomposed configurations
CONFIG_TYPEC=y
# CONFIG_TYPEC_TCPM is not set
# CONFIG_TYPEC_UCSI is not set
# CONFIG_TYPEC_TPS6598X is not set
# CONFIG_TYPEC_HD3SS3220 is not set
# CONFIG_TYPEC_STUSB160X is not set
#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
# end of USB Type-C Multiplexer/DeMultiplexer Switch support
#
# USB Type-C Alternate Mode drivers
#
# CONFIG_TYPEC_DP_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers
CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
# CONFIG_MMC_SDHCI_OF_ASPEED is not set
# CONFIG_MMC_SDHCI_OF_AT91 is not set
# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set
# CONFIG_MMC_SDHCI_CADENCE is not set
# CONFIG_MMC_SDHCI_F_SDH30 is not set
# CONFIG_MMC_SDHCI_MILBEAUT is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_USDHI6ROL0 is not set
CONFIG_MMC_CQHCI=y
# CONFIG_MMC_HSQ is not set
# CONFIG_MMC_MTK is not set
# CONFIG_MMC_SDHCI_XENON is not set
# CONFIG_MMC_SDHCI_OMAP is not set
# CONFIG_MMC_SDHCI_AM654 is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
# CONFIG_LEDS_CLASS_MULTICOLOR is not set
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
# CONFIG_LEDS_AW2013 is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_EL15203000 is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3532 is not set
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_LM3692X is not set
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
# CONFIG_LEDS_DAC124S085 is not set
# CONFIG_LEDS_PWM is not set
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
CONFIG_LEDS_ADP5520=y
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set
#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
# CONFIG_LEDS_SYSCON is not set
# CONFIG_LEDS_MLXREG is not set
# CONFIG_LEDS_USER is not set
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set
#
# Flash and Torch LED drivers
#
# CONFIG_LEDS_AAT1290 is not set
CONFIG_LEDS_AS3645A=y
# CONFIG_LEDS_KTD2692 is not set
# CONFIG_LEDS_LM3601X is not set
# CONFIG_LEDS_RT4505 is not set
# CONFIG_LEDS_RT8515 is not set
# CONFIG_LEDS_SGM3140 is not set
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
# CONFIG_LEDS_TRIGGER_MTD is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
CONFIG_LEDS_TRIGGER_CPU=y
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
# CONFIG_LEDS_TRIGGER_GPIO is not set
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
#
# iptables trigger is under Netfilter config (LED target)
#
# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
# CONFIG_LEDS_TRIGGER_CAMERA is not set
# CONFIG_LEDS_TRIGGER_PANIC is not set
# CONFIG_LEDS_TRIGGER_NETDEV is not set
# CONFIG_LEDS_TRIGGER_PATTERN is not set
# CONFIG_LEDS_TRIGGER_AUDIO is not set
# CONFIG_LEDS_TRIGGER_TTY is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
# CONFIG_RTC_DRV_ABX80X is not set
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_HYM8563 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
CONFIG_RTC_DRV_PCF8563=y
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
# CONFIG_RTC_DRV_SD3078 is not set
#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y
#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_DS3232_HWMON=y
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set
# CONFIG_RTC_DRV_RX6110 is not set
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
# CONFIG_RTC_DRV_ZYNQMP is not set
#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PL030 is not set
# CONFIG_RTC_DRV_PL031 is not set
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set
#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set
#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
# CONFIG_AMBA_PL08X is not set
CONFIG_AXI_DMAC=y
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_NBPFAXI_DMA is not set
CONFIG_PL330_DMA=y
CONFIG_XILINX_DMA=m
CONFIG_XILINX_ZYNQMP_DMA=m
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_XILINX_FRMBUF is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
# CONFIG_DW_DMAC is not set
# CONFIG_SF_PDMA is not set
#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set
CONFIG_XILINX_DMATEST=m
# CONFIG_XILINX_VDMATEST is not set
#
# DMABUF options
#
CONFIG_SYNC_FILE=y
# CONFIG_SW_SYNC is not set
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_HEAPS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
# end of DMABUF options
# CONFIG_AUXDISPLAY is not set
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
CONFIG_UIO_DMEM_GENIRQ=y
# CONFIG_UIO_PRUSS is not set
CONFIG_UIO_XILINX_APM=y
# CONFIG_UIO_XILINX_AI_ENGINE is not set
# CONFIG_VFIO is not set
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO_MENU=y
# CONFIG_VIRTIO_MMIO is not set
# CONFIG_VDPA is not set
CONFIG_VHOST_MENU=y
# CONFIG_VHOST_NET is not set
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support
# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
#
# IIO staging drivers
#
#
# Accelerometers
#
CONFIG_ADIS16203=y
CONFIG_ADIS16240=y
# end of Accelerometers
#
# Analog to digital converters
#
CONFIG_AD7816=y
CONFIG_AD7280=y
# end of Analog to digital converters
#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=y
CONFIG_ADT7316_SPI=y
CONFIG_ADT7316_I2C=y
# end of Analog digital bi-direction converters
#
# Capacitance to digital converters
#
CONFIG_AD7746=y
# end of Capacitance to digital converters
#
# Direct Digital Synthesis
#
CONFIG_AD9832=y
CONFIG_AD9834=y
# end of Direct Digital Synthesis
#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=y
# end of Network Analyzer, Impedance Converters
#
# Active energy metering IC
#
CONFIG_ADE7854=y
CONFIG_ADE7854_I2C=y
CONFIG_ADE7854_SPI=y
# end of Active energy metering IC
#
# Resolver to digital converters
#
CONFIG_AD2S1210=y
# end of Resolver to digital converters
# end of IIO staging drivers
# CONFIG_STAGING_MEDIA is not set
#
# Android
#
# end of Android
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_XILINX_APF is not set
CONFIG_FB_TFT=y
# CONFIG_FB_TFT_AGM1264K_FL is not set
# CONFIG_FB_TFT_BD663474 is not set
# CONFIG_FB_TFT_HX8340BN is not set
# CONFIG_FB_TFT_HX8347D is not set
# CONFIG_FB_TFT_HX8353D is not set
# CONFIG_FB_TFT_HX8357D is not set
# CONFIG_FB_TFT_ILI9163 is not set
# CONFIG_FB_TFT_ILI9320 is not set
# CONFIG_FB_TFT_ILI9325 is not set
# CONFIG_FB_TFT_ILI9340 is not set
# CONFIG_FB_TFT_ILI9341 is not set
# CONFIG_FB_TFT_ILI9481 is not set
# CONFIG_FB_TFT_ILI9486 is not set
# CONFIG_FB_TFT_PCD8544 is not set
# CONFIG_FB_TFT_RA8875 is not set
# CONFIG_FB_TFT_S6D02A1 is not set
# CONFIG_FB_TFT_S6D1121 is not set
CONFIG_FB_TFT_SEPS525=y
# CONFIG_FB_TFT_SH1106 is not set
# CONFIG_FB_TFT_SSD1289 is not set
# CONFIG_FB_TFT_SSD1305 is not set
# CONFIG_FB_TFT_SSD1306 is not set
# CONFIG_FB_TFT_SSD1331 is not set
# CONFIG_FB_TFT_SSD1351 is not set
# CONFIG_FB_TFT_ST7735R is not set
# CONFIG_FB_TFT_ST7789V is not set
# CONFIG_FB_TFT_TINYLCD is not set
# CONFIG_FB_TFT_TLS8204 is not set
# CONFIG_FB_TFT_UC1611 is not set
# CONFIG_FB_TFT_UC1701 is not set
# CONFIG_FB_TFT_UPD161704 is not set
# CONFIG_FB_TFT_WATTEROTT is not set
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_WFX is not set
# CONFIG_XILINX_FCLK is not set
# CONFIG_XLNX_TSMUX is not set
# CONFIG_XROE_FRAMER is not set
# CONFIG_XROE_TRAFFIC_GEN is not set
# CONFIG_SERIAL_UARTLITE_RS485 is not set
# CONFIG_XILINX_TSN is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
#
# Clock driver for ARM Reference designs
#
# CONFIG_ICST is not set
# CONFIG_CLK_SP810 is not set
# end of Clock driver for ARM Reference designs
# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
CONFIG_COMMON_CLK_SI514=y
# CONFIG_COMMON_CLK_SI544 is not set
CONFIG_COMMON_CLK_SI570=y
# CONFIG_COMMON_CLK_SI5324 is not set
# CONFIG_COMMON_CLK_IDT8T49N24X is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
CONFIG_COMMON_CLK_AXI_CLKGEN=y
CONFIG_COMMON_CLK_ADI=y
# CONFIG_COMMON_CLK_PWM is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD_V is not set
#
# Analog Devices Clock Drivers
#
CONFIG_COMMON_CLK_AD9545=y
CONFIG_COMMON_CLK_AD9545_I2C=y
CONFIG_COMMON_CLK_AD9545_SPI=y
# end of Analog Devices Clock Drivers
# CONFIG_XILINX_VCU is not set
# CONFIG_HWSPINLOCK is not set
#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_CADENCE_TTC_TIMER=y
CONFIG_ARM_GLOBAL_TIMER=y
CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
# CONFIG_MICROCHIP_PIT64B is not set
# end of Clock Source drivers
# CONFIG_MAILBOX is not set
# CONFIG_IOMMU_SUPPORT is not set
#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers
#
# Rpmsg drivers
#
# CONFIG_RPMSG_VIRTIO is not set
# end of Rpmsg drivers
# CONFIG_SOUNDWIRE is not set
#
# SOC (System On Chip) specific Drivers
#
#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers
#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers
#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers
#
# i.MX SoC drivers
#
# end of i.MX SoC drivers
#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers
#
# Qualcomm SoC drivers
#
# end of Qualcomm SoC drivers
# CONFIG_SOC_TI is not set
#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers
# CONFIG_PM_DEVFREQ is not set
CONFIG_EXTCON=y
#
# Extcon Device Drivers
#
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
# CONFIG_EXTCON_GPIO is not set
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_MEMORY=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_PL353_SMC=y
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_BUFFER_DMA=y
CONFIG_IIO_BUFFER_DMAENGINE=y
CONFIG_IIO_BUFFER_HW_CONSUMER=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=y
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=y
CONFIG_IIO_SW_TRIGGER=y
CONFIG_IIO_TRIGGERED_EVENT=y
#
# Accelerometers
#
CONFIG_ADIS16201=y
CONFIG_ADIS16209=y
CONFIG_ADXL313=y
CONFIG_ADXL313_I2C=y
CONFIG_ADXL313_SPI=y
CONFIG_ADXL345=y
CONFIG_ADXL345_I2C=y
CONFIG_ADXL345_SPI=y
CONFIG_ADXL355=y
CONFIG_ADXL355_I2C=y
CONFIG_ADXL355_SPI=y
CONFIG_ADXL367=y
CONFIG_ADXL367_SPI=y
CONFIG_ADXL367_I2C=y
CONFIG_ADXL372=y
CONFIG_ADXL372_SPI=y
CONFIG_ADXL372_I2C=y
# CONFIG_BMA180 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMA400 is not set
# CONFIG_BMC150_ACCEL is not set
# CONFIG_BMI088_ACCEL is not set
# CONFIG_DA280 is not set
# CONFIG_DA311 is not set
# CONFIG_DMARD06 is not set
# CONFIG_DMARD09 is not set
# CONFIG_DMARD10 is not set
# CONFIG_FXLS8962AF_I2C is not set
# CONFIG_FXLS8962AF_SPI is not set
# CONFIG_IIO_ST_ACCEL_3AXIS is not set
# CONFIG_KXSD9 is not set
# CONFIG_KXCJK1013 is not set
# CONFIG_MC3230 is not set
# CONFIG_MMA7455_I2C is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMA7660 is not set
# CONFIG_MMA8452 is not set
# CONFIG_MMA9551 is not set
# CONFIG_MMA9553 is not set
# CONFIG_MXC4005 is not set
# CONFIG_MXC6255 is not set
# CONFIG_SCA3000 is not set
# CONFIG_SCA3300 is not set
# CONFIG_STK8312 is not set
# CONFIG_STK8BA50 is not set
# end of Accelerometers
#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=y
CONFIG_AD4134=y
CONFIG_AD400X=y
CONFIG_AD4130=y
CONFIG_AD4630=y
CONFIG_AD7091R5=y
CONFIG_AD7124=y
CONFIG_AD7173=y
CONFIG_AD7192=y
CONFIG_AD7266=y
CONFIG_AD7291=y
CONFIG_AD7292=y
CONFIG_AD7298=y
CONFIG_AD738X=y
CONFIG_AD7476=y
CONFIG_AD7606=y
CONFIG_AD7606_IFACE_PARALLEL=y
CONFIG_AD7606_IFACE_SPI=y
CONFIG_AD7766=y
CONFIG_AD7768=y
CONFIG_AD7768_1=y
CONFIG_AD7780=y
CONFIG_AD7791=y
CONFIG_AD7793=y
CONFIG_AD7887=y
CONFIG_AD7923=y
CONFIG_AD7949=y
CONFIG_AD799X=y
CONFIG_AD9963=y
CONFIG_ADAQ8092=y
# CONFIG_ADM1177 is not set
# CONFIG_ADI_AXI_ADC is not set
CONFIG_CF_AXI_ADC=y
CONFIG_AD9081=y
CONFIG_AD9083=y
CONFIG_AD9208=y
CONFIG_AD9361=y
CONFIG_AD9361_EXT_BAND_CONTROL=y
CONFIG_AD9371=y
CONFIG_ADRV9001=y
CONFIG_ADRV9001_COMMON_VERBOSE=y
CONFIG_ADRV9001_ARM_VERBOSE=y
CONFIG_ADRV9001_VALIDATE_PARAMS=y
CONFIG_ADRV9009=y
CONFIG_ADRV9025=y
CONFIG_AD6676=y
CONFIG_AD9467=y
CONFIG_AD9680=y
CONFIG_ADMC=y
CONFIG_CF_AXI_TDD=y
CONFIG_AD_PULSAR=y
CONFIG_AXI_PULSE_CAPTURE=y
CONFIG_AXI_FMCADC5_SYNC=y
# CONFIG_CC10001_ADC is not set
# CONFIG_ENVELOPE_DETECTOR is not set
# CONFIG_HI8435 is not set
# CONFIG_HX711 is not set
# CONFIG_INA2XX_ADC is not set
# CONFIG_INA260_ADC is not set
CONFIG_LTC2308=y
CONFIG_LTC2387=y
CONFIG_LTC2471=y
CONFIG_LTC2485=y
CONFIG_LTC2496=y
CONFIG_LTC2497=y
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
CONFIG_MAX11410=y
# CONFIG_MAX1241 is not set
# CONFIG_MAX1363 is not set
# CONFIG_MAX9611 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
# CONFIG_MCP3911 is not set
# CONFIG_NAU7802 is not set
# CONFIG_SD_ADC_MODULATOR is not set
# CONFIG_TI_ADC081C is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS1015 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_ADS131E08 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_TI_TSC2046 is not set
# CONFIG_VF610_ADC is not set
CONFIG_XILINX_XADC=y
# CONFIG_VERSAL_SYSMON is not set
# end of Analog to digital converters
#
# Analog to digital and digital to analog converters
#
CONFIG_AD74115=y
CONFIG_AD74413R=y
CONFIG_ONE_BIT_ADC_DAC=y
# end of Analog to digital and digital to analog converters
#
# Analog Front Ends
#
# CONFIG_IIO_RESCALE is not set
# end of Analog Front Ends
#
# Amplifiers
#
CONFIG_AD8366=y
CONFIG_AD916X_AMP=y
CONFIG_ADA4250=y
CONFIG_HMC425=y
# end of Amplifiers
#
# Beamformers
#
CONFIG_ADAR1000=y
CONFIG_ADAR3000=y
# end of Beamformers
#
# Capacitance to digital converters
#
CONFIG_AD7150=y
# end of Capacitance to digital converters
#
# Chemical Sensors
#
# CONFIG_ATLAS_PH_SENSOR is not set
# CONFIG_ATLAS_EZO_SENSOR is not set
# CONFIG_BME680 is not set
# CONFIG_CCS811 is not set
# CONFIG_IAQCORE is not set
# CONFIG_SCD30_CORE is not set
# CONFIG_SENSIRION_SGP30 is not set
# CONFIG_SENSIRION_SGP40 is not set
# CONFIG_SPS30_I2C is not set
# CONFIG_VZ89X is not set
# end of Chemical Sensors
#
# Hid Sensor IIO Common
#
# end of Hid Sensor IIO Common
#
# IIO SCMI Sensors
#
# end of IIO SCMI Sensors
#
# SSP Sensor Common
#
# CONFIG_IIO_SSP_SENSORHUB is not set
# end of SSP Sensor Common
#
# Digital to analog converters
#
CONFIG_AD3552R=y
CONFIG_AD5064=y
CONFIG_AD5270=y
CONFIG_AD5360=y
CONFIG_AD5380=y
CONFIG_AD5421=y
CONFIG_AD5446=y
CONFIG_AD5449=y
CONFIG_AD5592R_BASE=y
CONFIG_AD5592R=y
CONFIG_AD5593R=y
CONFIG_AD5504=y
CONFIG_AD5624R_SPI=y
CONFIG_LTC2688=y
CONFIG_AD5686=y
CONFIG_AD5686_SPI=y
CONFIG_AD5696_I2C=y
CONFIG_AD5755=y
CONFIG_AD5758=y
CONFIG_AD5761=y
CONFIG_AD5764=y
CONFIG_AD5766=y
CONFIG_AD5770R=y
CONFIG_AD5791=y
CONFIG_AD7293=y
CONFIG_AD7303=y
CONFIG_AD8801=y
# CONFIG_DPOT_DAC is not set
# CONFIG_DS4424 is not set
CONFIG_LTC1660=y
CONFIG_LTC2632=y
# CONFIG_M62332 is not set
# CONFIG_MAX517 is not set
# CONFIG_MAX5821 is not set
# CONFIG_MCP4725 is not set
# CONFIG_MCP4922 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC5571 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_VF610_DAC is not set
# end of Digital to analog converters
#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver
#
# Filters
#
CONFIG_ADMV8818=y
# end of Filters
#
# Frequency Synthesizers DDS/PLL
#
#
# Clock Generator/Distribution
#
CONFIG_AD9508=y
CONFIG_AD9523=y
CONFIG_AD9528=y
CONFIG_AD9548=y
CONFIG_AD9517=y
CONFIG_ADMV1013=y
CONFIG_ADMV1014=y
CONFIG_ADMV4420=y
CONFIG_ADRF6780=y
CONFIG_HMC7044=y
CONFIG_LTC6952=y
# end of Clock Generator/Distribution
#
# Direct Digital Synthesis
#
CONFIG_CF_AXI_DDS=y
CONFIG_CF_AXI_DDS_AD9122=y
CONFIG_CF_AXI_DDS_AD9144=y
CONFIG_CF_AXI_DDS_AD9162=y
CONFIG_CF_AXI_DDS_AD9172=y
CONFIG_CF_AXI_DDS_AD9739A=y
CONFIG_CF_AXI_DDS_AD9783=y
CONFIG_M2K_DAC=y
# end of Direct Digital Synthesis
#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4159=y
CONFIG_ADF4350=y
CONFIG_ADF4360=y
CONFIG_ADF4371=y
CONFIG_ADF4377=y
CONFIG_ADF5355=y
# end of Phase-Locked Loop (PLL) frequency synthesizers
#
# RF Font-Ends
#
CONFIG_ADL5960=y
# end of RF Font-Ends
# end of Frequency Synthesizers DDS/PLL
#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=y
CONFIG_ADIS16130=y
CONFIG_ADIS16136=y
CONFIG_ADIS16260=y
CONFIG_ADXRS290=y
CONFIG_ADXRS450=y
# CONFIG_BMG160 is not set
# CONFIG_FXAS21002C is not set
# CONFIG_MPU3050_I2C is not set
# CONFIG_IIO_ST_GYRO_3AXIS is not set
# CONFIG_ITG3200 is not set
# end of Digital gyroscope sensors
#
# Health Sensors
#
#
# Heart Rate Monitors
#
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
# CONFIG_MAX30100 is not set
# CONFIG_MAX30102 is not set
# end of Heart Rate Monitors
# end of Health Sensors
#
# Humidity sensors
#
# CONFIG_AM2315 is not set
# CONFIG_DHT11 is not set
# CONFIG_HDC100X is not set
# CONFIG_HDC2010 is not set
# CONFIG_HTS221 is not set
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
# CONFIG_SI7020 is not set
# end of Humidity sensors
#
# Inertial measurement units
#
CONFIG_ADIS16400=y
CONFIG_ADIS16460=y
CONFIG_ADIS16475=y
CONFIG_ADIS16480=y
# CONFIG_BMI160_I2C is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_FXOS8700_I2C is not set
# CONFIG_FXOS8700_SPI is not set
# CONFIG_KMX61 is not set
# CONFIG_INV_ICM42600_I2C is not set
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_MPU6050_I2C is not set
# CONFIG_INV_MPU6050_SPI is not set
# CONFIG_IIO_ST_LSM6DSX is not set
# CONFIG_IIO_ST_LSM9DS0 is not set
# end of Inertial measurement units
CONFIG_IIO_ADIS_LIB=y
CONFIG_IIO_ADIS_LIB_BUFFER=y
# CONFIG_ALTERA_ARRIA10_JESD204_PHY is not set
CONFIG_AXI_ADXCVR=y
CONFIG_AXI_JESD204B=y
CONFIG_AXI_JESD204_TX=y
CONFIG_AXI_JESD204_RX=y
CONFIG_XILINX_TRANSCEIVER=y
CONFIG_ADI_IIO_FAKEDEV=y
#
# Light sensors
#
# CONFIG_ADJD_S311 is not set
CONFIG_ADUX1020=y
# CONFIG_AL3010 is not set
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
# CONFIG_AS73211 is not set
# CONFIG_BH1750 is not set
# CONFIG_BH1780 is not set
# CONFIG_CM32181 is not set
# CONFIG_CM3232 is not set
# CONFIG_CM3323 is not set
# CONFIG_CM3605 is not set
# CONFIG_CM36651 is not set
# CONFIG_GP2AP002 is not set
# CONFIG_GP2AP020A00F is not set
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_ISL29028 is not set
# CONFIG_ISL29125 is not set
# CONFIG_JSA1212 is not set
# CONFIG_RPR0521 is not set
# CONFIG_LTR501 is not set
# CONFIG_LV0104CS is not set
# CONFIG_MAX44000 is not set
# CONFIG_MAX44009 is not set
# CONFIG_NOA1305 is not set
# CONFIG_OPT3001 is not set
# CONFIG_PA12203001 is not set
# CONFIG_SI1133 is not set
# CONFIG_SI1145 is not set
# CONFIG_STK3310 is not set
# CONFIG_ST_UVIS25 is not set
# CONFIG_TCS3414 is not set
# CONFIG_TCS3472 is not set
# CONFIG_SENSORS_TSL2563 is not set
# CONFIG_TSL2583 is not set
# CONFIG_TSL2591 is not set
# CONFIG_TSL2772 is not set
# CONFIG_TSL4531 is not set
# CONFIG_US5182D is not set
# CONFIG_VCNL4000 is not set
# CONFIG_VCNL4035 is not set
# CONFIG_VEML6030 is not set
# CONFIG_VEML6070 is not set
# CONFIG_VL6180 is not set
# CONFIG_ZOPT2201 is not set
# end of Light sensors
#
# Logic Analyzers
#
CONFIG_M2K_LOGIC_ANALYZER=y
# end of Logic Analyzers
#
# Magnetometer sensors
#
# CONFIG_AK8974 is not set
# CONFIG_AK8975 is not set
# CONFIG_AK09911 is not set
# CONFIG_BMC150_MAGN_I2C is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_MAG3110 is not set
# CONFIG_MMC35240 is not set
# CONFIG_IIO_ST_MAGN_3AXIS is not set
# CONFIG_SENSORS_HMC5843_I2C is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_RM3100_I2C is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_YAMAHA_YAS530 is not set
# end of Magnetometer sensors
#
# Multiplexers
#
# CONFIG_IIO_MUX is not set
CONFIG_IIO_GEN_MUX=y
# end of Multiplexers
#
# IIO Regmap Access Drivers
#
CONFIG_IIO_REGMAP=y
CONFIG_IIO_REGMAP_I2C=y
CONFIG_IIO_REGMAP_SPI=y
# end of IIO Regmap Access Drivers
#
# Inclinometer sensors
#
# end of Inclinometer sensors
#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=y
CONFIG_IIO_INTERRUPT_TRIGGER=y
CONFIG_IIO_TIGHTLOOP_TRIGGER=y
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone
#
# Linear and angular position sensors
#
# end of Linear and angular position sensors
#
# Digital potentiometers
#
CONFIG_AD5110=y
CONFIG_AD5272=y
# CONFIG_DS1803 is not set
# CONFIG_MAX5432 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MCP4018 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
# CONFIG_MCP41010 is not set
# CONFIG_TPL0102 is not set
# end of Digital potentiometers
#
# Digital potentiostats
#
# CONFIG_LMP91000 is not set
# end of Digital potentiostats
#
# Pressure sensors
#
# CONFIG_ABP060MG is not set
# CONFIG_BMP280 is not set
# CONFIG_DLHL60D is not set
# CONFIG_DPS310 is not set
# CONFIG_HP03 is not set
# CONFIG_ICP10100 is not set
# CONFIG_MPL115_I2C is not set
# CONFIG_MPL115_SPI is not set
# CONFIG_MPL3115 is not set
# CONFIG_MS5611 is not set
# CONFIG_MS5637 is not set
# CONFIG_IIO_ST_PRESS is not set
# CONFIG_T5403 is not set
# CONFIG_HP206C is not set
# CONFIG_ZPA2326 is not set
# end of Pressure sensors
#
# Lightning sensors
#
# CONFIG_AS3935 is not set
# end of Lightning sensors
#
# Proximity and distance sensors
#
# CONFIG_ISL29501 is not set
# CONFIG_LIDAR_LITE_V2 is not set
# CONFIG_MB1232 is not set
# CONFIG_PING is not set
# CONFIG_RFD77402 is not set
# CONFIG_SRF04 is not set
# CONFIG_SX9310 is not set
# CONFIG_SX9500 is not set
# CONFIG_SRF08 is not set
# CONFIG_VCNL3020 is not set
# CONFIG_VL53L0X_I2C is not set
# end of Proximity and distance sensors
#
# Resolver to digital converters
#
CONFIG_AD2S90=y
CONFIG_AD2S1200=y
# end of Resolver to digital converters
#
# Temperature sensors
#
CONFIG_LTC2983=y
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_MLX90614 is not set
# CONFIG_MLX90632 is not set
# CONFIG_TMP006 is not set
# CONFIG_TMP007 is not set
# CONFIG_TMP117 is not set
# CONFIG_TSYS01 is not set
# CONFIG_TSYS02D is not set
# CONFIG_MAX31856 is not set
CONFIG_MAX31865=y
# end of Temperature sensors
CONFIG_JESD204=y
CONFIG_JESD204_TOP_DEVICE=y
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
CONFIG_PWM_AXI_PWMGEN=y
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_PCA9685 is not set
# CONFIG_PWM_CADENCE is not set
#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
# CONFIG_AL_FIC is not set
# CONFIG_XILINX_INTC is not set
# end of IRQ chip support
# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_TI_SYSCON is not set
CONFIG_RESET_ZYNQ=y
#
# PHY Subsystem
#
# CONFIG_GENERIC_PHY is not set
# CONFIG_PHY_CAN_TRANSCEIVER is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem
# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set
#
# Performance monitor support
#
# CONFIG_ARM_CCI_PMU is not set
# CONFIG_ARM_CCN is not set
CONFIG_ARM_PMU=y
# end of Performance monitor support
# CONFIG_RAS is not set
#
# Android
#
# CONFIG_ANDROID is not set
# end of Android
# CONFIG_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_AXI_SYSID=y
# CONFIG_NVMEM_RMEM is not set
#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# end of HW tracing support
CONFIG_FPGA=y
# CONFIG_FPGA_MGR_DEBUG_FS is not set
# CONFIG_ALTERA_PR_IP_CORE is not set
# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
CONFIG_FPGA_MGR_ZYNQ_FPGA=y
# CONFIG_FPGA_MGR_XILINX_SPI is not set
# CONFIG_FPGA_MGR_ICE40_SPI is not set
# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
CONFIG_FPGA_MGR_ZYNQ_AFI_FPGA=y
CONFIG_FPGA_BRIDGE=y
# CONFIG_ALTERA_FREEZE_BRIDGE is not set
# CONFIG_XILINX_PR_DECOUPLER is not set
CONFIG_FPGA_REGION=y
CONFIG_OF_FPGA_REGION=y
# CONFIG_FPGA_DFL is not set
# CONFIG_FSI is not set
# CONFIG_TEE is not set
CONFIG_MULTIPLEXER=y
#
# Multiplexer drivers
#
CONFIG_MUX_ADG792A=y
CONFIG_MUX_ADGS1408=y
CONFIG_MUX_GPIO=y
CONFIG_MUX_MMIO=y
# end of Multiplexer drivers
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
# CONFIG_COUNTER is not set
# CONFIG_MOST is not set
# end of Device Drivers
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_VALIDATE_FS_PARSER is not set
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
# CONFIG_EXT4_FS_SECURITY is not set
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_F2FS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
CONFIG_FILE_LOCKING=y
# CONFIG_FS_ENCRYPTION is not set
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
# CONFIG_CUSE is not set
# CONFIG_VIRTIO_FS is not set
# CONFIG_OVERLAY_FS is not set
#
# Caches
#
# CONFIG_FSCACHE is not set
# end of Caches
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
# end of CD-ROM/DVD Filesystems
#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_FAT_DEFAULT_UTF8 is not set
# CONFIG_EXFAT_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS3_FS is not set
# end of DOS/FAT/EXFAT/NT Filesystems
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
# CONFIG_PROC_CHILDREN is not set
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
CONFIG_MEMFD_CREATE=y
CONFIG_CONFIGFS_FS=y
# end of Pseudo filesystems
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_PSTORE is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_EROFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
# CONFIG_NFS_SWAP is not set
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=y
CONFIG_PNFS_FLEXFILE_LAYOUT=y
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFS_V4_2_READ_PLUS is not set
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_SUNRPC_BACKCHANNEL=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_SMB_SERVER is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
# CONFIG_NLS_UTF8 is not set
# CONFIG_DLM is not set
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems
#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf"
#
# Kernel hardening options
#
#
# Memory initialization
#
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
# end of Kernel hardening options
# end of Security options
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
# CONFIG_CRYPTO_PCRYPT is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set
#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
# CONFIG_CRYPTO_DH is not set
# CONFIG_CRYPTO_ECDH is not set
# CONFIG_CRYPTO_ECDSA is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_CURVE25519 is not set
#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_AEGIS128 is not set
# CONFIG_CRYPTO_SEQIV is not set
# CONFIG_CRYPTO_ECHAINIV is not set
#
# Block modes
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CFB is not set
CONFIG_CRYPTO_CTR=y
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_KEYWRAP is not set
# CONFIG_CRYPTO_ADIANTUM is not set
# CONFIG_CRYPTO_ESSIV is not set
#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set
#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRC32 is not set
# CONFIG_CRYPTO_XXHASH is not set
# CONFIG_CRYPTO_BLAKE2B is not set
# CONFIG_CRYPTO_BLAKE2S is not set
# CONFIG_CRYPTO_CRCT10DIF is not set
CONFIG_CRYPTO_GHASH=y
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_SHA1 is not set
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_STREEBOG is not set
# CONFIG_CRYPTO_WP512 is not set
#
# Ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_TWOFISH is not set
#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_ZSTD is not set
#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_DRBG_MENU is not set
# CONFIG_CRYPTO_JITTERENTROPY is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
CONFIG_CRYPTO_HASH_INFO=y
#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
# CONFIG_CRYPTO_LIB_BLAKE2S is not set
# CONFIG_CRYPTO_LIB_CHACHA is not set
# CONFIG_CRYPTO_LIB_CURVE25519 is not set
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
# CONFIG_CRYPTO_LIB_POLY1305 is not set
# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking
#
# Library routines
#
CONFIG_LINEAR_RANGES=y
# CONFIG_PACKING is not set
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
# CONFIG_CORDIC is not set
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC64 is not set
# CONFIG_CRC4 is not set
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_DECOMPRESS=y
# CONFIG_XZ_DEC is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set
#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=128
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_FONT_SUPPORT=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_ACORN_8x8 is not set
# CONFIG_FONT_MINI_4x6 is not set
# CONFIG_FONT_6x10 is not set
# CONFIG_FONT_10x18 is not set
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_TER16x32 is not set
# CONFIG_FONT_6x8 is not set
CONFIG_SG_POOL=y
CONFIG_SBITMAP=y
# end of Library routines
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
#
# Kernel hacking
#
#
# printk and dmesg options
#
# CONFIG_PRINTK_TIME is not set
# CONFIG_PRINTK_CALLER is not set
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DYNAMIC_DEBUG_CORE is not set
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options
#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
# CONFIG_DEBUG_INFO_COMPRESSED is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
# CONFIG_DEBUG_INFO_BTF is not set
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=1024
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
# CONFIG_HEADERS_INSTALL is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options
#
# Generic Kernel Debugging Instruments
#
# CONFIG_MAGIC_SYSRQ is not set
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
# CONFIG_UBSAN is not set
# end of Generic Kernel Debugging Instruments
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y
#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_RODATA_TEST is not set
# CONFIG_DEBUG_WX is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
# CONFIG_DEBUG_VM is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
# CONFIG_DEBUG_KMAP_LOCAL is not set
# CONFIG_DEBUG_HIGHMEM is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
# end of Memory Debugging
# CONFIG_DEBUG_SHIRQ is not set
#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=20
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs
#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging
# CONFIG_DEBUG_TIMEKEEPING is not set
# CONFIG_DEBUG_PREEMPT is not set
#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)
# CONFIG_DEBUG_IRQFLAGS is not set
# CONFIG_STACKTRACE is not set
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Debug kernel data structures
# CONFIG_DEBUG_CREDENTIALS is not set
#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=60
CONFIG_RCU_TRACE=y
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging
# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_SAMPLES is not set
# CONFIG_STRICT_DEVMEM is not set
#
# arm Debugging
#
# CONFIG_ARM_PTDUMP_DEBUGFS is not set
# CONFIG_UNWINDER_FRAME_POINTER is not set
CONFIG_UNWINDER_ARM=y
CONFIG_ARM_UNWIND=y
# CONFIG_DEBUG_USER is not set
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ZYNQ_UART0 is not set
CONFIG_DEBUG_ZYNQ_UART1=y
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_DEBUG_SEMIHOSTING is not set
# CONFIG_DEBUG_LL_UART_8250 is not set
# CONFIG_DEBUG_LL_UART_PL01X is not set
# CONFIG_DEBUG_UART_FLOW_CONTROL is not set
CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S"
# CONFIG_DEBUG_UNCOMPRESS is not set
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_EARLY_PRINTK=y
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_CORESIGHT is not set
# end of arm Debugging
#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_STRING_SELFTEST is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_SCANF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_ARCH_USE_MEMTEST=y
# CONFIG_MEMTEST is not set
# end of Kernel Testing and Coverage
# end of Kernel hacking
================================================
FILE: kernel_boot/kernel_config_zynqmp
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.15.36 Kernel Configuration
#
CONFIG_KERNEL_ALL_ADI_DRIVERS=y
CONFIG_CLK_ALL_ADI_DRIVERS=y
CONFIG_HWMON_ALL_ADI_DRIVERS=y
CONFIG_IIO_ALL_ADI_DRIVERS=y
CONFIG_INPUT_ALL_ADI_DRIVERS=y
CONFIG_MEDIA_ALL_ADI_DRIVERS=y
CONFIG_USB_ALL_ADI_DRIVERS=y
CONFIG_SND_SOC_ALL_ADI_CODECS=y
CONFIG_CC_VERSION_TEXT="aarch64-xilinx-linux-gcc.real (GCC) 10.2.0"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=100200
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=23500
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=23500
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y
#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem
CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
#
# BPF subsystem
#
# CONFIG_BPF_SYSCALL is not set
# CONFIG_BPF_JIT is not set
CONFIG_USERMODE_DRIVER=y
# end of BPF subsystem
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting
CONFIG_CPU_ISOLATION=y
#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=16
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y
#
# Scheduler features
#
# end of Scheduler features
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
# CONFIG_MEMCG is not set
# CONFIG_BLK_CGROUP is not set
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CGROUP_PIDS is not set
# CONFIG_CGROUP_RDMA is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CGROUP_HUGETLB is not set
# CONFIG_CPUSETS is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_PERF is not set
# CONFIG_CGROUP_MISC is not set
# CONFIG_CGROUP_DEBUG is not set
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
# CONFIG_BOOT_CONFIG is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_HAVE_FUTEX_CMPXCHG=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set
#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
# end of General setup
CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM2835 is not set
# CONFIG_ARCH_BCM4908 is not set
# CONFIG_ARCH_BCM_IPROC is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_BRCMSTB is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LAYERSCAPE is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_ARCH_S32 is not set
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
CONFIG_ARCH_ZYNQMP=y
# end of Platform selection
#
# Kernel Features
#
#
# ARM errata workarounds via the alternatives framework
#
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework
CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_SCHED_MC is not set
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
# CONFIG_NUMA is not set
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC is not set
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y
#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
# end of ARMv8.1 architectural features
#
# ARMv8.2 architectural features
#
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features
#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_PAC=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features
#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features
#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_ARM64_BTI_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARCH_RANDOM=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features
#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features
CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
# CONFIG_ARM64_PSEUDO_NMI is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features
#
# Boot options
#
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
# CONFIG_DMI is not set
# end of Boot options
CONFIG_SYSVIPC_COMPAT=y
#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
# CONFIG_ENERGY_MODEL is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options
#
# CPU Power Management
#
#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
#
# ARM CPU Idle Drivers
#
CONFIG_ARM_CPUIDLE=y
# CONFIG_ARM_PSCI_CPUIDLE is not set
# end of ARM CPU Idle Drivers
# end of CPU Idle
#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_GOV_USERSPACE=y
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# end of CPU Frequency scaling
# end of CPU Power Management
CONFIG_ARCH_SUPPORTS_ACPI=y
# CONFIG_ACPI is not set
# CONFIG_VIRTUALIZATION is not set
# CONFIG_ARM64_CRYPTO is not set
#
# General architecture-dependent options
#
# CONFIG_KPROBES is not set
# CONFIG_JUMP_LABEL is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling
CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
# end of General architecture-dependent options
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_DEV_BSG_COMMON=y
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
# CONFIG_BLK_DEV_ZONED is not set
# CONFIG_BLK_WBT is not set
CONFIG_BLK_DEBUG_FS=y
# CONFIG_BLK_SED_OPAL is not set
# CONFIG_BLK_INLINE_ENCRYPTION is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_EFI_PARTITION=y
# end of Partition Types
CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
# CONFIG_IOSCHED_BFQ is not set
# end of IO Schedulers
CONFIG_ASN1=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK=y
CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_READ_LOCK=y
CONFIG_ARCH_INLINE_READ_LOCK_BH=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_READ_UNLOCK=y
CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_WRITE_LOCK=y
CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_SPIN_TRYLOCK=y
CONFIG_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_INLINE_SPIN_LOCK=y
CONFIG_INLINE_SPIN_LOCK_BH=y
CONFIG_INLINE_SPIN_LOCK_IRQ=y
CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_INLINE_SPIN_UNLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_READ_LOCK=y
CONFIG_INLINE_READ_LOCK_BH=y
CONFIG_INLINE_READ_LOCK_IRQ=y
CONFIG_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_BH=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_WRITE_LOCK=y
CONFIG_INLINE_WRITE_LOCK_BH=y
CONFIG_INLINE_WRITE_LOCK_IRQ=y
CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_BH=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
# CONFIG_BINFMT_MISC is not set
CONFIG_COREDUMP=y
# end of Executable file formats
#
# Memory Management options
#
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_COMPACTION=y
# CONFIG_PAGE_REPORTING is not set
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
# CONFIG_CLEANCACHE is not set
# CONFIG_FRONTSWAP is not set
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
# CONFIG_ZPOOL is not set
# CONFIG_ZSMALLOC is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options
CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_SKB_EXTENSIONS=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_TLS is not set
CONFIG_XFRM=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_INTERFACE is not set
# CONFIG_XFRM_SUB_POLICY is not set
CONFIG_XFRM_MIGRATE=y
# CONFIG_XFRM_STATISTICS is not set
CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=y
# CONFIG_NET_IPGRE_DEMUX is not set
CONFIG_NET_IP_TUNNEL=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
# CONFIG_IP_PIMSM_V1 is not set
# CONFIG_IP_PIMSM_V2 is not set
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=y
# CONFIG_NET_FOU is not set
# CONFIG_NET_FOU_IP_TUNNELS is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_INET_UDP_DIAG is not set
# CONFIG_INET_RAW_DIAG is not set
# CONFIG_INET_DIAG_DESTROY is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
# CONFIG_IPV6_ILA is not set
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=y
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_IPV6_MROUTE is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
# CONFIG_BRIDGE_NETFILTER is not set
#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
# CONFIG_NETFILTER_NETLINK_ACCT is not set
# CONFIG_NETFILTER_NETLINK_QUEUE is not set
CONFIG_NETFILTER_NETLINK_LOG=y
# CONFIG_NETFILTER_NETLINK_OSF is not set
CONFIG_NF_CONNTRACK=m
CONFIG_NF_LOG_SYSLOG=y
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
# CONFIG_NF_CONNTRACK_ZONES is not set
CONFIG_NF_CONNTRACK_PROCFS=y
# CONFIG_NF_CONNTRACK_EVENTS is not set
# CONFIG_NF_CONNTRACK_TIMEOUT is not set
# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
# CONFIG_NF_CONNTRACK_LABELS is not set
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
# CONFIG_NF_CONNTRACK_AMANDA is not set
# CONFIG_NF_CONNTRACK_FTP is not set
# CONFIG_NF_CONNTRACK_H323 is not set
# CONFIG_NF_CONNTRACK_IRC is not set
# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
# CONFIG_NF_CONNTRACK_SNMP is not set
# CONFIG_NF_CONNTRACK_PPTP is not set
# CONFIG_NF_CONNTRACK_SANE is not set
# CONFIG_NF_CONNTRACK_SIP is not set
# CONFIG_NF_CONNTRACK_TFTP is not set
CONFIG_NF_CT_NETLINK=m
# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set
# CONFIG_NF_NAT is not set
# CONFIG_NF_TABLES is not set
CONFIG_NETFILTER_XTABLES=y
CONFIG_NETFILTER_XTABLES_COMPAT=y
#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=m
#
# Xtables targets
#
# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y
# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
# CONFIG_NETFILTER_XT_TARGET_HL is not set
# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
# CONFIG_NETFILTER_XT_TARGET_LED is not set
CONFIG_NETFILTER_XT_TARGET_LOG=y
# CONFIG_NETFILTER_XT_TARGET_MARK is not set
# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
# CONFIG_NETFILTER_XT_TARGET_TEE is not set
# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set
# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
#
# Xtables matches
#
# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
# CONFIG_NETFILTER_XT_MATCH_BPF is not set
# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set
# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set
# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
# CONFIG_NETFILTER_XT_MATCH_CPU is not set
# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
# CONFIG_NETFILTER_XT_MATCH_ECN is not set
# CONFIG_NETFILTER_XT_MATCH_ESP is not set
# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
# CONFIG_NETFILTER_XT_MATCH_HL is not set
# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
# CONFIG_NETFILTER_XT_MATCH_MARK is not set
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
# CONFIG_NETFILTER_XT_MATCH_OSF is not set
# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
# CONFIG_NETFILTER_XT_MATCH_REALM is not set
# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
CONFIG_NETFILTER_XT_MATCH_STATE=m
# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
# CONFIG_NETFILTER_XT_MATCH_STRING is not set
# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
# CONFIG_NETFILTER_XT_MATCH_TIME is not set
# CONFIG_NETFILTER_XT_MATCH_U32 is not set
# end of Core Netfilter Configuration
# CONFIG_IP_SET is not set
# CONFIG_IP_VS is not set
#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=m
# CONFIG_NF_SOCKET_IPV4 is not set
# CONFIG_NF_TPROXY_IPV4 is not set
# CONFIG_NF_DUP_IPV4 is not set
# CONFIG_NF_LOG_ARP is not set
# CONFIG_NF_LOG_IPV4 is not set
CONFIG_NF_REJECT_IPV4=y
CONFIG_IP_NF_IPTABLES=y
# CONFIG_IP_NF_MATCH_AH is not set
# CONFIG_IP_NF_MATCH_ECN is not set
# CONFIG_IP_NF_MATCH_RPFILTER is not set
# CONFIG_IP_NF_MATCH_TTL is not set
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
# CONFIG_IP_NF_TARGET_SYNPROXY is not set
# CONFIG_IP_NF_NAT is not set
CONFIG_IP_NF_MANGLE=y
# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
# CONFIG_IP_NF_TARGET_ECN is not set
# CONFIG_IP_NF_TARGET_TTL is not set
# CONFIG_IP_NF_RAW is not set
# CONFIG_IP_NF_ARPTABLES is not set
# end of IP: Netfilter Configuration
#
# IPv6: Netfilter Configuration
#
# CONFIG_NF_SOCKET_IPV6 is not set
# CONFIG_NF_TPROXY_IPV6 is not set
# CONFIG_NF_DUP_IPV6 is not set
CONFIG_NF_REJECT_IPV6=y
CONFIG_NF_LOG_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
# CONFIG_IP6_NF_MATCH_AH is not set
# CONFIG_IP6_NF_MATCH_EUI64 is not set
# CONFIG_IP6_NF_MATCH_FRAG is not set
# CONFIG_IP6_NF_MATCH_OPTS is not set
# CONFIG_IP6_NF_MATCH_HL is not set
# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
# CONFIG_IP6_NF_MATCH_MH is not set
# CONFIG_IP6_NF_MATCH_RPFILTER is not set
# CONFIG_IP6_NF_MATCH_RT is not set
# CONFIG_IP6_NF_MATCH_SRH is not set
# CONFIG_IP6_NF_TARGET_HL is not set
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
# CONFIG_IP6_NF_TARGET_SYNPROXY is not set
CONFIG_IP6_NF_MANGLE=y
# CONFIG_IP6_NF_RAW is not set
# CONFIG_IP6_NF_NAT is not set
# end of IPv6: Netfilter Configuration
CONFIG_NF_DEFRAG_IPV6=m
# CONFIG_NF_CONNTRACK_BRIDGE is not set
CONFIG_BRIDGE_NF_EBTABLES=y
# CONFIG_BRIDGE_EBT_BROUTE is not set
CONFIG_BRIDGE_EBT_T_FILTER=y
CONFIG_BRIDGE_EBT_T_NAT=y
# CONFIG_BRIDGE_EBT_802_3 is not set
# CONFIG_BRIDGE_EBT_AMONG is not set
# CONFIG_BRIDGE_EBT_ARP is not set
# CONFIG_BRIDGE_EBT_IP is not set
# CONFIG_BRIDGE_EBT_IP6 is not set
# CONFIG_BRIDGE_EBT_LIMIT is not set
# CONFIG_BRIDGE_EBT_MARK is not set
# CONFIG_BRIDGE_EBT_PKTTYPE is not set
# CONFIG_BRIDGE_EBT_STP is not set
# CONFIG_BRIDGE_EBT_VLAN is not set
# CONFIG_BRIDGE_EBT_ARPREPLY is not set
# CONFIG_BRIDGE_EBT_DNAT is not set
CONFIG_BRIDGE_EBT_MARK_T=y
# CONFIG_BRIDGE_EBT_REDIRECT is not set
# CONFIG_BRIDGE_EBT_SNAT is not set
# CONFIG_BRIDGE_EBT_LOG is not set
# CONFIG_BRIDGE_EBT_NFLOG is not set
CONFIG_BPFILTER=y
CONFIG_BPFILTER_UMH=m
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
CONFIG_STP=y
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
# CONFIG_BRIDGE_MRP is not set
# CONFIG_BRIDGE_CFM is not set
CONFIG_NET_DSA=y
# CONFIG_NET_DSA_TAG_AR9331 is not set
# CONFIG_NET_DSA_TAG_BRCM is not set
# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set
# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set
# CONFIG_NET_DSA_TAG_HELLCREEK is not set
# CONFIG_NET_DSA_TAG_GSWIP is not set
# CONFIG_NET_DSA_TAG_DSA is not set
# CONFIG_NET_DSA_TAG_EDSA is not set
# CONFIG_NET_DSA_TAG_MTK is not set
# CONFIG_NET_DSA_TAG_KSZ is not set
# CONFIG_NET_DSA_TAG_RTL4_A is not set
# CONFIG_NET_DSA_TAG_OCELOT is not set
# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
# CONFIG_NET_DSA_TAG_QCA is not set
# CONFIG_NET_DSA_TAG_LAN9303 is not set
# CONFIG_NET_DSA_TAG_SJA1105 is not set
# CONFIG_NET_DSA_TAG_TRAILER is not set
# CONFIG_NET_DSA_TAG_XRS700X is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
CONFIG_LLC=y
# CONFIG_LLC2 is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_6LOWPAN is not set
CONFIG_IEEE802154=y
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=y
CONFIG_MAC802154=y
CONFIG_NET_SCHED=y
#
# Queueing/Scheduling
#
# CONFIG_NET_SCH_CBQ is not set
# CONFIG_NET_SCH_HTB is not set
# CONFIG_NET_SCH_HFSC is not set
# CONFIG_NET_SCH_PRIO is not set
# CONFIG_NET_SCH_MULTIQ is not set
# CONFIG_NET_SCH_RED is not set
# CONFIG_NET_SCH_SFB is not set
# CONFIG_NET_SCH_SFQ is not set
# CONFIG_NET_SCH_TEQL is not set
# CONFIG_NET_SCH_TBF is not set
# CONFIG_NET_SCH_CBS is not set
# CONFIG_NET_SCH_ETF is not set
# CONFIG_NET_SCH_TAPRIO is not set
# CONFIG_NET_SCH_GRED is not set
# CONFIG_NET_SCH_DSMARK is not set
# CONFIG_NET_SCH_NETEM is not set
# CONFIG_NET_SCH_DRR is not set
# CONFIG_NET_SCH_MQPRIO is not set
# CONFIG_NET_SCH_SKBPRIO is not set
# CONFIG_NET_SCH_CHOKE is not set
# CONFIG_NET_SCH_QFQ is not set
# CONFIG_NET_SCH_CODEL is not set
# CONFIG_NET_SCH_FQ_CODEL is not set
# CONFIG_NET_SCH_CAKE is not set
# CONFIG_NET_SCH_FQ is not set
# CONFIG_NET_SCH_HHF is not set
# CONFIG_NET_SCH_PIE is not set
# CONFIG_NET_SCH_PLUG is not set
# CONFIG_NET_SCH_ETS is not set
# CONFIG_NET_SCH_DEFAULT is not set
#
# Classification
#
# CONFIG_NET_CLS_BASIC is not set
# CONFIG_NET_CLS_TCINDEX is not set
# CONFIG_NET_CLS_ROUTE4 is not set
# CONFIG_NET_CLS_FW is not set
# CONFIG_NET_CLS_U32 is not set
# CONFIG_NET_CLS_RSVP is not set
# CONFIG_NET_CLS_RSVP6 is not set
# CONFIG_NET_CLS_FLOW is not set
# CONFIG_NET_CLS_CGROUP is not set
# CONFIG_NET_CLS_BPF is not set
# CONFIG_NET_CLS_FLOWER is not set
# CONFIG_NET_CLS_MATCHALL is not set
# CONFIG_NET_EMATCH is not set
# CONFIG_NET_CLS_ACT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=y
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
# CONFIG_BATMAN_ADV_NC is not set
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
# CONFIG_NET_L3_MASTER_DEV is not set
# CONFIG_QRTR is not set
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_NET_FLOW_LIMIT=y
#
# Network testing
#
CONFIG_NET_PKTGEN=y
# end of Network testing
# end of Networking options
# CONFIG_HAMRADIO is not set
CONFIG_CAN=y
CONFIG_CAN_RAW=y
CONFIG_CAN_BCM=y
CONFIG_CAN_GW=y
# CONFIG_CAN_J1939 is not set
# CONFIG_CAN_ISOTP is not set
#
# CAN Device Drivers
#
# CONFIG_CAN_VCAN is not set
# CONFIG_CAN_VXCAN is not set
# CONFIG_CAN_SLCAN is not set
CONFIG_CAN_DEV=y
CONFIG_CAN_CALC_BITTIMING=y
# CONFIG_CAN_FLEXCAN is not set
# CONFIG_CAN_GRCAN is not set
# CONFIG_CAN_KVASER_PCIEFD is not set
CONFIG_CAN_XILINXCAN=y
# CONFIG_CAN_C_CAN is not set
# CONFIG_CAN_CC770 is not set
# CONFIG_CAN_IFI_CANFD is not set
# CONFIG_CAN_M_CAN is not set
# CONFIG_CAN_PEAK_PCIEFD is not set
# CONFIG_CAN_SJA1000 is not set
# CONFIG_CAN_SOFTING is not set
#
# CAN SPI interfaces
#
# CONFIG_CAN_HI311X is not set
# CONFIG_CAN_MCP251X is not set
# CONFIG_CAN_MCP251XFD is not set
# end of CAN SPI interfaces
#
# CAN USB interfaces
#
# CONFIG_CAN_8DEV_USB is not set
# CONFIG_CAN_EMS_USB is not set
# CONFIG_CAN_ESD_USB2 is not set
# CONFIG_CAN_ETAS_ES58X is not set
# CONFIG_CAN_GS_USB is not set
# CONFIG_CAN_KVASER_USB is not set
# CONFIG_CAN_MCBA_USB is not set
# CONFIG_CAN_PEAK_USB is not set
# CONFIG_CAN_UCAN is not set
# end of CAN USB interfaces
# CONFIG_CAN_DEBUG_DEVICES is not set
# end of CAN Device Drivers
CONFIG_BT=y
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=y
# CONFIG_BT_HS is not set
CONFIG_BT_LE=y
CONFIG_BT_LEDS=y
# CONFIG_BT_MSFTEXT is not set
# CONFIG_BT_AOSPEXT is not set
CONFIG_BT_DEBUGFS=y
# CONFIG_BT_SELFTEST is not set
# CONFIG_BT_FEATURE_DEBUG is not set
#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=y
CONFIG_BT_BCM=y
CONFIG_BT_RTL=y
CONFIG_BT_QCA=y
CONFIG_BT_HCIBTUSB=y
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_BCM=y
# CONFIG_BT_HCIBTUSB_MTK is not set
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
# CONFIG_BT_HCIUART_NOKIA is not set
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
# CONFIG_BT_HCIUART_BCM is not set
# CONFIG_BT_HCIUART_RTL is not set
CONFIG_BT_HCIUART_QCA=y
# CONFIG_BT_HCIUART_AG6XX is not set
# CONFIG_BT_HCIUART_MRVL is not set
CONFIG_BT_HCIBCM203X=y
CONFIG_BT_HCIBPA10X=y
CONFIG_BT_HCIBFUSB=y
CONFIG_BT_HCIVHCI=y
CONFIG_BT_MRVL=y
CONFIG_BT_MRVL_SDIO=y
CONFIG_BT_ATH3K=y
# CONFIG_BT_MTKSDIO is not set
# CONFIG_BT_MTKUART is not set
# CONFIG_BT_VIRTIO is not set
# end of Bluetooth device drivers
# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
# CONFIG_MCTP is not set
CONFIG_WIRELESS=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_CFG80211=y
CONFIG_NL80211_TESTMODE=y
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_DEBUGFS=y
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_MAC80211=y
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_MAC80211_DEBUGFS=y
CONFIG_MAC80211_MESSAGE_TRACING=y
CONFIG_MAC80211_DEBUG_MENU=y
# CONFIG_MAC80211_NOINLINE is not set
CONFIG_MAC80211_VERBOSE_DEBUG=y
CONFIG_MAC80211_MLME_DEBUG=y
CONFIG_MAC80211_STA_DEBUG=y
CONFIG_MAC80211_HT_DEBUG=y
# CONFIG_MAC80211_OCB_DEBUG is not set
# CONFIG_MAC80211_IBSS_DEBUG is not set
CONFIG_MAC80211_PS_DEBUG=y
# CONFIG_MAC80211_MPL_DEBUG is not set
# CONFIG_MAC80211_MPATH_DEBUG is not set
# CONFIG_MAC80211_MHWMP_DEBUG is not set
# CONFIG_MAC80211_MESH_SYNC_DEBUG is not set
# CONFIG_MAC80211_MESH_CSA_DEBUG is not set
# CONFIG_MAC80211_MESH_PS_DEBUG is not set
# CONFIG_MAC80211_TDLS_DEBUG is not set
CONFIG_MAC80211_DEBUG_COUNTERS=y
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=y
CONFIG_NET_9P=y
# CONFIG_NET_9P_VIRTIO is not set
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_DEVLINK=y
# CONFIG_FAILOVER is not set
CONFIG_ETHTOOL_NETLINK=y
#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
# CONFIG_HOTPLUG_PCI is not set
#
# PCI controller drivers
#
CONFIG_PCIE_XILINX_NWL=y
# CONFIG_PCI_FTPCI100 is not set
# CONFIG_PCI_HOST_GENERIC is not set
# CONFIG_PCIE_XILINX is not set
# CONFIG_PCIE_XILINX_CPM is not set
# CONFIG_PCIE_XDMA_PL is not set
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
# CONFIG_PCIE_MICROCHIP_HOST is not set
#
# DesignWare PCI Core Support
#
# CONFIG_PCIE_DW_PLAT_HOST is not set
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
# CONFIG_PCI_MESON is not set
# CONFIG_PCIE_AL is not set
# end of DesignWare PCI Core Support
#
# Mobiveil PCIe Core Support
#
# CONFIG_PCIE_MOBIVEIL_PLAT is not set
# end of Mobiveil PCIe Core Support
#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCI_J721E_HOST is not set
# end of Cadence PCIe controllers support
# end of PCI controller drivers
#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint
#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers
# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set
#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_EXTRA_FIRMWARE="ad9144_fmc_ebz_ad9516.stp Mykonos_M3.bin TaliseStream.bin TaliseTDDArmFirmware.bin TaliseTxArmFirmware.bin TaliseRxArmFirmware.bin adau1761.bin Navassa_EvaluationFw.bin RxGainTable.csv RxGainTable_GainCompensated.csv ORxGainTable.csv TxAttenTable.csv Navassa_Stream.bin Navassa_CMOS_profile.json Navassa_LVDS_profile.json Navassa_CMOS_profile_adrv9003.json Navassa_LVDS_profile_adrv9003.json ADRV9025_DPDCORE_FW.bin ADRV9025_FW.bin ADRV9025_RxGainTable.csv ADRV9025_TxAttenTable.csv stream_image_6E3E00EFB74FE7D465FA88A171B81B8F.bin ActiveUseCase.profile ActiveUtilInit.profile"
CONFIG_EXTRA_FIRMWARE_DIR="./firmware"
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
CONFIG_FW_CACHE=y
# end of Firmware loader
CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options
#
# Bus devices
#
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
# CONFIG_VEXPRESS_CONFIG is not set
# CONFIG_MHI_BUS is not set
# end of Bus devices
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
#
# Firmware Drivers
#
#
# ARM System Control and Management Interface Protocol
#
# CONFIG_ARM_SCMI_PROTOCOL is not set
# end of ARM System Control and Management Interface Protocol
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_ARM_SDE_INTERFACE is not set
# CONFIG_FIRMWARE_MEMMAP is not set
# CONFIG_FW_CFG_SYSFS is not set
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
# CONFIG_ARM_FFA_TRANSPORT is not set
# CONFIG_GOOGLE_FIRMWARE is not set
#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
# end of EFI (Extensible Firmware Interface) Support
CONFIG_EFI_EARLYCON=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_PSCI_CHECKER is not set
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y
#
# Tegra firmware driver
#
# end of Tegra firmware driver
#
# Zynq MPSoC Firmware Drivers
#
CONFIG_ZYNQMP_FIRMWARE=y
# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
# CONFIG_ZYNQMP_FIRMWARE_SECURE is not set
# end of Zynq MPSoC Firmware Drivers
# end of Firmware Drivers
# CONFIG_GNSS is not set
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers
#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
CONFIG_MTD_DATAFLASH=y
# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
# CONFIG_MTD_DATAFLASH_OTP is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers
#
# NAND
#
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set
#
# ECC engine support
#
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
# end of ECC engine support
# end of NAND
#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
# CONFIG_MTD_UBI is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_CONFIGFS=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=65536
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_VIRTIO_BLK is not set
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set
#
# NVME Support
#
# CONFIG_BLK_DEV_NVME is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TCP is not set
# CONFIG_NVME_TARGET is not set
# end of NVME Support
#
# Misc devices
#
CONFIG_AD525X_DPOT=y
CONFIG_AD525X_DPOT_I2C=y
CONFIG_AD525X_DPOT_SPI=y
CONFIG_ADI_AXI_DATA_OFFLOAD=y
CONFIG_ADI_AXI_TDD=y
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
# CONFIG_SRAM is not set
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
CONFIG_XILINX_SDFEC=y
# CONFIG_XILINX_DPU is not set
# CONFIG_XILINX_FLEX_PM is not set
# CONFIG_XILINX_TRAFGEN is not set
# CONFIG_XILINX_AIE is not set
# CONFIG_HISI_HIKEY_USB is not set
CONFIG_XILINX_JESD204B=y
CONFIG_XILINX_JESD204B_PHY=y
# CONFIG_C2PORT is not set
#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support
# CONFIG_CB710_CORE is not set
#
# Texas Instruments shared transport line discipline
#
CONFIG_TI_ST=y
# end of Texas Instruments shared transport line discipline
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
#
# MathWorks IP Drivers
#
CONFIG_MATHWORKS_IP_CORE=y
CONFIG_MWIPCORE=y
CONFIG_MWIPCORE_DMA_STREAMING=y
CONFIG_MWIPCORE_IIO_STREAMING=y
CONFIG_MWIPCORE_IIO_MM=y
CONFIG_MWIPCORE_IIO_SHAREDMEM=y
CONFIG_MATHWORKS_GENERIC_OF=y
# CONFIG_MATHWORKS_GENERIC_PCI is not set
# end of MathWorks IP Drivers
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
# CONFIG_MISC_RTSX_USB is not set
# CONFIG_HABANA_AI is not set
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# end of Misc devices
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
CONFIG_BLK_DEV_BSG=y
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
# CONFIG_SCSI_VIRTIO is not set
# CONFIG_SCSI_DH is not set
# end of SCSI device support
CONFIG_HAVE_PATA_PLATFORM=y
CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_SATA_PMP=y
#
# Controllers with non-SFF native interface
#
# CONFIG_SATA_AHCI is not set
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_CEVA=y
# CONFIG_AHCI_QORIQ is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_SATA_ACARD_AHCI is not set
# CONFIG_SATA_SIL24 is not set
# CONFIG_ATA_SFF is not set
# CONFIG_MD is not set
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_WIREGUARD is not set
# CONFIG_EQUALIZER is not set
# CONFIG_NET_FC is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_IPVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_GENEVE is not set
# CONFIG_BAREUDP is not set
# CONFIG_GTP is not set
# CONFIG_MACSEC is not set
# CONFIG_NETCONSOLE is not set
CONFIG_TUN=y
# CONFIG_TUN_VNET_CROSS_LE is not set
# CONFIG_VETH is not set
# CONFIG_VIRTIO_NET is not set
# CONFIG_NLMON is not set
# CONFIG_ARCNET is not set
#
# Distributed Switch Architecture drivers
#
# CONFIG_B53 is not set
# CONFIG_NET_DSA_BCM_SF2 is not set
# CONFIG_NET_DSA_LOOP is not set
# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
# CONFIG_NET_DSA_MT7530 is not set
# CONFIG_NET_DSA_MV88E6060 is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set
# CONFIG_NET_DSA_MV88E6XXX is not set
# CONFIG_NET_DSA_MSCC_SEVILLE is not set
# CONFIG_NET_DSA_AR9331 is not set
# CONFIG_NET_DSA_SJA1105 is not set
# CONFIG_NET_DSA_XRS700X_I2C is not set
# CONFIG_NET_DSA_XRS700X_MDIO is not set
# CONFIG_NET_DSA_QCA8K is not set
# CONFIG_NET_DSA_REALTEK_SMI is not set
# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
# end of Distributed Switch Architecture drivers
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_3COM=y
# CONFIG_VORTEX is not set
# CONFIG_TYPHOON is not set
CONFIG_NET_VENDOR_ADAPTEC=y
# CONFIG_ADAPTEC_STARFIRE is not set
CONFIG_NET_VENDOR_AGERE=y
# CONFIG_ET131X is not set
CONFIG_NET_VENDOR_ALACRITECH=y
# CONFIG_SLICOSS is not set
CONFIG_NET_VENDOR_ALTEON=y
# CONFIG_ACENIC is not set
# CONFIG_ALTERA_TSE is not set
CONFIG_NET_VENDOR_AMAZON=y
# CONFIG_ENA_ETHERNET is not set
CONFIG_NET_VENDOR_AMD=y
# CONFIG_AMD8111_ETH is not set
# CONFIG_PCNET32 is not set
# CONFIG_AMD_XGBE is not set
CONFIG_NET_VENDOR_AQUANTIA=y
# CONFIG_AQTION is not set
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
# CONFIG_ALX is not set
CONFIG_NET_VENDOR_BROADCOM=y
# CONFIG_B44 is not set
# CONFIG_BCMGENET is not set
# CONFIG_BNX2 is not set
# CONFIG_CNIC is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2X is not set
# CONFIG_SYSTEMPORT is not set
# CONFIG_BNXT is not set
CONFIG_NET_VENDOR_CADENCE=y
CONFIG_MACB=y
CONFIG_MACB_USE_HWSTAMP=y
# CONFIG_MACB_PCI is not set
CONFIG_NET_VENDOR_CAVIUM=y
# CONFIG_THUNDER_NIC_PF is not set
# CONFIG_THUNDER_NIC_VF is not set
# CONFIG_THUNDER_NIC_BGX is not set
# CONFIG_THUNDER_NIC_RGX is not set
# CONFIG_CAVIUM_PTP is not set
# CONFIG_LIQUIDIO is not set
# CONFIG_LIQUIDIO_VF is not set
CONFIG_NET_VENDOR_CHELSIO=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_CHELSIO_T4 is not set
# CONFIG_CHELSIO_T4VF is not set
CONFIG_NET_VENDOR_CISCO=y
# CONFIG_ENIC is not set
CONFIG_NET_VENDOR_CORTINA=y
# CONFIG_GEMINI_ETHERNET is not set
# CONFIG_DNET is not set
CONFIG_NET_VENDOR_DEC=y
# CONFIG_NET_TULIP is not set
CONFIG_NET_VENDOR_DLINK=y
# CONFIG_DL2K is not set
# CONFIG_SUNDANCE is not set
CONFIG_NET_VENDOR_EMULEX=y
# CONFIG_BE2NET is not set
CONFIG_NET_VENDOR_EZCHIP=y
# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
CONFIG_NET_VENDOR_GOOGLE=y
# CONFIG_GVE is not set
CONFIG_NET_VENDOR_HISILICON=y
# CONFIG_HIX5HD2_GMAC is not set
# CONFIG_HISI_FEMAC is not set
# CONFIG_HIP04_ETH is not set
# CONFIG_HNS_DSAF is not set
# CONFIG_HNS_ENET is not set
# CONFIG_HNS3 is not set
CONFIG_NET_VENDOR_HUAWEI=y
# CONFIG_HINIC is not set
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
# CONFIG_E1000 is not set
# CONFIG_E1000E is not set
# CONFIG_IGB is not set
# CONFIG_IGBVF is not set
# CONFIG_IXGB is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
# CONFIG_IGC is not set
# CONFIG_JME is not set
CONFIG_NET_VENDOR_ADI=y
CONFIG_ADIN1110=y
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
CONFIG_NET_VENDOR_MARVELL=y
# CONFIG_MVMDIO is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_OCTEONTX2_AF is not set
# CONFIG_OCTEONTX2_PF is not set
CONFIG_NET_VENDOR_MELLANOX=y
# CONFIG_MLX4_EN is not set
# CONFIG_MLX5_CORE is not set
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8842 is not set
# CONFIG_KS8851 is not set
# CONFIG_KS8851_MLL is not set
# CONFIG_KSZ884X_PCI is not set
CONFIG_NET_VENDOR_MICROCHIP=y
# CONFIG_ENC28J60 is not set
# CONFIG_ENCX24J600 is not set
# CONFIG_LAN743X is not set
CONFIG_NET_VENDOR_MICROSEMI=y
# CONFIG_MSCC_OCELOT_SWITCH is not set
CONFIG_NET_VENDOR_MICROSOFT=y
CONFIG_NET_VENDOR_MYRI=y
# CONFIG_MYRI10GE is not set
# CONFIG_FEALNX is not set
CONFIG_NET_VENDOR_NI=y
# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
CONFIG_NET_VENDOR_NATSEMI=y
# CONFIG_NATSEMI is not set
# CONFIG_NS83820 is not set
CONFIG_NET_VENDOR_NETERION=y
# CONFIG_S2IO is not set
# CONFIG_VXGE is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_NFP is not set
CONFIG_NET_VENDOR_8390=y
# CONFIG_NE2K_PCI is not set
CONFIG_NET_VENDOR_NVIDIA=y
# CONFIG_FORCEDETH is not set
CONFIG_NET_VENDOR_OKI=y
# CONFIG_ETHOC is not set
CONFIG_NET_VENDOR_PACKET_ENGINES=y
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
CONFIG_NET_VENDOR_PENSANDO=y
# CONFIG_IONIC is not set
CONFIG_NET_VENDOR_QLOGIC=y
# CONFIG_QLA3XXX is not set
# CONFIG_QLCNIC is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_QED is not set
CONFIG_NET_VENDOR_BROCADE=y
# CONFIG_BNA is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
# CONFIG_QCOM_EMAC is not set
# CONFIG_RMNET is not set
CONFIG_NET_VENDOR_RDC=y
# CONFIG_R6040 is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_R8169 is not set
CONFIG_NET_VENDOR_RENESAS=y
CONFIG_NET_VENDOR_ROCKER=y
# CONFIG_ROCKER is not set
CONFIG_NET_VENDOR_SAMSUNG=y
# CONFIG_SXGBE_ETH is not set
CONFIG_NET_VENDOR_SEEQ=y
CONFIG_NET_VENDOR_SILAN=y
# CONFIG_SC92031 is not set
CONFIG_NET_VENDOR_SIS=y
# CONFIG_SIS900 is not set
# CONFIG_SIS190 is not set
CONFIG_NET_VENDOR_SOLARFLARE=y
# CONFIG_SFC is not set
# CONFIG_SFC_FALCON is not set
CONFIG_NET_VENDOR_SMSC=y
# CONFIG_SMC91X is not set
# CONFIG_EPIC100 is not set
# CONFIG_SMSC911X is not set
# CONFIG_SMSC9420 is not set
CONFIG_NET_VENDOR_SOCIONEXT=y
CONFIG_NET_VENDOR_STMICRO=y
# CONFIG_STMMAC_ETH is not set
CONFIG_NET_VENDOR_SUN=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NIU is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
CONFIG_NET_VENDOR_TEHUTI=y
# CONFIG_TEHUTI is not set
CONFIG_NET_VENDOR_TI=y
# CONFIG_TI_CPSW_PHY_SEL is not set
# CONFIG_TLAN is not set
CONFIG_NET_VENDOR_VIA=y
# CONFIG_VIA_RHINE is not set
# CONFIG_VIA_VELOCITY is not set
CONFIG_NET_VENDOR_WIZNET=y
# CONFIG_WIZNET_W5100 is not set
# CONFIG_WIZNET_W5300 is not set
CONFIG_NET_VENDOR_XILINX=y
CONFIG_XILINX_EMACLITE=y
CONFIG_XILINX_AXI_EMAC=y
# CONFIG_XILINX_AXI_EMAC_HWTSTAMP is not set
# CONFIG_AXIENET_HAS_MCDMA is not set
# CONFIG_XILINX_LL_TEMAC is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set
#
# MII PHY device drivers
#
CONFIG_AMD_PHY=y
CONFIG_ADIN_PHY=y
CONFIG_ADIN1100_PHY=y
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=y
CONFIG_BROADCOM_PHY=y
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=y
# CONFIG_BCM84881_PHY is not set
CONFIG_BCM87XX_PHY=y
CONFIG_BCM_NET_PHYLIB=y
CONFIG_CICADA_PHY=y
# CONFIG_CORTINA_PHY is not set
CONFIG_DAVICOM_PHY=y
CONFIG_ICPLUS_PHY=y
CONFIG_LXT_PHY=y
# CONFIG_INTEL_XWAY_PHY is not set
CONFIG_LSI_ET1011C_PHY=y
CONFIG_MARVELL_PHY=y
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
# CONFIG_MEDIATEK_GE_PHY is not set
CONFIG_MICREL_PHY=y
# CONFIG_MICROCHIP_PHY is not set
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_MOTORCOMM_PHY is not set
CONFIG_NATIONAL_PHY=y
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
CONFIG_AT803X_PHY=y
CONFIG_QSEMI_PHY=y
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
# CONFIG_ROCKCHIP_PHY is not set
CONFIG_SMSC_PHY=y
CONFIG_STE10XP=y
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
CONFIG_DP83867_PHY=y
# CONFIG_DP83869_PHY is not set
CONFIG_VITESSE_PHY=y
# CONFIG_XILINX_PHY is not set
CONFIG_XILINX_GMII2RGMII=y
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MDIO_BITBANG is not set
# CONFIG_MDIO_BCM_UNIMAC is not set
# CONFIG_MDIO_HISI_FEMAC is not set
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_IPQ4019 is not set
# CONFIG_MDIO_IPQ8064 is not set
# CONFIG_MDIO_THUNDER is not set
#
# MDIO Multiplexers
#
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
#
# PCS device drivers
#
# CONFIG_PCS_XPCS is not set
# end of PCS device drivers
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
CONFIG_USB_NET_DRIVERS=y
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_LAN78XX is not set
CONFIG_USB_USBNET=y
CONFIG_USB_NET_AX8817X=y
CONFIG_USB_NET_AX88179_178A=y
CONFIG_USB_NET_CDCETHER=y
# CONFIG_USB_NET_CDC_EEM is not set
CONFIG_USB_NET_CDC_NCM=y
# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
# CONFIG_USB_NET_CDC_MBIM is not set
# CONFIG_USB_NET_DM9601 is not set
# CONFIG_USB_NET_SR9700 is not set
# CONFIG_USB_NET_SR9800 is not set
# CONFIG_USB_NET_SMSC75XX is not set
# CONFIG_USB_NET_SMSC95XX is not set
# CONFIG_USB_NET_GL620A is not set
CONFIG_USB_NET_NET1080=y
# CONFIG_USB_NET_PLUSB is not set
# CONFIG_USB_NET_MCS7830 is not set
# CONFIG_USB_NET_RNDIS_HOST is not set
CONFIG_USB_NET_CDC_SUBSET_ENABLE=y
CONFIG_USB_NET_CDC_SUBSET=y
# CONFIG_USB_ALI_M5632 is not set
# CONFIG_USB_AN2720 is not set
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
# CONFIG_USB_EPSON2888 is not set
# CONFIG_USB_KC2190 is not set
CONFIG_USB_NET_ZAURUS=y
# CONFIG_USB_NET_CX82310_ETH is not set
# CONFIG_USB_NET_KALMIA is not set
# CONFIG_USB_NET_QMI_WWAN is not set
# CONFIG_USB_HSO is not set
# CONFIG_USB_NET_INT51X1 is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_USB_SIERRA_NET is not set
# CONFIG_USB_VL600 is not set
# CONFIG_USB_NET_CH9200 is not set
# CONFIG_USB_NET_AQC111 is not set
# CONFIG_USB_RTL8153_ECM is not set
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
# CONFIG_ADM8211 is not set
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set
# CONFIG_ATH5K is not set
# CONFIG_ATH5K_PCI is not set
# CONFIG_ATH9K is not set
# CONFIG_ATH9K_HTC is not set
# CONFIG_CARL9170 is not set
# CONFIG_ATH6KL is not set
# CONFIG_AR5523 is not set
# CONFIG_WIL6210 is not set
# CONFIG_ATH10K is not set
# CONFIG_WCN36XX is not set
CONFIG_WLAN_VENDOR_ATMEL=y
# CONFIG_ATMEL is not set
# CONFIG_AT76C50X_USB is not set
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
# CONFIG_BRCMSMAC is not set
# CONFIG_BRCMFMAC is not set
CONFIG_WLAN_VENDOR_CISCO=y
CONFIG_WLAN_VENDOR_INTEL=y
# CONFIG_IPW2100 is not set
# CONFIG_IPW2200 is not set
# CONFIG_IWL4965 is not set
# CONFIG_IWL3945 is not set
# CONFIG_IWLWIFI is not set
CONFIG_WLAN_VENDOR_INTERSIL=y
# CONFIG_HOSTAP is not set
# CONFIG_HERMES is not set
# CONFIG_P54_COMMON is not set
CONFIG_WLAN_VENDOR_MARVELL=y
# CONFIG_LIBERTAS is not set
# CONFIG_LIBERTAS_THINFIRM is not set
# CONFIG_MWIFIEX is not set
# CONFIG_MWL8K is not set
CONFIG_WLAN_VENDOR_MEDIATEK=y
# CONFIG_MT7601U is not set
# CONFIG_MT76x0U is not set
# CONFIG_MT76x0E is not set
# CONFIG_MT76x2E is not set
# CONFIG_MT76x2U is not set
# CONFIG_MT7603E is not set
# CONFIG_MT7615E is not set
# CONFIG_MT7663U is not set
# CONFIG_MT7663S is not set
# CONFIG_MT7915E is not set
# CONFIG_MT7921E is not set
CONFIG_WLAN_VENDOR_MICROCHIP=y
# CONFIG_WILC1000_SDIO is not set
# CONFIG_WILC1000_SPI is not set
CONFIG_WLAN_VENDOR_RALINK=y
# CONFIG_RT2X00 is not set
CONFIG_WLAN_VENDOR_REALTEK=y
# CONFIG_RTL8180 is not set
# CONFIG_RTL8187 is not set
CONFIG_RTL_CARDS=y
# CONFIG_RTL8192CE is not set
# CONFIG_RTL8192SE is not set
# CONFIG_RTL8192DE is not set
# CONFIG_RTL8723AE is not set
# CONFIG_RTL8723BE is not set
# CONFIG_RTL8188EE is not set
# CONFIG_RTL8192EE is not set
# CONFIG_RTL8821AE is not set
# CONFIG_RTL8192CU is not set
# CONFIG_RTL8XXXU is not set
# CONFIG_RTW88 is not set
CONFIG_WLAN_VENDOR_RSI=y
# CONFIG_RSI_91X is not set
CONFIG_WLAN_VENDOR_ST=y
# CONFIG_CW1200 is not set
CONFIG_WLAN_VENDOR_TI=y
# CONFIG_WL1251 is not set
# CONFIG_WL12XX is not set
CONFIG_WL18XX=y
CONFIG_WLCORE=y
CONFIG_WLCORE_SPI=y
CONFIG_WLCORE_SDIO=y
CONFIG_WILINK_PLATFORM_DATA=y
CONFIG_WLAN_VENDOR_ZYDAS=y
# CONFIG_USB_ZD1201 is not set
# CONFIG_ZD1211RW is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
# CONFIG_QTNFMAC_PCIE is not set
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_VIRT_WIFI is not set
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=y
# CONFIG_IEEE802154_FAKELB is not set
# CONFIG_IEEE802154_AT86RF230 is not set
# CONFIG_IEEE802154_MRF24J40 is not set
# CONFIG_IEEE802154_CC2520 is not set
# CONFIG_IEEE802154_ATUSB is not set
CONFIG_IEEE802154_ADF7242=y
# CONFIG_IEEE802154_CA8210 is not set
# CONFIG_IEEE802154_MCR20A is not set
# CONFIG_IEEE802154_HWSIM is not set
#
# Wireless WAN
#
# CONFIG_WWAN is not set
# end of Wireless WAN
# CONFIG_VMXNET3 is not set
# CONFIG_NETDEVSIM is not set
# CONFIG_NET_FAILOVER is not set
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_MATRIXKMAP is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
CONFIG_KEYBOARD_ADP5520=y
CONFIG_KEYBOARD_ADP5588=y
CONFIG_KEYBOARD_ADP5589=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_GPIO_POLLED=y
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_MOUSE_SYNAPTICS_USB is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_AD7877=y
CONFIG_TOUCHSCREEN_AD7879=y
CONFIG_TOUCHSCREEN_AD7879_I2C=y
CONFIG_TOUCHSCREEN_AD7879_SPI=y
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_ILITEK is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MSG2638 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AD714X=y
CONFIG_INPUT_AD714X_I2C=y
CONFIG_INPUT_AD714X_SPI=y
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MMA8450 is not set
# CONFIG_INPUT_GPIO_BEEPER is not set
# CONFIG_INPUT_GPIO_DECODER is not set
# CONFIG_INPUT_GPIO_VIBRA is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
# CONFIG_INPUT_UINPUT is not set
CONFIG_INPUT_PCF8574=y
# CONFIG_INPUT_PWM_BEEPER is not set
# CONFIG_INPUT_PWM_VIBRA is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
# CONFIG_RMI4_CORE is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
# CONFIG_GAMEPORT is not set
# end of Hardware I/O ports
# end of Input device support
#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_LDISC_AUTOLOAD=y
#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_16550A_VARIANTS=y
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
CONFIG_SERIAL_8250_FSL=y
# CONFIG_SERIAL_8250_DW is not set
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_OF_PLATFORM=y
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_AMBA_PL010 is not set
# CONFIG_SERIAL_AMBA_PL011 is not set
# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
# CONFIG_SERIAL_MAX3100 is not set
CONFIG_SERIAL_MAX310X=y
CONFIG_SERIAL_UARTLITE=y
CONFIG_SERIAL_UARTLITE_CONSOLE=y
CONFIG_SERIAL_UARTLITE_NR_UARTS=16
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_BCM63XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
CONFIG_SERIAL_XILINX_PS_UART=y
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers
CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
# CONFIG_HVC_DCC is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
# CONFIG_VIRTIO_CONSOLE is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
# CONFIG_TCG_TPM is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
CONFIG_AXI_INTR_MONITOR=y
# CONFIG_RANDOM_TRUST_CPU is not set
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
# end of Character devices
#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
#
# Multiplexer I2C Chip support
#
# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
# CONFIG_I2C_MUX_GPIO is not set
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=y
CONFIG_I2C_MUX_PCA9541=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_I2C_MUX_PINCTRL is not set
# CONFIG_I2C_MUX_REG is not set
# CONFIG_I2C_DEMUX_PINCTRL is not set
# CONFIG_I2C_MUX_MLXCPLD is not set
# end of Multiplexer I2C Chip support
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y
#
# I2C Hardware Bus support
#
#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_CADENCE=y
# CONFIG_I2C_CBUS_GPIO is not set
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EMEV2 is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_RK3X is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
CONFIG_I2C_XILINX=y
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_VIRTIO is not set
# end of I2C Hardware Bus support
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_SLAVE is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support
# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
CONFIG_SPI_AXI_SPI_ENGINE=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_CADENCE=y
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_PXA2XX is not set
# CONFIG_SPI_ROCKCHIP is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
CONFIG_SPI_AD9250FMC=y
CONFIG_SPI_XILINX=y
CONFIG_SPI_ZYNQMP_GQSPI=y
# CONFIG_SPI_AMD is not set
#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set
#
# SPI Protocol Masters
#
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set
#
# PPS generators support
#
#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
# CONFIG_DP83640_PHY is not set
# CONFIG_PTP_1588_CLOCK_INES is not set
CONFIG_PTP_1588_CLOCK_KVM=y
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
CONFIG_PTP_1588_CLOCK_XILINX=y
# CONFIG_PTP_1588_CLOCK_OCP is not set
# end of PTP clock support
CONFIG_PINCTRL=y
CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_MCP23S08 is not set
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_SX150X is not set
# CONFIG_PINCTRL_STMFX is not set
CONFIG_PINCTRL_ZYNQMP=y
# CONFIG_PINCTRL_OCELOT is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_EXAR is not set
# CONFIG_GPIO_FTGPIO010 is not set
# CONFIG_GPIO_GENERIC_PLATFORM is not set
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
# CONFIG_GPIO_PL061 is not set
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
# CONFIG_GPIO_SIFIVE is not set
# CONFIG_GPIO_SYSCON is not set
# CONFIG_GPIO_XGENE is not set
CONFIG_GPIO_XILINX=y
CONFIG_GPIO_ZYNQ=y
CONFIG_GPIO_ZYNQMP_MODEPIN=y
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers
#
# I2C GPIO expanders
#
CONFIG_GPIO_ADP5588=y
CONFIG_GPIO_ADP5588_IRQ=y
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
CONFIG_GPIO_PCA953X=y
# CONFIG_GPIO_PCA953X_IRQ is not set
# CONFIG_GPIO_PCA9570 is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_SLG7XL45106 is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders
#
# MFD GPIO expanders
#
CONFIG_GPIO_ADP5520=y
CONFIG_GPIO_TPS65086=y
# end of MFD GPIO expanders
#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders
#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
CONFIG_GPIO_ADI_DAQ1=y
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders
#
# USB GPIO expanders
#
# end of USB GPIO expanders
#
# Virtual GPIO drivers
#
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_GPIO_VIRTIO is not set
# end of Virtual GPIO drivers
# CONFIG_W1 is not set
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
# CONFIG_POWER_RESET_GPIO is not set
# CONFIG_POWER_RESET_GPIO_RESTART is not set
CONFIG_POWER_RESET_LTC2952=y
# CONFIG_POWER_RESET_REGULATOR is not set
# CONFIG_POWER_RESET_RESTART is not set
# CONFIG_POWER_RESET_TPS65086 is not set
# CONFIG_POWER_RESET_XGENE is not set
# CONFIG_POWER_RESET_SYSCON is not set
# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
# CONFIG_SYSCON_REBOOT_MODE is not set
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_TEST_POWER is not set
CONFIG_CHARGER_ADP5061=y
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
CONFIG_CHARGER_LT3651=y
CONFIG_CHARGER_LTC4162L=y
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_BQ256XX is not set
# CONFIG_CHARGER_SMB347 is not set
CONFIG_BATTERY_GAUGE_LTC2941=y
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Native drivers
#
CONFIG_SENSORS_AD7314=y
CONFIG_SENSORS_AD7414=y
CONFIG_SENSORS_AD7418=y
CONFIG_SENSORS_ADM1021=y
CONFIG_SENSORS_ADM1025=y
CONFIG_SENSORS_ADM1026=y
CONFIG_SENSORS_ADM1029=y
CONFIG_SENSORS_ADM1031=y
CONFIG_SENSORS_ADM1177=y
CONFIG_SENSORS_ADM9240=y
CONFIG_SENSORS_ADT7X10=y
CONFIG_SENSORS_ADT7310=y
CONFIG_SENSORS_ADT7410=y
CONFIG_SENSORS_ADT7411=y
CONFIG_SENSORS_ADT7462=y
CONFIG_SENSORS_ADT7470=y
CONFIG_SENSORS_ADT7475=y
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
CONFIG_SENSORS_AXI_FAN_CONTROL=y
# CONFIG_SENSORS_ASPEED is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
# CONFIG_SENSORS_DRIVETEMP is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
# CONFIG_SENSORS_GPIO_FAN is not set
# CONFIG_SENSORS_HIH6130 is not set
CONFIG_SENSORS_IIO_HWMON=y
# CONFIG_SENSORS_IT87 is not set
CONFIG_SENSORS_JC42=y
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
CONFIG_SENSORS_LTC2945=y
CONFIG_SENSORS_LTC2947=y
CONFIG_SENSORS_LTC2947_I2C=y
CONFIG_SENSORS_LTC2947_SPI=y
CONFIG_SENSORS_LTC2990=y
CONFIG_SENSORS_LTC2992=y
CONFIG_SENSORS_LTC4151=y
CONFIG_SENSORS_LTC4215=y
CONFIG_SENSORS_LTC4222=y
CONFIG_SENSORS_LTC4245=y
CONFIG_SENSORS_LTC4260=y
CONFIG_SENSORS_LTC4261=y
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
CONFIG_MAX31827=y
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
CONFIG_SENSORS_LM87=y
CONFIG_SENSORS_LM90=y
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_PCF8591 is not set
CONFIG_PMBUS=y
CONFIG_SENSORS_PMBUS=y
CONFIG_SENSORS_ADM1266=y
CONFIG_SENSORS_ADM1275=y
# CONFIG_SENSORS_BEL_PFE is not set
# CONFIG_SENSORS_BPA_RS600 is not set
# CONFIG_SENSORS_FSP_3Y is not set
# CONFIG_SENSORS_IBM_CFFPS is not set
# CONFIG_SENSORS_DPS920AB is not set
# CONFIG_SENSORS_INSPUR_IPSPS is not set
# CONFIG_SENSORS_IR35221 is not set
# CONFIG_SENSORS_IR36021 is not set
# CONFIG_SENSORS_IR38064 is not set
# CONFIG_SENSORS_IRPS5401 is not set
# CONFIG_SENSORS_ISL68137 is not set
# CONFIG_SENSORS_LM25066 is not set
CONFIG_SENSORS_LTC2978=y
CONFIG_SENSORS_LTC2978_REGULATOR=y
CONFIG_SENSORS_LTC3815=y
# CONFIG_SENSORS_MAX15301 is not set
# CONFIG_SENSORS_MAX16064 is not set
# CONFIG_SENSORS_MAX16601 is not set
# CONFIG_SENSORS_MAX20730 is not set
CONFIG_SENSORS_MAX20751=y
# CONFIG_SENSORS_MAX31785 is not set
# CONFIG_SENSORS_MAX34440 is not set
# CONFIG_SENSORS_MAX8688 is not set
# CONFIG_SENSORS_MP2888 is not set
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_PIM4328 is not set
# CONFIG_SENSORS_PM6764TR is not set
# CONFIG_SENSORS_PXE1610 is not set
# CONFIG_SENSORS_Q54SJ108A2 is not set
# CONFIG_SENSORS_STPDDC60 is not set
# CONFIG_SENSORS_TPS40422 is not set
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_TPS544 is not set
# CONFIG_SENSORS_UCD9000 is not set
# CONFIG_SENSORS_UCD9200 is not set
# CONFIG_SENSORS_XDPE122 is not set
# CONFIG_SENSORS_ZL6100 is not set
# CONFIG_SENSORS_PWM_FAN is not set
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHT4x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
CONFIG_SENSORS_INA2XX=y
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_GPIO_WATCHDOG is not set
CONFIG_XILINX_WATCHDOG=y
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
# CONFIG_ARM_SBSA_WATCHDOG is not set
CONFIG_CADENCE_WATCHDOG=y
# CONFIG_DW_WATCHDOG is not set
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_MEN_A21_WDT is not set
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
# CONFIG_BCMA is not set
#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
CONFIG_PMIC_ADP5520=y
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_INTEL_PMT is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_RK808 is not set
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
CONFIG_MFD_TPS65086=y
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
CONFIG_REGULATOR_AD5398=y
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_FAN53880 is not set
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
CONFIG_REGULATOR_LTC3589=y
CONFIG_REGULATOR_LTC3676=y
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_PCA9450 is not set
# CONFIG_REGULATOR_PF8X00 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
# CONFIG_REGULATOR_PWM is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
CONFIG_REGULATOR_TPS65086=y
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_REGULATOR_VCTRL is not set
# CONFIG_RC_CORE is not set
CONFIG_CEC_CORE=y
CONFIG_MEDIA_CEC_SUPPORT=y
# CONFIG_CEC_CH7322 is not set
# CONFIG_USB_PULSE8_CEC is not set
# CONFIG_USB_RAINSHADOW_CEC is not set
CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_SUPPORT_FILTER is not set
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types
#
# Media core support
#
CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=y
# end of Media core support
#
# Video4Linux options
#
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_V4L2_MEM2MEM_DEV=y
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
# end of Video4Linux options
#
# Media controller options
#
# CONFIG_MEDIA_CONTROLLER_DVB is not set
# end of Media controller options
#
# Digital TV options
#
# CONFIG_DVB_MMAP is not set
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=16
CONFIG_DVB_DYNAMIC_MINORS=y
# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
# CONFIG_DVB_ULE_DEBUG is not set
# end of Digital TV options
#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y
#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=y
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
# CONFIG_USB_GSPCA is not set
# CONFIG_USB_PWC is not set
# CONFIG_VIDEO_CPIA2 is not set
# CONFIG_USB_ZR364XX is not set
# CONFIG_USB_STKWEBCAM is not set
# CONFIG_USB_S2255 is not set
# CONFIG_VIDEO_USBTV is not set
#
# Analog TV USB devices
#
# CONFIG_VIDEO_PVRUSB2 is not set
# CONFIG_VIDEO_HDPVR is not set
# CONFIG_VIDEO_STK1160_COMMON is not set
# CONFIG_VIDEO_GO7007 is not set
#
# Analog/digital TV USB devices
#
# CONFIG_VIDEO_AU0828 is not set
# CONFIG_VIDEO_CX231XX is not set
#
# Digital TV USB devices
#
# CONFIG_DVB_USB_V2 is not set
# CONFIG_DVB_TTUSB_BUDGET is not set
# CONFIG_DVB_TTUSB_DEC is not set
# CONFIG_SMS_USB_DRV is not set
# CONFIG_DVB_B2C2_FLEXCOP_USB is not set
# CONFIG_DVB_AS102 is not set
#
# Webcam, TV (analog/digital) USB devices
#
# CONFIG_VIDEO_EM28XX is not set
#
# Software defined radio USB devices
#
# CONFIG_USB_AIRSPY is not set
# CONFIG_USB_HACKRF is not set
# CONFIG_USB_MSI2500 is not set
# CONFIG_MEDIA_PCI_SUPPORT is not set
CONFIG_RADIO_ADAPTERS=y
# CONFIG_RADIO_SI470X is not set
# CONFIG_RADIO_SI4713 is not set
# CONFIG_USB_MR800 is not set
# CONFIG_USB_DSBR is not set
# CONFIG_RADIO_MAXIRADIO is not set
# CONFIG_RADIO_SHARK is not set
# CONFIG_RADIO_SHARK2 is not set
# CONFIG_USB_KEENE is not set
# CONFIG_USB_RAREMONO is not set
# CONFIG_USB_MA901 is not set
# CONFIG_RADIO_TEA5764 is not set
# CONFIG_RADIO_SAA7706H is not set
# CONFIG_RADIO_TEF6862 is not set
# CONFIG_RADIO_WL1273 is not set
# CONFIG_RADIO_WL128X is not set
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_VIDEO_CAFE_CCIC is not set
# CONFIG_VIDEO_CADENCE is not set
# CONFIG_VIDEO_ASPEED is not set
# CONFIG_VIDEO_MUX is not set
CONFIG_VIDEO_AXI_HDMI_RX=y
# CONFIG_VIDEO_IMAGEON_BRIDGE is not set
CONFIG_VIDEO_XILINX=y
CONFIG_VIDEO_XILINX_CSI2RXSS=y
CONFIG_VIDEO_XILINX_AXI4S_SWITCH=y
CONFIG_VIDEO_XILINX_CFA=y
CONFIG_VIDEO_XILINX_CRESAMPLE=y
CONFIG_VIDEO_XILINX_DEMOSAIC=y
CONFIG_VIDEO_XILINX_GAMMA=y
# CONFIG_VIDEO_XILINX_HDMI21RXSS is not set
CONFIG_VIDEO_XILINX_HLS=y
CONFIG_VIDEO_XILINX_REMAPPER=y
CONFIG_VIDEO_XILINX_RGB2YUV=y
CONFIG_VIDEO_XILINX_SCALER=y
CONFIG_VIDEO_XILINX_MULTISCALER=y
CONFIG_VIDEO_XILINX_SDIRXSS=y
CONFIG_VIDEO_XILINX_SWITCH=y
CONFIG_VIDEO_XILINX_TPG=y
CONFIG_VIDEO_XILINX_VPSS_CSC=y
CONFIG_VIDEO_XILINX_VPSS_SCALER=y
CONFIG_VIDEO_XILINX_VTC=y
# CONFIG_VIDEO_XILINX_DPRXSS is not set
CONFIG_VIDEO_XILINX_SCD=y
CONFIG_VIDEO_XILINX_M2M=y
# CONFIG_VIDEO_XILINX_AXI4S_BROADCASTER is not set
# CONFIG_VIDEO_XILINX_AXI4S_SUBSETCONV is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
CONFIG_ADI_AXI_VIDEO_FRAME_BUFFER=y
# CONFIG_DVB_PLATFORM_DRIVERS is not set
# CONFIG_SDR_PLATFORM_DRIVERS is not set
#
# MMC/SDIO DVB adapters
#
# CONFIG_SMS_SDIO_DRV is not set
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_DVB_TEST_DRIVERS is not set
# end of Media drivers
#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y
#
# Audio decoders, processors and mixers
#
# CONFIG_VIDEO_TVAUDIO is not set
# CONFIG_VIDEO_TDA7432 is not set
# CONFIG_VIDEO_TDA9840 is not set
# CONFIG_VIDEO_TDA1997X is not set
# CONFIG_VIDEO_TEA6415C is not set
# CONFIG_VIDEO_TEA6420 is not set
# CONFIG_VIDEO_MSP3400 is not set
# CONFIG_VIDEO_CS3308 is not set
# CONFIG_VIDEO_CS5345 is not set
# CONFIG_VIDEO_CS53L32A is not set
# CONFIG_VIDEO_TLV320AIC23B is not set
# CONFIG_VIDEO_UDA1342 is not set
# CONFIG_VIDEO_WM8775 is not set
# CONFIG_VIDEO_WM8739 is not set
# CONFIG_VIDEO_VP27SMPX is not set
# CONFIG_VIDEO_SONY_BTF_MPX is not set
# end of Audio decoders, processors and mixers
#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set
# end of RDS decoders
#
# Video decoders
#
CONFIG_VIDEO_ADV7180=y
CONFIG_VIDEO_ADV7183=y
CONFIG_VIDEO_ADV748X=y
CONFIG_VIDEO_ADV7604=y
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=y
CONFIG_VIDEO_ADV7842_CEC=y
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_SAA7110 is not set
# CONFIG_VIDEO_SAA711X is not set
# CONFIG_VIDEO_TC358743 is not set
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
# CONFIG_VIDEO_TVP7002 is not set
# CONFIG_VIDEO_TW2804 is not set
# CONFIG_VIDEO_TW9903 is not set
# CONFIG_VIDEO_TW9906 is not set
# CONFIG_VIDEO_TW9910 is not set
# CONFIG_VIDEO_VPX3220 is not set
# CONFIG_VIDEO_MAX9286 is not set
#
# Video and audio decoders
#
# CONFIG_VIDEO_SAA717X is not set
# CONFIG_VIDEO_CX25840 is not set
# end of Video decoders
#
# Video encoders
#
# CONFIG_VIDEO_SAA7127 is not set
# CONFIG_VIDEO_SAA7185 is not set
CONFIG_VIDEO_ADV7170=y
CONFIG_VIDEO_ADV7175=y
CONFIG_VIDEO_ADV7343=y
CONFIG_VIDEO_ADV7393=y
CONFIG_VIDEO_AD9389B=y
# CONFIG_VIDEO_AK881X is not set
# CONFIG_VIDEO_THS8200 is not set
# end of Video encoders
#
# Video improvement chips
#
# CONFIG_VIDEO_UPD64031A is not set
# CONFIG_VIDEO_UPD64083 is not set
# end of Video improvement chips
# CONFIG_VIDEO_AP1302 is not set
#
# Audio/Video compression chips
#
# CONFIG_VIDEO_SAA6752HS is not set
# end of Audio/Video compression chips
#
# SDR tuner chips
#
# CONFIG_SDR_MAX2175 is not set
# end of SDR tuner chips
#
# Miscellaneous helper chips
#
# CONFIG_VIDEO_THS7303 is not set
# CONFIG_VIDEO_M52790 is not set
# CONFIG_VIDEO_I2C is not set
# CONFIG_VIDEO_ST_MIPID02 is not set
# end of Miscellaneous helper chips
#
# Camera sensor devices
#
CONFIG_VIDEO_ADDI9036=y
# CONFIG_VIDEO_HI556 is not set
# CONFIG_VIDEO_IMX208 is not set
# CONFIG_VIDEO_IMX214 is not set
# CONFIG_VIDEO_IMX219 is not set
# CONFIG_VIDEO_IMX258 is not set
# CONFIG_VIDEO_IMX274 is not set
# CONFIG_VIDEO_IMX290 is not set
# CONFIG_VIDEO_IMX319 is not set
# CONFIG_VIDEO_IMX334 is not set
# CONFIG_VIDEO_IMX335 is not set
# CONFIG_VIDEO_IMX355 is not set
# CONFIG_VIDEO_IMX412 is not set
# CONFIG_VIDEO_OV02A10 is not set
# CONFIG_VIDEO_OV2640 is not set
# CONFIG_VIDEO_OV2659 is not set
# CONFIG_VIDEO_OV2680 is not set
# CONFIG_VIDEO_OV2685 is not set
# CONFIG_VIDEO_OV5640 is not set
# CONFIG_VIDEO_OV5645 is not set
# CONFIG_VIDEO_OV5647 is not set
# CONFIG_VIDEO_OV5648 is not set
# CONFIG_VIDEO_OV6650 is not set
# CONFIG_VIDEO_OV5670 is not set
# CONFIG_VIDEO_OV5675 is not set
# CONFIG_VIDEO_OV5695 is not set
# CONFIG_VIDEO_OV7251 is not set
# CONFIG_VIDEO_OV772X is not set
# CONFIG_VIDEO_OV7640 is not set
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_OV7740 is not set
# CONFIG_VIDEO_OV8856 is not set
# CONFIG_VIDEO_OV8865 is not set
# CONFIG_VIDEO_OV9282 is not set
# CONFIG_VIDEO_OV9640 is not set
# CONFIG_VIDEO_OV9650 is not set
# CONFIG_VIDEO_OV13858 is not set
# CONFIG_VIDEO_VS6624 is not set
# CONFIG_VIDEO_MT9M001 is not set
# CONFIG_VIDEO_MT9M032 is not set
# CONFIG_VIDEO_MT9M111 is not set
# CONFIG_VIDEO_MT9P031 is not set
# CONFIG_VIDEO_MT9T001 is not set
# CONFIG_VIDEO_MT9T112 is not set
# CONFIG_VIDEO_MT9V011 is not set
# CONFIG_VIDEO_MT9V032 is not set
# CONFIG_VIDEO_MT9V111 is not set
# CONFIG_VIDEO_SR030PC30 is not set
# CONFIG_VIDEO_NOON010PC30 is not set
# CONFIG_VIDEO_M5MOLS is not set
# CONFIG_VIDEO_RDACM20 is not set
# CONFIG_VIDEO_RDACM21 is not set
# CONFIG_VIDEO_RJ54N1 is not set
# CONFIG_VIDEO_S5K6AA is not set
# CONFIG_VIDEO_S5K6A3 is not set
# CONFIG_VIDEO_S5K4ECGX is not set
# CONFIG_VIDEO_S5K5BAF is not set
# CONFIG_VIDEO_CCS is not set
# CONFIG_VIDEO_ET8EK8 is not set
# CONFIG_VIDEO_S5C73M3 is not set
# end of Camera sensor devices
#
# Lens drivers
#
# CONFIG_VIDEO_AD5820 is not set
# CONFIG_VIDEO_AK7375 is not set
# CONFIG_VIDEO_DW9714 is not set
# CONFIG_VIDEO_DW9768 is not set
# CONFIG_VIDEO_DW9807_VCM is not set
# end of Lens drivers
#
# Flash devices
#
CONFIG_VIDEO_ADP1653=y
# CONFIG_VIDEO_LM3560 is not set
# CONFIG_VIDEO_LM3646 is not set
# end of Flash devices
#
# SPI helper chips
#
# CONFIG_VIDEO_GS1662 is not set
# end of SPI helper chips
#
# Media SPI Adapters
#
CONFIG_CXD2880_SPI_DRV=m
# end of Media SPI Adapters
CONFIG_MEDIA_TUNER=y
#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA827X=m
CONFIG_MEDIA_TUNER_TDA18271=m
CONFIG_MEDIA_TUNER_TDA9887=m
CONFIG_MEDIA_TUNER_TEA5761=m
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_MSI001=m
CONFIG_MEDIA_TUNER_MT20XX=m
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC5000=m
CONFIG_MEDIA_TUNER_XC4000=m
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_MC44S803=m
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_TDA18218=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_IT913X=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
# end of Customize TV tuners
#
# Customise DVB Frontends
#
#
# Multistandard (satellite) frontends
#
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
CONFIG_DVB_STV6110x=m
CONFIG_DVB_STV6111=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_M88DS3103=m
#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
CONFIG_DVB_TDA18271C2DD=m
CONFIG_DVB_SI2165=m
CONFIG_DVB_MN88472=m
CONFIG_DVB_MN88473=m
#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_MT312=m
CONFIG_DVB_ZL10036=m
CONFIG_DVB_ZL10039=m
CONFIG_DVB_S5H1420=m
CONFIG_DVB_STV0288=m
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV6110=m
CONFIG_DVB_STV0900=m
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA10086=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_VES1X93=m
CONFIG_DVB_TUNER_ITD1000=m
CONFIG_DVB_TUNER_CX24113=m
CONFIG_DVB_TDA826X=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_CX24116=m
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
CONFIG_DVB_SI21XX=m
CONFIG_DVB_TS2020=m
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_TDA10071=m
#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_SP887X=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=m
CONFIG_DVB_S5H1432=m
CONFIG_DVB_DRXD=m
CONFIG_DVB_L64781=m
CONFIG_DVB_TDA1004X=m
CONFIG_DVB_NXT6000=m
CONFIG_DVB_MT352=m
CONFIG_DVB_ZL10353=m
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
CONFIG_DVB_DIB9000=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_AF9013=m
CONFIG_DVB_EC100=m
CONFIG_DVB_STV0367=m
CONFIG_DVB_CXD2820R=m
CONFIG_DVB_CXD2841ER=m
CONFIG_DVB_RTL2830=m
CONFIG_DVB_RTL2832=m
CONFIG_DVB_RTL2832_SDR=m
CONFIG_DVB_SI2168=m
CONFIG_DVB_ZD1301_DEMOD=m
CONFIG_DVB_CXD2880=m
#
# DVB-C (cable) frontends
#
CONFIG_DVB_VES1820=m
CONFIG_DVB_TDA10021=m
CONFIG_DVB_TDA10023=m
CONFIG_DVB_STV0297=m
#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_BCM3510=m
CONFIG_DVB_LGDT330X=m
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
CONFIG_DVB_LG2160=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
CONFIG_DVB_S5H1411=m
CONFIG_DVB_MXL692=m
#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_S921=m
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m
#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
CONFIG_DVB_TC90522=m
CONFIG_DVB_MN88443X=m
#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=m
CONFIG_DVB_TUNER_DIB0070=m
CONFIG_DVB_TUNER_DIB0090=m
#
# SEC control devices for DVB-S
#
CONFIG_DVB_DRX39XYJ=m
CONFIG_DVB_LNBH25=m
CONFIG_DVB_LNBH29=m
CONFIG_DVB_LNBP21=m
CONFIG_DVB_LNBP22=m
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_A8293=m
CONFIG_DVB_LGS8GL5=m
CONFIG_DVB_LGS8GXX=m
CONFIG_DVB_ATBM8830=m
CONFIG_DVB_TDA665x=m
CONFIG_DVB_IX2505V=m
CONFIG_DVB_M88RS2000=m
CONFIG_DVB_AF9033=m
CONFIG_DVB_HORUS3A=m
CONFIG_DVB_ASCOT2E=m
CONFIG_DVB_HELENE=m
#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=m
CONFIG_DVB_SP2=m
# end of Customise DVB Frontends
#
# Tools to develop new frontends
#
# CONFIG_DVB_DUMMY_FE is not set
# end of Media ancillary drivers
#
# Graphics support
#
# CONFIG_VGA_ARB is not set
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y
#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips
#
# ARM devices
#
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices
# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
CONFIG_DRM_ADI_AXI_HDMI=y
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_QXL is not set
# CONFIG_DRM_VIRTIO_GPU is not set
CONFIG_DRM_PANEL=y
#
# Display Panels
#
# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
# CONFIG_DRM_PANEL_DSI_CM is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_SIMPLE is not set
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y
#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
CONFIG_DRM_I2C_ADV7511=y
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_I2C_ADV7511_CEC=y
# CONFIG_DRM_CDNS_MHDP8546 is not set
# end of Display Interface Bridges
# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_LIMA is not set
# CONFIG_DRM_PANFROST is not set
# CONFIG_DRM_TIDSS is not set
CONFIG_DRM_ZYNQMP_DPSUB=y
CONFIG_DRM_XLNX=y
CONFIG_DRM_XLNX_BRIDGE=y
CONFIG_DRM_XLNX_BRIDGE_DEBUG_FS=y
# CONFIG_DRM_XLNX_DPTX is not set
CONFIG_DRM_XLNX_DSI=y
# CONFIG_DRM_XLNX_HDMITX is not set
CONFIG_DRM_XLNX_MIXER=y
CONFIG_DRM_XLNX_PL_DISP=y
CONFIG_DRM_XLNX_SDI=y
CONFIG_DRM_XLNX_BRIDGE_CSC=y
CONFIG_DRM_XLNX_BRIDGE_SCALER=y
CONFIG_DRM_XLNX_BRIDGE_VTC=y
# CONFIG_DRM_GUD is not set
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=y
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_ALTERA_VIP is not set
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_ARMCLCD is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
# CONFIG_FB_EFI is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
CONFIG_FB_XILINX=y
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices
#
# Backlight & LCD device support
#
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_PWM is not set
# CONFIG_BACKLIGHT_QCOM_WLED is not set
CONFIG_BACKLIGHT_ADP5520=y
CONFIG_BACKLIGHT_ADP8860=y
CONFIG_BACKLIGHT_ADP8870=y
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_LED is not set
# end of Backlight & LCD device support
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y
#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support
# CONFIG_LOGO is not set
# end of Graphics support
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
# CONFIG_SND_HRTIMER is not set
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_PCI is not set
#
# HD-Audio
#
# end of HD-Audio
CONFIG_SND_HDA_PREALLOC_SIZE=64
CONFIG_SND_SPI=y
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_USB_6FIRE is not set
# CONFIG_SND_USB_HIFACE is not set
# CONFIG_SND_BCD2000 is not set
# CONFIG_SND_USB_POD is not set
# CONFIG_SND_USB_PODHD is not set
# CONFIG_SND_USB_TONEPORT is not set
# CONFIG_SND_USB_VARIAX is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_SOC_ADI=y
CONFIG_SND_SOC_ADI_AXI_I2S=y
CONFIG_SND_SOC_ADI_AXI_SPDIF=y
CONFIG_SND_SOC_ADRV936X_BOX=y
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
# CONFIG_SND_DESIGNWARE_I2S is not set
#
# SoC Audio for Freescale CPUs
#
#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_FSL_XCVR is not set
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs
# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support
CONFIG_SND_SOC_XILINX_DP=y
CONFIG_SND_SOC_XILINX_SDI=y
CONFIG_SND_SOC_XILINX_I2S=y
CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y
CONFIG_SND_SOC_XILINX_SPDIF=y
CONFIG_SND_SOC_XILINX_PL_SND_CARD=y
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y
#
# CODEC drivers
#
# CONFIG_SND_SOC_AC97_CODEC is not set
CONFIG_SND_SOC_AD1836=y
CONFIG_SND_SOC_AD193X=y
CONFIG_SND_SOC_AD193X_SPI=y
CONFIG_SND_SOC_AD193X_I2C=y
# CONFIG_SND_SOC_AD1980 is not set
CONFIG_SND_SOC_AD73311=y
CONFIG_SND_SOC_ADAU_UTILS=y
CONFIG_SND_SOC_ADAU1372=y
CONFIG_SND_SOC_ADAU1372_I2C=y
CONFIG_SND_SOC_ADAU1372_SPI=y
CONFIG_SND_SOC_ADAU1373=y
CONFIG_SND_SOC_ADAU1701=y
CONFIG_SND_SOC_ADAU17X1=y
CONFIG_SND_SOC_ADAU1761=y
CONFIG_SND_SOC_ADAU1761_I2C=y
CONFIG_SND_SOC_ADAU1761_SPI=y
CONFIG_SND_SOC_ADAU1781=y
CONFIG_SND_SOC_ADAU1781_I2C=y
CONFIG_SND_SOC_ADAU1781_SPI=y
CONFIG_SND_SOC_ADAU1977=y
CONFIG_SND_SOC_ADAU1977_SPI=y
CONFIG_SND_SOC_ADAU1977_I2C=y
CONFIG_SND_SOC_ADAU7002=y
CONFIG_SND_SOC_ADAU7118=y
CONFIG_SND_SOC_ADAU7118_HW=y
CONFIG_SND_SOC_ADAU7118_I2C=y
CONFIG_SND_SOC_ADAV80X=y
CONFIG_SND_SOC_ADAV801=y
CONFIG_SND_SOC_ADAV803=y
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4118 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_BD28623 is not set
# CONFIG_SND_SOC_BT_SCO is not set
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS35L36 is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4341 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
# CONFIG_SND_SOC_CX2072X is not set
# CONFIG_SND_SOC_DA7213 is not set
# CONFIG_SND_SOC_DMIC is not set
CONFIG_SND_SOC_HDMI_CODEC=y
# CONFIG_SND_SOC_ES7134 is not set
# CONFIG_SND_SOC_ES7241 is not set
# CONFIG_SND_SOC_ES8316 is not set
# CONFIG_SND_SOC_ES8328_I2C is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_GTM601 is not set
# CONFIG_SND_SOC_ICS43432 is not set
# CONFIG_SND_SOC_INNO_RK3036 is not set
# CONFIG_SND_SOC_MAX98088 is not set
# CONFIG_SND_SOC_MAX98357A is not set
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
# CONFIG_SND_SOC_MAX98927 is not set
# CONFIG_SND_SOC_MAX98373_I2C is not set
# CONFIG_SND_SOC_MAX98390 is not set
# CONFIG_SND_SOC_MAX9860 is not set
# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_I2C is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_I2C is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM5102A is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3328 is not set
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
# CONFIG_SND_SOC_RT5640 is not set
# CONFIG_SND_SOC_RT5659 is not set
# CONFIG_SND_SOC_SGTL5000 is not set
CONFIG_SND_SOC_SIGMADSP=y
CONFIG_SND_SOC_SIGMADSP_I2C=y
CONFIG_SND_SOC_SIGMADSP_REGMAP=y
# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set
# CONFIG_SND_SOC_SIMPLE_MUX is not set
# CONFIG_SND_SOC_SPDIF is not set
CONFIG_SND_SOC_SSM2305=y
CONFIG_SND_SOC_SSM2518=y
CONFIG_SND_SOC_SSM2602=y
CONFIG_SND_SOC_SSM2602_SPI=y
CONFIG_SND_SOC_SSM2602_I2C=y
CONFIG_SND_SOC_SSM4567=y
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TFA989X is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
# CONFIG_SND_SOC_TLV320ADCX140 is not set
CONFIG_SND_SOC_TS3A227E=y
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_UDA1334 is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731 is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
# CONFIG_SND_SOC_WM8904 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_MT6358 is not set
# CONFIG_SND_SOC_MT6660 is not set
# CONFIG_SND_SOC_NAU8315 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8822 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
# end of CODEC drivers
CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
# CONFIG_SND_AUDIO_GRAPH_CARD is not set
# CONFIG_SND_VIRTIO is not set
#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y
#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACCUTOUCH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_ASUS is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_BETOP_FF is not set
# CONFIG_HID_BIGBEN_FF is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_COUGAR is not set
# CONFIG_HID_MACALLY is not set
# CONFIG_HID_PRODIKEYS is not set
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CREATIVE_SB0540 is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELAN is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_ELO is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_VIEWSONIC is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
# CONFIG_HID_ITE is not set
# CONFIG_HID_JABRA is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LED is not set
# CONFIG_HID_LENOVO is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MALTRON is not set
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_REDRAGON is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NTI is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PENMOUNT is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PLAYSTATION is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_RETRODE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SEMITEK is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEAM is not set
# CONFIG_HID_STEELSERIES is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_RMI is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_THINGM is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_ALPS is not set
# CONFIG_HID_MCP2221 is not set
# end of Special HID drivers
#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
CONFIG_USB_HIDDEV=y
# end of USB HID support
#
# I2C HID support
#
# CONFIG_I2C_HID_OF is not set
# CONFIG_I2C_HID_OF_GOODIX is not set
# end of I2C HID support
# end of HID support
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
# CONFIG_USB_LED_TRIG is not set
CONFIG_USB_ULPI_BUS=y
# CONFIG_USB_CONN_GPIO is not set
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=y
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
# CONFIG_USB_MON is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
# CONFIG_USB_EHCI_FSL is not set
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_FOTG210_HCD is not set
# CONFIG_USB_MAX3421_HCD is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_TEST_MODE is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_REALTEK is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_STORAGE_ENE_UB6250 is not set
CONFIG_USB_UAS=y
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USBIP_CORE is not set
# CONFIG_USB_CDNS_SUPPORT is not set
# CONFIG_USB_MUSB_HDRC is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y
# CONFIG_USB_DWC3_OTG is not set
#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_HAPS=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3_XILINX=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set
#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
# CONFIG_USB_DWC2_PCI is not set
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_PCI=y
CONFIG_USB_CHIPIDEA_MSM=y
CONFIG_USB_CHIPIDEA_IMX=y
CONFIG_USB_CHIPIDEA_GENERIC=y
CONFIG_USB_CHIPIDEA_TEGRA=y
# CONFIG_USB_ISP1760 is not set
#
# USB port drivers
#
CONFIG_USB_SERIAL=y
# CONFIG_USB_SERIAL_CONSOLE is not set
CONFIG_USB_SERIAL_GENERIC=y
# CONFIG_USB_SERIAL_SIMPLE is not set
# CONFIG_USB_SERIAL_AIRCABLE is not set
# CONFIG_USB_SERIAL_ARK3116 is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_CH341 is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_CP210X is not set
# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
# CONFIG_USB_SERIAL_EMPEG is not set
CONFIG_USB_SERIAL_FTDI_SIO=y
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_IPAQ is not set
# CONFIG_USB_SERIAL_IR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
# CONFIG_USB_SERIAL_F81232 is not set
# CONFIG_USB_SERIAL_F8153X is not set
# CONFIG_USB_SERIAL_GARMIN is not set
# CONFIG_USB_SERIAL_IPW is not set
# CONFIG_USB_SERIAL_IUU is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KLSI is not set
# CONFIG_USB_SERIAL_KOBIL_SCT is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_METRO is not set
# CONFIG_USB_SERIAL_MOS7720 is not set
# CONFIG_USB_SERIAL_MOS7840 is not set
# CONFIG_USB_SERIAL_MXUPORT is not set
# CONFIG_USB_SERIAL_NAVMAN is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_OTI6858 is not set
# CONFIG_USB_SERIAL_QCAUX is not set
# CONFIG_USB_SERIAL_QUALCOMM is not set
# CONFIG_USB_SERIAL_SPCP8X5 is not set
# CONFIG_USB_SERIAL_SAFE is not set
# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
# CONFIG_USB_SERIAL_SYMBOL is not set
# CONFIG_USB_SERIAL_TI is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OPTION is not set
# CONFIG_USB_SERIAL_OMNINET is not set
# CONFIG_USB_SERIAL_OPTICON is not set
# CONFIG_USB_SERIAL_XSENS_MT is not set
# CONFIG_USB_SERIAL_WISHBONE is not set
# CONFIG_USB_SERIAL_SSU100 is not set
# CONFIG_USB_SERIAL_QT2 is not set
CONFIG_USB_SERIAL_UPD78F0730=y
# CONFIG_USB_SERIAL_XR is not set
# CONFIG_USB_SERIAL_DEBUG is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_APPLE_MFI_FASTCHARGE is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_USB2244 is not set
# CONFIG_USB_USB5744 is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_LINK_LAYER_TEST is not set
#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set
#
# USB Peripheral Controller
#
# CONFIG_USB_FOTG210_UDC is not set
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET2280 is not set
# CONFIG_USB_GOKU is not set
# CONFIG_USB_EG20T is not set
CONFIG_USB_GADGET_XILINX=y
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_NCM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_SUBSET=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_FS=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
# CONFIG_USB_CONFIGFS_OBEX is not set
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
CONFIG_USB_CONFIGFS_F_FS=y
# CONFIG_USB_CONFIGFS_F_UAC1 is not set
# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
# CONFIG_USB_CONFIGFS_F_UAC2 is not set
# CONFIG_USB_CONFIGFS_F_MIDI is not set
# CONFIG_USB_CONFIGFS_F_HID is not set
# CONFIG_USB_CONFIGFS_F_UVC is not set
# CONFIG_USB_CONFIGFS_F_PRINTER is not set
#
# USB Gadget precomposed configurations
#
# CONFIG_USB_ZERO is not set
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_G_NCM is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FUNCTIONFS is not set
# CONFIG_USB_MASS_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_CDC_COMPOSITE is not set
# CONFIG_USB_G_ACM_MS is not set
# CONFIG_USB_G_MULTI is not set
# CONFIG_USB_G_HID is not set
# CONFIG_USB_G_DBGP is not set
# CONFIG_USB_G_WEBCAM is not set
# CONFIG_USB_RAW_GADGET is not set
# end of USB Gadget precomposed configurations
CONFIG_TYPEC=y
# CONFIG_TYPEC_TCPM is not set
# CONFIG_TYPEC_UCSI is not set
CONFIG_TYPEC_TPS6598X=y
# CONFIG_TYPEC_HD3SS3220 is not set
# CONFIG_TYPEC_STUSB160X is not set
#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
# end of USB Type-C Multiplexer/DeMultiplexer Switch support
#
# USB Type-C Alternate Mode drivers
#
# CONFIG_TYPEC_DP_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers
CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
# CONFIG_MMC_SDHCI_OF_ASPEED is not set
# CONFIG_MMC_SDHCI_OF_AT91 is not set
# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set
# CONFIG_MMC_SDHCI_CADENCE is not set
# CONFIG_MMC_SDHCI_F_SDH30 is not set
# CONFIG_MMC_SDHCI_MILBEAUT is not set
# CONFIG_MMC_TIFM_SD is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_USDHI6ROL0 is not set
CONFIG_MMC_CQHCI=y
# CONFIG_MMC_HSQ is not set
# CONFIG_MMC_TOSHIBA_PCI is not set
# CONFIG_MMC_MTK is not set
# CONFIG_MMC_SDHCI_XENON is not set
# CONFIG_MMC_SDHCI_OMAP is not set
# CONFIG_MMC_SDHCI_AM654 is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
# CONFIG_LEDS_CLASS_MULTICOLOR is not set
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
# CONFIG_LEDS_AW2013 is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_EL15203000 is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3532 is not set
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_LM3692X is not set
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
# CONFIG_LEDS_DAC124S085 is not set
# CONFIG_LEDS_PWM is not set
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
CONFIG_LEDS_ADP5520=y
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set
#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
# CONFIG_LEDS_SYSCON is not set
# CONFIG_LEDS_MLXREG is not set
# CONFIG_LEDS_USER is not set
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set
#
# Flash and Torch LED drivers
#
# CONFIG_LEDS_AAT1290 is not set
CONFIG_LEDS_AS3645A=y
# CONFIG_LEDS_KTD2692 is not set
# CONFIG_LEDS_LM3601X is not set
# CONFIG_LEDS_RT4505 is not set
# CONFIG_LEDS_RT8515 is not set
# CONFIG_LEDS_SGM3140 is not set
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
# CONFIG_LEDS_TRIGGER_DISK is not set
# CONFIG_LEDS_TRIGGER_MTD is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
# CONFIG_LEDS_TRIGGER_PANIC is not set
# CONFIG_LEDS_TRIGGER_NETDEV is not set
# CONFIG_LEDS_TRIGGER_PATTERN is not set
# CONFIG_LEDS_TRIGGER_AUDIO is not set
# CONFIG_LEDS_TRIGGER_TTY is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_THUNDERX is not set
CONFIG_EDAC_SYNOPSYS=y
CONFIG_EDAC_ZYNQMP_OCM=y
# CONFIG_EDAC_XGENE is not set
# CONFIG_EDAC_DMC520 is not set
# CONFIG_EDAC_XILINX_DDR is not set
# CONFIG_EDAC_XILINX_XILSEM is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
# CONFIG_RTC_DRV_ABX80X is not set
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_HYM8563 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
# CONFIG_RTC_DRV_SD3078 is not set
#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y
#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set
# CONFIG_RTC_DRV_RX6110 is not set
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
# CONFIG_RTC_DRV_EFI is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
CONFIG_RTC_DRV_ZYNQMP=y
#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PL030 is not set
# CONFIG_RTC_DRV_PL031 is not set
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set
#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set
#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
# CONFIG_AMBA_PL08X is not set
CONFIG_AXI_DMAC=y
# CONFIG_BCM_SBA_RAID is not set
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_HISI_DMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
# CONFIG_PL330_DMA is not set
# CONFIG_PLX_DMA is not set
CONFIG_XILINX_DMA=m
CONFIG_XILINX_ZYNQMP_DMA=y
CONFIG_XILINX_ZYNQMP_DPDMA=y
CONFIG_XILINX_FRMBUF=y
# CONFIG_XILINX_PS_PCIE_DMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
# CONFIG_DW_DMAC is not set
# CONFIG_DW_DMAC_PCI is not set
# CONFIG_DW_EDMA is not set
# CONFIG_DW_EDMA_PCIE is not set
# CONFIG_SF_PDMA is not set
#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
CONFIG_DMATEST=y
CONFIG_DMA_ENGINE_RAID=y
# CONFIG_XILINX_DMATEST is not set
# CONFIG_XILINX_VDMATEST is not set
#
# DMABUF options
#
CONFIG_SYNC_FILE=y
# CONFIG_SW_SYNC is not set
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_HEAPS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
# end of DMABUF options
# CONFIG_AUXDISPLAY is not set
CONFIG_UIO=y
# CONFIG_UIO_CIF is not set
CONFIG_UIO_PDRV_GENIRQ=m
CONFIG_UIO_DMEM_GENIRQ=m
# CONFIG_UIO_AEC is not set
# CONFIG_UIO_SERCOS3 is not set
# CONFIG_UIO_PCI_GENERIC is not set
# CONFIG_UIO_NETX is not set
# CONFIG_UIO_PRUSS is not set
# CONFIG_UIO_MF624 is not set
CONFIG_UIO_XILINX_APM=y
# CONFIG_UIO_XILINX_AI_ENGINE is not set
# CONFIG_VFIO is not set
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO=y
CONFIG_VIRTIO_MENU=y
# CONFIG_VIRTIO_PCI is not set
# CONFIG_VIRTIO_BALLOON is not set
# CONFIG_VIRTIO_INPUT is not set
# CONFIG_VIRTIO_MMIO is not set
# CONFIG_VDPA is not set
CONFIG_VHOST_MENU=y
# CONFIG_VHOST_NET is not set
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support
# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
# CONFIG_PRISM2_USB is not set
# CONFIG_RTL8192U is not set
# CONFIG_RTLLIB is not set
# CONFIG_RTL8723BS is not set
# CONFIG_R8712U is not set
# CONFIG_R8188EU is not set
# CONFIG_RTS5208 is not set
# CONFIG_VT6655 is not set
# CONFIG_VT6656 is not set
#
# IIO staging drivers
#
#
# Accelerometers
#
CONFIG_ADIS16203=y
CONFIG_ADIS16240=y
# end of Accelerometers
#
# Analog to digital converters
#
CONFIG_AD7816=y
CONFIG_AD7280=y
# end of Analog to digital converters
#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=y
CONFIG_ADT7316_SPI=y
CONFIG_ADT7316_I2C=y
# end of Analog digital bi-direction converters
#
# Capacitance to digital converters
#
CONFIG_AD7746=y
# end of Capacitance to digital converters
#
# Direct Digital Synthesis
#
CONFIG_AD9832=y
CONFIG_AD9834=y
# end of Direct Digital Synthesis
#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=y
# end of Network Analyzer, Impedance Converters
#
# Active energy metering IC
#
CONFIG_ADE7854=y
CONFIG_ADE7854_I2C=y
CONFIG_ADE7854_SPI=y
# end of Active energy metering IC
#
# Resolver to digital converters
#
CONFIG_AD2S1210=y
# end of Resolver to digital converters
# end of IIO staging drivers
# CONFIG_FB_SM750 is not set
# CONFIG_STAGING_MEDIA is not set
#
# Android
#
# CONFIG_ASHMEM is not set
# end of Android
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_XILINX_APF is not set
CONFIG_FB_TFT=y
# CONFIG_FB_TFT_AGM1264K_FL is not set
# CONFIG_FB_TFT_BD663474 is not set
# CONFIG_FB_TFT_HX8340BN is not set
# CONFIG_FB_TFT_HX8347D is not set
# CONFIG_FB_TFT_HX8353D is not set
# CONFIG_FB_TFT_HX8357D is not set
# CONFIG_FB_TFT_ILI9163 is not set
# CONFIG_FB_TFT_ILI9320 is not set
# CONFIG_FB_TFT_ILI9325 is not set
# CONFIG_FB_TFT_ILI9340 is not set
# CONFIG_FB_TFT_ILI9341 is not set
# CONFIG_FB_TFT_ILI9481 is not set
# CONFIG_FB_TFT_ILI9486 is not set
# CONFIG_FB_TFT_PCD8544 is not set
# CONFIG_FB_TFT_RA8875 is not set
# CONFIG_FB_TFT_S6D02A1 is not set
# CONFIG_FB_TFT_S6D1121 is not set
CONFIG_FB_TFT_SEPS525=y
# CONFIG_FB_TFT_SH1106 is not set
# CONFIG_FB_TFT_SSD1289 is not set
# CONFIG_FB_TFT_SSD1305 is not set
# CONFIG_FB_TFT_SSD1306 is not set
# CONFIG_FB_TFT_SSD1331 is not set
# CONFIG_FB_TFT_SSD1351 is not set
# CONFIG_FB_TFT_ST7735R is not set
# CONFIG_FB_TFT_ST7789V is not set
# CONFIG_FB_TFT_TINYLCD is not set
# CONFIG_FB_TFT_TLS8204 is not set
# CONFIG_FB_TFT_UC1611 is not set
# CONFIG_FB_TFT_UC1701 is not set
# CONFIG_FB_TFT_UPD161704 is not set
# CONFIG_FB_TFT_WATTEROTT is not set
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_WFX is not set
CONFIG_XILINX_FCLK=y
# CONFIG_XLNX_SYNC is not set
# CONFIG_XLNX_TSMUX is not set
# CONFIG_XROE_FRAMER is not set
# CONFIG_XROE_TRAFFIC_GEN is not set
# CONFIG_SERIAL_UARTLITE_RS485 is not set
# CONFIG_XILINX_TSN is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
#
# Clock driver for ARM Reference designs
#
# CONFIG_ICST is not set
# CONFIG_CLK_SP810 is not set
# end of Clock driver for ARM Reference designs
# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_SI5341=y
# CONFIG_COMMON_CLK_SI5351 is not set
CONFIG_COMMON_CLK_SI514=y
# CONFIG_COMMON_CLK_SI544 is not set
CONFIG_COMMON_CLK_SI570=y
CONFIG_COMMON_CLK_SI5324=y
# CONFIG_COMMON_CLK_IDT8T49N24X is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
CONFIG_COMMON_CLK_AXI_CLKGEN=y
CONFIG_COMMON_CLK_ADI=y
# CONFIG_COMMON_CLK_XGENE is not set
# CONFIG_COMMON_CLK_PWM is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_COMMON_CLK_XLNX_CLKWZRD=y
# CONFIG_COMMON_CLK_XLNX_CLKWZRD_V is not set
#
# Analog Devices Clock Drivers
#
CONFIG_COMMON_CLK_AD9545=y
CONFIG_COMMON_CLK_AD9545_I2C=y
CONFIG_COMMON_CLK_AD9545_SPI=y
# end of Analog Devices Clock Drivers
CONFIG_XILINX_VCU=m
CONFIG_COMMON_CLK_ZYNQMP=y
# CONFIG_HWSPINLOCK is not set
#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
# CONFIG_MICROCHIP_PIT64B is not set
# end of Clock Source drivers
CONFIG_MAILBOX=y
# CONFIG_ARM_MHU is not set
# CONFIG_ARM_MHU_V2 is not set
# CONFIG_PLATFORM_MHU is not set
# CONFIG_PL320_MBOX is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_ZYNQMP_IPI_MBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y
#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# end of Generic IOMMU Pagetable Support
# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
# CONFIG_ARM_SMMU_V3 is not set
# CONFIG_VIRTIO_IOMMU is not set
#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
# CONFIG_REMOTEPROC_CDEV is not set
CONFIG_ZYNQMP_R5_REMOTEPROC=m
# end of Remoteproc drivers
#
# Rpmsg drivers
#
CONFIG_RPMSG=m
# CONFIG_RPMSG_CHAR is not set
CONFIG_RPMSG_NS=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers
# CONFIG_SOUNDWIRE is not set
#
# SOC (System On Chip) specific Drivers
#
#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers
#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers
#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers
#
# i.MX SoC drivers
#
# end of i.MX SoC drivers
#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers
#
# Qualcomm SoC drivers
#
# end of Qualcomm SoC drivers
# CONFIG_SOC_TI is not set
#
# Xilinx SoC drivers
#
CONFIG_ZYNQMP_POWER=y
CONFIG_ZYNQMP_PM_DOMAINS=y
CONFIG_XLNX_EVENT_MANAGER=y
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers
# CONFIG_PM_DEVFREQ is not set
CONFIG_EXTCON=y
#
# Extcon Device Drivers
#
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
# CONFIG_EXTCON_GPIO is not set
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_EXTCON_USBC_TUSB320 is not set
# CONFIG_MEMORY is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_BUFFER_DMA=y
CONFIG_IIO_BUFFER_DMAENGINE=y
CONFIG_IIO_BUFFER_HW_CONSUMER=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=y
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=y
CONFIG_IIO_SW_TRIGGER=y
CONFIG_IIO_TRIGGERED_EVENT=y
#
# Accelerometers
#
CONFIG_ADIS16201=y
CONFIG_ADIS16209=y
CONFIG_ADXL313=y
CONFIG_ADXL313_I2C=y
CONFIG_ADXL313_SPI=y
CONFIG_ADXL345=y
CONFIG_ADXL345_I2C=y
CONFIG_ADXL345_SPI=y
CONFIG_ADXL355=y
CONFIG_ADXL355_I2C=y
CONFIG_ADXL355_SPI=y
CONFIG_ADXL367=y
CONFIG_ADXL367_SPI=y
CONFIG_ADXL367_I2C=y
CONFIG_ADXL372=y
CONFIG_ADXL372_SPI=y
CONFIG_ADXL372_I2C=y
# CONFIG_BMA180 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMA400 is not set
# CONFIG_BMC150_ACCEL is not set
# CONFIG_BMI088_ACCEL is not set
# CONFIG_DA280 is not set
# CONFIG_DA311 is not set
# CONFIG_DMARD06 is not set
# CONFIG_DMARD09 is not set
# CONFIG_DMARD10 is not set
# CONFIG_FXLS8962AF_I2C is not set
# CONFIG_FXLS8962AF_SPI is not set
# CONFIG_IIO_ST_ACCEL_3AXIS is not set
# CONFIG_KXSD9 is not set
# CONFIG_KXCJK1013 is not set
# CONFIG_MC3230 is not set
# CONFIG_MMA7455_I2C is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMA7660 is not set
# CONFIG_MMA8452 is not set
# CONFIG_MMA9551 is not set
# CONFIG_MMA9553 is not set
# CONFIG_MXC4005 is not set
# CONFIG_MXC6255 is not set
# CONFIG_SCA3000 is not set
# CONFIG_SCA3300 is not set
# CONFIG_STK8312 is not set
# CONFIG_STK8BA50 is not set
# end of Accelerometers
#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=y
CONFIG_AD4134=y
CONFIG_AD400X=y
CONFIG_AD4130=y
CONFIG_AD4630=y
CONFIG_AD7091R5=y
CONFIG_AD7124=y
CONFIG_AD7173=y
CONFIG_AD7192=y
CONFIG_AD7266=y
CONFIG_AD7291=y
CONFIG_AD7292=y
CONFIG_AD7298=y
CONFIG_AD738X=y
CONFIG_AD7476=y
CONFIG_AD7606=y
CONFIG_AD7606_IFACE_PARALLEL=y
CONFIG_AD7606_IFACE_SPI=y
CONFIG_AD7766=y
CONFIG_AD7768=y
CONFIG_AD7768_1=y
CONFIG_AD7780=y
CONFIG_AD7791=y
CONFIG_AD7793=y
CONFIG_AD7887=y
CONFIG_AD7923=y
CONFIG_AD7949=y
CONFIG_AD799X=y
CONFIG_AD9963=y
CONFIG_ADAQ8092=y
# CONFIG_ADM1177 is not set
# CONFIG_ADI_AXI_ADC is not set
CONFIG_CF_AXI_ADC=y
CONFIG_AD9081=y
CONFIG_AD9083=y
CONFIG_AD9208=y
CONFIG_AD9361=y
CONFIG_AD9361_EXT_BAND_CONTROL=y
CONFIG_AD9371=y
CONFIG_ADRV9001=y
CONFIG_ADRV9001_COMMON_VERBOSE=y
CONFIG_ADRV9001_ARM_VERBOSE=y
CONFIG_ADRV9001_VALIDATE_PARAMS=y
CONFIG_ADRV9009=y
CONFIG_ADRV9025=y
CONFIG_AD6676=y
CONFIG_AD9467=y
CONFIG_AD9680=y
CONFIG_ADMC=y
CONFIG_CF_AXI_TDD=y
CONFIG_AD_PULSAR=y
CONFIG_AXI_PULSE_CAPTURE=y
CONFIG_AXI_FMCADC5_SYNC=y
# CONFIG_CC10001_ADC is not set
# CONFIG_ENVELOPE_DETECTOR is not set
# CONFIG_HI8435 is not set
# CONFIG_HX711 is not set
CONFIG_LTC2308=y
CONFIG_LTC2387=y
CONFIG_LTC2471=y
CONFIG_LTC2485=y
CONFIG_LTC2496=y
CONFIG_LTC2497=y
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
CONFIG_MAX11410=y
# CONFIG_MAX1241 is not set
# CONFIG_MAX1363 is not set
# CONFIG_MAX9611 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
# CONFIG_MCP3911 is not set
# CONFIG_NAU7802 is not set
# CONFIG_SD_ADC_MODULATOR is not set
# CONFIG_TI_ADC081C is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS1015 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_ADS131E08 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_TI_TSC2046 is not set
# CONFIG_VF610_ADC is not set
CONFIG_XILINX_XADC=y
CONFIG_XILINX_AMS=y
# CONFIG_VERSAL_SYSMON is not set
# end of Analog to digital converters
#
# Analog to digital and digital to analog converters
#
CONFIG_AD74115=y
CONFIG_AD74413R=y
CONFIG_ONE_BIT_ADC_DAC=y
# end of Analog to digital and digital to analog converters
#
# Analog Front Ends
#
# CONFIG_IIO_RESCALE is not set
# end of Analog Front Ends
#
# Amplifiers
#
CONFIG_AD8366=y
CONFIG_AD916X_AMP=y
CONFIG_ADA4250=y
CONFIG_HMC425=y
# end of Amplifiers
#
# Beamformers
#
CONFIG_ADAR1000=y
CONFIG_ADAR3000=y
# end of Beamformers
#
# Capacitance to digital converters
#
CONFIG_AD7150=y
# end of Capacitance to digital converters
#
# Chemical Sensors
#
# CONFIG_ATLAS_PH_SENSOR is not set
# CONFIG_ATLAS_EZO_SENSOR is not set
# CONFIG_BME680 is not set
# CONFIG_CCS811 is not set
# CONFIG_IAQCORE is not set
# CONFIG_PMS7003 is not set
# CONFIG_SCD30_CORE is not set
# CONFIG_SENSIRION_SGP30 is not set
# CONFIG_SENSIRION_SGP40 is not set
# CONFIG_SPS30_I2C is not set
# CONFIG_SPS30_SERIAL is not set
# CONFIG_VZ89X is not set
# end of Chemical Sensors
#
# Hid Sensor IIO Common
#
# end of Hid Sensor IIO Common
#
# IIO SCMI Sensors
#
# end of IIO SCMI Sensors
#
# SSP Sensor Common
#
# CONFIG_IIO_SSP_SENSORHUB is not set
# end of SSP Sensor Common
#
# Digital to analog converters
#
CONFIG_AD3552R=y
CONFIG_AD5064=y
CONFIG_AD5270=y
CONFIG_AD5360=y
CONFIG_AD5380=y
CONFIG_AD5421=y
CONFIG_AD5446=y
CONFIG_AD5449=y
CONFIG_AD5592R_BASE=y
CONFIG_AD5592R=y
CONFIG_AD5593R=y
CONFIG_AD5504=y
CONFIG_AD5624R_SPI=y
CONFIG_LTC2688=y
CONFIG_AD5686=y
CONFIG_AD5686_SPI=y
CONFIG_AD5696_I2C=y
CONFIG_AD5755=y
CONFIG_AD5758=y
CONFIG_AD5761=y
CONFIG_AD5764=y
CONFIG_AD5766=y
CONFIG_AD5770R=y
CONFIG_AD5791=y
CONFIG_AD7293=y
CONFIG_AD7303=y
CONFIG_AD8801=y
# CONFIG_DPOT_DAC is not set
# CONFIG_DS4424 is not set
CONFIG_LTC1660=y
CONFIG_LTC2632=y
# CONFIG_M62332 is not set
# CONFIG_MAX517 is not set
# CONFIG_MAX5821 is not set
# CONFIG_MCP4725 is not set
# CONFIG_MCP4922 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC5571 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_VF610_DAC is not set
# end of Digital to analog converters
#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver
#
# Filters
#
CONFIG_ADMV8818=y
# end of Filters
#
# Frequency Synthesizers DDS/PLL
#
#
# Clock Generator/Distribution
#
CONFIG_AD9508=y
CONFIG_AD9523=y
CONFIG_AD9528=y
CONFIG_AD9548=y
CONFIG_AD9517=y
CONFIG_ADMV1013=y
CONFIG_ADMV1014=y
CONFIG_ADMV4420=y
CONFIG_ADRF6780=y
CONFIG_HMC7044=y
CONFIG_LTC6952=y
# end of Clock Generator/Distribution
#
# Direct Digital Synthesis
#
CONFIG_CF_AXI_DDS=y
CONFIG_CF_AXI_DDS_AD9122=y
CONFIG_CF_AXI_DDS_AD9144=y
CONFIG_CF_AXI_DDS_AD9162=y
CONFIG_CF_AXI_DDS_AD9172=y
CONFIG_CF_AXI_DDS_AD9739A=y
CONFIG_CF_AXI_DDS_AD9783=y
CONFIG_M2K_DAC=y
# end of Direct Digital Synthesis
#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4159=y
CONFIG_ADF4350=y
CONFIG_ADF4360=y
CONFIG_ADF4371=y
CONFIG_ADF4377=y
CONFIG_ADF5355=y
# end of Phase-Locked Loop (PLL) frequency synthesizers
#
# RF Font-Ends
#
CONFIG_ADL5960=y
# end of RF Font-Ends
# end of Frequency Synthesizers DDS/PLL
#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=y
CONFIG_ADIS16130=y
CONFIG_ADIS16136=y
CONFIG_ADIS16260=y
CONFIG_ADXRS290=y
CONFIG_ADXRS450=y
# CONFIG_BMG160 is not set
# CONFIG_FXAS21002C is not set
# CONFIG_MPU3050_I2C is not set
# CONFIG_IIO_ST_GYRO_3AXIS is not set
# CONFIG_ITG3200 is not set
# end of Digital gyroscope sensors
#
# Health Sensors
#
#
# Heart Rate Monitors
#
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
# CONFIG_MAX30100 is not set
# CONFIG_MAX30102 is not set
# end of Heart Rate Monitors
# end of Health Sensors
#
# Humidity sensors
#
# CONFIG_AM2315 is not set
# CONFIG_DHT11 is not set
# CONFIG_HDC100X is not set
# CONFIG_HDC2010 is not set
# CONFIG_HTS221 is not set
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
# CONFIG_SI7020 is not set
# end of Humidity sensors
#
# Inertial measurement units
#
CONFIG_ADIS16400=y
CONFIG_ADIS16460=y
CONFIG_ADIS16475=y
CONFIG_ADIS16480=y
# CONFIG_BMI160_I2C is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_FXOS8700_I2C is not set
# CONFIG_FXOS8700_SPI is not set
# CONFIG_KMX61 is not set
# CONFIG_INV_ICM42600_I2C is not set
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_MPU6050_I2C is not set
# CONFIG_INV_MPU6050_SPI is not set
# CONFIG_IIO_ST_LSM6DSX is not set
# CONFIG_IIO_ST_LSM9DS0 is not set
# end of Inertial measurement units
CONFIG_IIO_ADIS_LIB=y
CONFIG_IIO_ADIS_LIB_BUFFER=y
# CONFIG_ALTERA_ARRIA10_JESD204_PHY is not set
CONFIG_AXI_ADXCVR=y
# CONFIG_AXI_JESD204B is not set
CONFIG_AXI_JESD204_TX=y
CONFIG_AXI_JESD204_RX=y
CONFIG_XILINX_TRANSCEIVER=y
CONFIG_ADI_IIO_FAKEDEV=y
#
# Light sensors
#
# CONFIG_ADJD_S311 is not set
CONFIG_ADUX1020=y
# CONFIG_AL3010 is not set
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
# CONFIG_AS73211 is not set
# CONFIG_BH1750 is not set
# CONFIG_BH1780 is not set
# CONFIG_CM32181 is not set
# CONFIG_CM3232 is not set
# CONFIG_CM3323 is not set
# CONFIG_CM3605 is not set
# CONFIG_CM36651 is not set
# CONFIG_GP2AP002 is not set
# CONFIG_GP2AP020A00F is not set
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_ISL29028 is not set
# CONFIG_ISL29125 is not set
# CONFIG_JSA1212 is not set
# CONFIG_RPR0521 is not set
# CONFIG_LTR501 is not set
# CONFIG_LV0104CS is not set
# CONFIG_MAX44000 is not set
# CONFIG_MAX44009 is not set
# CONFIG_NOA1305 is not set
# CONFIG_OPT3001 is not set
# CONFIG_PA12203001 is not set
# CONFIG_SI1133 is not set
# CONFIG_SI1145 is not set
# CONFIG_STK3310 is not set
# CONFIG_ST_UVIS25 is not set
# CONFIG_TCS3414 is not set
# CONFIG_TCS3472 is not set
# CONFIG_SENSORS_TSL2563 is not set
# CONFIG_TSL2583 is not set
# CONFIG_TSL2591 is not set
# CONFIG_TSL2772 is not set
# CONFIG_TSL4531 is not set
# CONFIG_US5182D is not set
# CONFIG_VCNL4000 is not set
# CONFIG_VCNL4035 is not set
# CONFIG_VEML6030 is not set
# CONFIG_VEML6070 is not set
# CONFIG_VL6180 is not set
# CONFIG_ZOPT2201 is not set
# end of Light sensors
#
# Logic Analyzers
#
CONFIG_M2K_LOGIC_ANALYZER=y
# end of Logic Analyzers
#
# Magnetometer sensors
#
# CONFIG_AK8974 is not set
# CONFIG_AK8975 is not set
# CONFIG_AK09911 is not set
# CONFIG_BMC150_MAGN_I2C is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_MAG3110 is not set
# CONFIG_MMC35240 is not set
# CONFIG_IIO_ST_MAGN_3AXIS is not set
# CONFIG_SENSORS_HMC5843_I2C is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_RM3100_I2C is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_YAMAHA_YAS530 is not set
# end of Magnetometer sensors
#
# Multiplexers
#
# CONFIG_IIO_MUX is not set
CONFIG_IIO_GEN_MUX=y
# end of Multiplexers
#
# IIO Regmap Access Drivers
#
CONFIG_IIO_REGMAP=y
CONFIG_IIO_REGMAP_I2C=y
CONFIG_IIO_REGMAP_SPI=y
# end of IIO Regmap Access Drivers
#
# Inclinometer sensors
#
# end of Inclinometer sensors
#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=y
CONFIG_IIO_INTERRUPT_TRIGGER=y
CONFIG_IIO_TIGHTLOOP_TRIGGER=y
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone
#
# Linear and angular position sensors
#
# end of Linear and angular position sensors
#
# Digital potentiometers
#
CONFIG_AD5110=y
CONFIG_AD5272=y
# CONFIG_DS1803 is not set
# CONFIG_MAX5432 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MCP4018 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
# CONFIG_MCP41010 is not set
# CONFIG_TPL0102 is not set
# end of Digital potentiometers
#
# Digital potentiostats
#
# CONFIG_LMP91000 is not set
# end of Digital potentiostats
#
# Pressure sensors
#
# CONFIG_ABP060MG is not set
# CONFIG_BMP280 is not set
# CONFIG_DLHL60D is not set
# CONFIG_DPS310 is not set
# CONFIG_HP03 is not set
# CONFIG_ICP10100 is not set
# CONFIG_MPL115_I2C is not set
# CONFIG_MPL115_SPI is not set
# CONFIG_MPL3115 is not set
# CONFIG_MS5611 is not set
# CONFIG_MS5637 is not set
# CONFIG_IIO_ST_PRESS is not set
# CONFIG_T5403 is not set
# CONFIG_HP206C is not set
# CONFIG_ZPA2326 is not set
# end of Pressure sensors
#
# Lightning sensors
#
# CONFIG_AS3935 is not set
# end of Lightning sensors
#
# Proximity and distance sensors
#
# CONFIG_ISL29501 is not set
# CONFIG_LIDAR_LITE_V2 is not set
# CONFIG_MB1232 is not set
# CONFIG_PING is not set
# CONFIG_RFD77402 is not set
# CONFIG_SRF04 is not set
# CONFIG_SX9310 is not set
# CONFIG_SX9500 is not set
# CONFIG_SRF08 is not set
# CONFIG_VCNL3020 is not set
# CONFIG_VL53L0X_I2C is not set
# end of Proximity and distance sensors
#
# Resolver to digital converters
#
CONFIG_AD2S90=y
CONFIG_AD2S1200=y
# end of Resolver to digital converters
#
# Temperature sensors
#
CONFIG_LTC2983=y
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_MLX90614 is not set
# CONFIG_MLX90632 is not set
# CONFIG_TMP006 is not set
# CONFIG_TMP007 is not set
# CONFIG_TMP117 is not set
# CONFIG_TSYS01 is not set
# CONFIG_TSYS02D is not set
# CONFIG_MAX31856 is not set
CONFIG_MAX31865=y
# end of Temperature sensors
CONFIG_JESD204=y
CONFIG_JESD204_TOP_DEVICE=y
# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
CONFIG_PWM_AXI_PWMGEN=y
# CONFIG_PWM_DWC is not set
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_PCA9685 is not set
# CONFIG_PWM_CADENCE is not set
#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_XILINX_INTC=y
# CONFIG_IRQCHIP_XILINX_INTC_MODULE_SUPPORT_EXPERIMENTAL is not set
CONFIG_PARTITION_PERCPU=y
# end of IRQ chip support
# CONFIG_IPACK_BUS is not set
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_TI_SYSCON is not set
#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
# CONFIG_PHY_XGENE is not set
# CONFIG_PHY_CAN_TRANSCEIVER is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
CONFIG_PHY_XILINX_ZYNQMP=y
# CONFIG_PHY_XILINX_HDMIPHY is not set
# end of PHY Subsystem
# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set
#
# Performance monitor support
#
# CONFIG_ARM_CCI_PMU is not set
# CONFIG_ARM_CCN is not set
# CONFIG_ARM_CMN is not set
CONFIG_ARM_PMU=y
# CONFIG_ARM_DSU_PMU is not set
# CONFIG_ARM_SPE_PMU is not set
# end of Performance monitor support
CONFIG_RAS=y
# CONFIG_USB4 is not set
#
# Android
#
CONFIG_ANDROID=y
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android
# CONFIG_LIBNVDIMM is not set
# CONFIG_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_AXI_SYSID=y
CONFIG_NVMEM_ZYNQMP=y
# CONFIG_XLNX_SEC_CFG is not set
# CONFIG_NVMEM_RMEM is not set
#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# end of HW tracing support
CONFIG_FPGA=y
# CONFIG_FPGA_MGR_DEBUG_FS is not set
# CONFIG_ALTERA_PR_IP_CORE is not set
# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
# CONFIG_FPGA_MGR_ALTERA_CVP is not set
# CONFIG_FPGA_MGR_XILINX_SPI is not set
# CONFIG_FPGA_MGR_ICE40_SPI is not set
# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
CONFIG_XILINX_AFI_FPGA=y
CONFIG_FPGA_BRIDGE=y
# CONFIG_ALTERA_FREEZE_BRIDGE is not set
CONFIG_XILINX_PR_DECOUPLER=y
CONFIG_FPGA_REGION=y
CONFIG_OF_FPGA_REGION=y
# CONFIG_FPGA_DFL is not set
CONFIG_FPGA_MGR_ZYNQMP_FPGA=y
# CONFIG_FPGA_MGR_VERSAL_FPGA is not set
# CONFIG_FSI is not set
# CONFIG_TEE is not set
CONFIG_MULTIPLEXER=y
#
# Multiplexer drivers
#
CONFIG_MUX_ADG792A=y
CONFIG_MUX_ADGS1408=y
CONFIG_MUX_GPIO=y
# CONFIG_MUX_MMIO is not set
# end of Multiplexer drivers
CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
# CONFIG_COUNTER is not set
# CONFIG_MOST is not set
# end of Device Drivers
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_VALIDATE_FS_PARSER is not set
CONFIG_FS_IOMAP=y
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
CONFIG_BTRFS_FS=y
# CONFIG_BTRFS_FS_POSIX_ACL is not set
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_F2FS_FS is not set
# CONFIG_FS_DAX is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
CONFIG_FILE_LOCKING=y
# CONFIG_FS_ENCRYPTION is not set
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
CONFIG_QUOTA=y
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
CONFIG_PRINT_QUOTA_WARNING=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
# CONFIG_CUSE is not set
# CONFIG_VIRTIO_FS is not set
# CONFIG_OVERLAY_FS is not set
#
# Caches
#
# CONFIG_FSCACHE is not set
# end of Caches
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
# end of CD-ROM/DVD Filesystems
#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_FAT_DEFAULT_UTF8 is not set
# CONFIG_EXFAT_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS3_FS is not set
# end of DOS/FAT/EXFAT/NT Filesystems
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
# CONFIG_PROC_CHILDREN is not set
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=m
# end of Pseudo filesystems
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=y
# CONFIG_ECRYPT_FS_MESSAGING is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_FS_POSIX_ACL=y
CONFIG_JFFS2_FS_SECURITY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_CRAMFS=y
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_PSTORE is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_EROFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
# CONFIG_NFS_SWAP is not set
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=y
CONFIG_PNFS_FLEXFILE_LAYOUT=y
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFS_V4_2_READ_PLUS is not set
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_SUNRPC_BACKCHANNEL=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_SMB_SERVER is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
# CONFIG_NLS_UTF8 is not set
# CONFIG_DLM is not set
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems
#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf"
#
# Kernel hardening options
#
#
# Memory initialization
#
CONFIG_INIT_STACK_NONE=y
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
# end of Kernel hardening options
# end of Security options
CONFIG_XOR_BLOCKS=y
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
# CONFIG_CRYPTO_PCRYPT is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ENGINE=y
#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
# CONFIG_CRYPTO_DH is not set
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
# CONFIG_CRYPTO_ECDSA is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_CURVE25519 is not set
#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_AEGIS128 is not set
# CONFIG_CRYPTO_SEQIV is not set
# CONFIG_CRYPTO_ECHAINIV is not set
#
# Block modes
#
CONFIG_CRYPTO_CBC=y
# CONFIG_CRYPTO_CFB is not set
CONFIG_CRYPTO_CTR=y
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_KEYWRAP is not set
# CONFIG_CRYPTO_ADIANTUM is not set
# CONFIG_CRYPTO_ESSIV is not set
#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set
#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRC32 is not set
CONFIG_CRYPTO_XXHASH=y
CONFIG_CRYPTO_BLAKE2B=y
# CONFIG_CRYPTO_BLAKE2S is not set
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_GHASH=y
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_SHA1 is not set
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_STREEBOG is not set
# CONFIG_CRYPTO_WP512 is not set
#
# Ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set
#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_ZSTD is not set
#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
# CONFIG_CRYPTO_DRBG_CTR is not set
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_USER_API=y
# CONFIG_CRYPTO_USER_API_HASH is not set
CONFIG_CRYPTO_USER_API_SKCIPHER=y
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_HASH_INFO=y
#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
# CONFIG_CRYPTO_LIB_BLAKE2S is not set
# CONFIG_CRYPTO_LIB_CHACHA is not set
# CONFIG_CRYPTO_LIB_CURVE25519 is not set
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
# CONFIG_CRYPTO_LIB_POLY1305 is not set
# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ZYNQMP_KECCAK_384=y
CONFIG_CRYPTO_DEV_XILINX_RSA=y
CONFIG_CRYPTO_DEV_ZYNQMP_AES=y
# CONFIG_CRYPTO_DEV_VIRTIO is not set
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking
#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
# CONFIG_PACKING is not set
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
# CONFIG_CORDIC is not set
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
# CONFIG_INDIRECT_PIO is not set
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC64 is not set
# CONFIG_CRC4 is not set
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set
#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_STACKWALK=y
CONFIG_SBITMAP=y
# end of Library routines
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
#
# Kernel hacking
#
#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DYNAMIC_DEBUG_CORE is not set
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options
#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
# CONFIG_DEBUG_INFO_COMPRESSED is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
# CONFIG_DEBUG_INFO_BTF is not set
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=2048
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
# CONFIG_HEADERS_INSTALL is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options
#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
# end of Generic Kernel Debugging Instruments
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y
#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging
# CONFIG_DEBUG_SHIRQ is not set
#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs
#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging
# CONFIG_DEBUG_TIMEKEEPING is not set
#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)
# CONFIG_DEBUG_IRQFLAGS is not set
# CONFIG_STACKTRACE is not set
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Debug kernel data structures
# CONFIG_DEBUG_CREDENTIALS is not set
#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_TRACE=y
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging
# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_SAMPLES is not set
CONFIG_STRICT_DEVMEM=y
# CONFIG_IO_STRICT_DEVMEM is not set
#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_DEBUG_EFI is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging
#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_STRING_SELFTEST is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_SCANF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_ARCH_USE_MEMTEST=y
# CONFIG_MEMTEST is not set
# end of Kernel Testing and Coverage
# end of Kernel hacking
================================================
FILE: kernel_boot/kernel_patch_readme.md
================================================
axi_hdmi_crtc.patch to avoid axi hdmi compiling error after enable Xilinx axi dma.
ad9361.patch to expose some APIs for openwifi driver and add one register write for AGC setting.
ad9361_private.patch to add bool for missing AGC setting.
ad9361_conv.patch to avoid 61.44Msps lvds interface self timing calibration for some low-end/bad hardware (sometimes difficult).
================================================
FILE: openwifi-arch.jpg.license
================================================
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
================================================
FILE: user_space/agc_settings.sh
================================================
#!/bin/bash
if [ "$#" -ne 1 ]; then
echo "You must enter 1 to apply new settings or 0 to restore default settings"
exit 1
fi
set -x
if test -f "/sys/kernel/debug/iio/iio:device0/direct_reg_access"; then
cd /sys/kernel/debug/iio/iio:device0/
else if test -f "/sys/kernel/debug/iio/iio:device1/direct_reg_access"; then
cd /sys/kernel/debug/iio/iio:device1/
else if test -f "/sys/kernel/debug/iio/iio:device2/direct_reg_access"; then
cd /sys/kernel/debug/iio/iio:device2/
else if test -f "/sys/kernel/debug/iio/iio:device3/direct_reg_access"; then
cd /sys/kernel/debug/iio/iio:device3/
else if test -f "/sys/kernel/debug/iio/iio:device4/direct_reg_access"; then
cd /sys/kernel/debug/iio/iio:device4/
else
echo "Can not find direct_reg_access!"
echo "Check log to make sure ad9361 driver is loaded!"
exit 1
fi
fi
fi
fi
fi
set +x
if [ $1 == "0" ]; then
echo 0x15C 0x72 > direct_reg_access
echo 0x106 0x72 > direct_reg_access
echo 0x103 0x08 > direct_reg_access
echo 0x101 0x0A > direct_reg_access
echo 0x110 0x40 > direct_reg_access
echo 0x115 0x00 > direct_reg_access
echo 0x10A 0x58 > direct_reg_access
echo "Applied default AGC settings"
elif [ $1 == "1" ]; then
echo 0x15C 0x70 > direct_reg_access
echo 0x106 0x77 > direct_reg_access
echo 0x103 0x1C > direct_reg_access
echo 0x101 0x0C > direct_reg_access
echo 0x110 0x48 > direct_reg_access
# DO NOT change 0x48 to 0x4A! Otherwise: did not acknowledge authentication response
echo 0x114 0xb0 > direct_reg_access
# 0x30 is the original value for register 0x114
echo 0x115 0x80 > direct_reg_access
echo 0x10A 0x18 > direct_reg_access
echo "Applied optimized AGC settings"
fi
# #Due to https://github.ugent.be/xjiao/openwifi/issues/148
echo 0x0fa 0x5 > direct_reg_access
echo 0x0fa 0xE5 > direct_reg_access
================================================
FILE: user_space/arbitrary_iq_gen/iq_single_carrier_1000000Hz_512.txt
================================================
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-15036,-6507
================================================
FILE: user_space/arbitrary_iq_gen/single_carrier_gen.m
================================================
% Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com)
% SPDX-FileCopyrightText: 2023 UGent
% SPDX-License-Identifier: AGPL-3.0-or-later
function single_carrier_gen(carrier_freq, num_iq)
if exist('carrier_freq', 'var')==0 || isempty(carrier_freq)
carrier_freq = 1e6;
end
if exist('num_iq', 'var')==0 || isempty(num_iq)
num_iq = 512;
end
sampling_rate = 20e6;
sampling_time = 1/sampling_rate;
t = (0.3+(0:(num_iq-1))).*sampling_time;
s = exp(2.*pi.*carrier_freq.*t.*1i);
%let's use 14 bits
real_part = round(real(s).*(2^14));
imag_part = round(imag(s).*(2^14));
filename = ['iq_single_carrier_' num2str(carrier_freq) 'Hz_' num2str(num_iq) '.txt'];
fid = fopen(filename,'w');
if fid == -1
disp('fopen failed');
return;
end
len = length(s);
for j=1:len
fprintf(fid, '%d,%d\n', real_part(j), imag_part(j));
end
fclose(fid);
disp(['Saved to ' filename]);
filename = ['iq_single_carrier_' num2str(carrier_freq) 'Hz_' num2str(num_iq) '.bin'];
fid = fopen(filename,'w');
if fid == -1
disp('fopen error');
return;
end
iq_int16 = [real_part; imag_part];
iq_int16 = iq_int16(:);
fwrite(fid, iq_int16, 'int16');
fclose(fid);
disp(['Saved to ' filename]);
================================================
FILE: user_space/boot_bin_gen.sh
================================================
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -ne 3 ]; then
echo "You must enter exactly 3 arguments: \$XILINX_DIR \$BOARD_NAME DIR_TO_filename.xsa"
exit 1
fi
XILINX_DIR=$1
BOARD_NAME=$2
XSA_FILE=$3
OPENWIFI_DIR=$(pwd)/../
echo OPENWIFI_DIR $OPENWIFI_DIR
echo XSA_FILE $XSA_FILE
if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
echo "$OPENWIFI_DIR is found!"
else
echo "$OPENWIFI_DIR is not correct. Please check!"
exit 1
fi
XILINX_ENV_FILE=$XILINX_DIR/Vitis/2022.2/settings64.sh
echo "Expect env file $XILINX_ENV_FILE"
if [ -f "$XILINX_ENV_FILE" ]; then
echo "$XILINX_ENV_FILE is found!"
else
echo "$XILINX_ENV_FILE is not correct. Please check!"
exit 1
fi
# if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then
# echo "$BOARD_NAME is not correct. Please check!"
# exit 1
# else
# echo "$BOARD_NAME is found!"
# fi
if [ -f "$XSA_FILE" ]; then
echo "$XSA_FILE is found!"
else
echo "$XSA_FILE is not found. Please check!"
exit 1
fi
home_dir=$(pwd)
set -ex
source $XILINX_ENV_FILE
cd $OPENWIFI_DIR/kernel_boot
if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then
./build_zynqmp_boot_bin.sh $XSA_FILE boards/$BOARD_NAME/u-boot_xilinx_zynqmp_zcu102_revA.elf boards/$BOARD_NAME/bl31.elf
ARCH="zynqmp"
ARCH_BIT=64
elif [ "$BOARD_NAME" == "antsdr" ] || [ "$BOARD_NAME" == "antsdr_e200" ] || [ "$BOARD_NAME" == "e310v2" ] || [ "$BOARD_NAME" == "sdrpi" ] || [ "$BOARD_NAME" == "neptunesdr" ] || [ "$BOARD_NAME" == "zc706_fmcs2" ] || [ "$BOARD_NAME" == "zc702_fmcs2" ] || [ "$BOARD_NAME" == "zed_fmcs2" ] || [ "$BOARD_NAME" == "adrv9361z7035" ] || [ "$BOARD_NAME" == "adrv9364z7020" ]; then
./build_boot_bin.sh $XSA_FILE boards/$BOARD_NAME/u-boot.elf
ARCH="zynq"
ARCH_BIT=32
else
echo "$BOARD_NAME is not correct. Please check!"
cd $home_dir
exit 1
fi
rm -rf build_boot_bin
rm -rf boards/$BOARD_NAME/output_boot_bin
mv output_boot_bin boards/$BOARD_NAME/
cd $home_dir
### Get basename of xsa and bit file
XSA_FILE_BASENAME="$(basename $XSA_FILE)"
XSA_FILE_BASENAME_WO_EXT="$(basename $XSA_FILE .xsa)"
BIT_FILE_BASENAME="$XSA_FILE_BASENAME_WO_EXT.bit"
# generate $BIT_FILE_BASENAME.bin for FPGA dynamic loading
echo "all:" > ./fpga_bit_to_bin.bif
echo "{" >> ./fpga_bit_to_bin.bif
echo "$BIT_FILE_BASENAME /* Bitstream file name */" >> ./fpga_bit_to_bin.bif
echo "}" >> ./fpga_bit_to_bin.bif
unzip -o $XSA_FILE
rm -rf ./$BIT_FILE_BASENAME.bin
bootgen -image fpga_bit_to_bin.bif -arch $ARCH -process_bitstream bin -w
ls ./$BIT_FILE_BASENAME.bin -al
================================================
FILE: user_space/build_wpa_supplicant_wo11b.sh
================================================
#!/bin/bash
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
# if [ "$#" -ne 1 ]; then
# echo "You must enter exactly 1 arguments: \$OPENWIFI_DIR"
# exit 1
# fi
OPENWIFI_DIR=$(pwd)/../
set -x
cd $OPENWIFI_DIR/user_space
wget http://w1.fi/releases/wpa_supplicant-2.1.tar.gz
tar xzvf wpa_supplicant-2.1.tar.gz
patch -d wpa_supplicant-2.1/src/drivers/ < driver_nl80211.patch
cd wpa_supplicant-2.1/wpa_supplicant/
cp defconfig .config
sed -i 's/#CONFIG_LIBNL32.*/CONFIG_LIBNL32=y/g' .config
make -j16
# sudo make install
cd ../../
rm -r wpa_supplicant-2.1/ wpa_supplicant-2.1.tar.gz
================================================
FILE: user_space/cd_adi_iio_dir.sh
================================================
#!/bin/sh
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2022 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
set -x
if test -f "/sys/bus/iio/devices/iio:device0/in_voltage_rf_bandwidth"; then
cd /sys/bus/iio/devices/iio:device0/
else if test -f "/sys/bus/iio/devices/iio:device1/in_voltage_rf_bandwidth"; then
cd /sys/bus/iio/devices/iio:device1/
else if test -f "/sys/bus/iio/devices/iio:device2/in_voltage_rf_bandwidth"; then
cd /sys/bus/iio/devices/iio:device2/
else if test -f "/sys/bus/iio/devices/iio:device3/in_voltage_rf_bandwidth"; then
cd /sys/bus/iio/devices/iio:device3/
else if test -f "/sys/bus/iio/devices/iio:device4/in_voltage_rf_bandwidth"; then
cd /sys/bus/iio/devices/iio:device4/
else
echo "Can not find in_voltage_rf_bandwidth!"
echo "Check log to make sure ad9361 driver is loaded!"
exit 1
fi
fi
fi
fi
fi
set +x
================================================
FILE: user_space/check_calib_inf.sh
================================================
#!/bin/bash
set -x
if test -f "/sys/kernel/debug/iio/iio:device0/direct_reg_access"; then
device_path=/sys/kernel/debug/iio/iio:device0/
else if test -f "/sys/kernel/debug/iio/iio:device1/direct_reg_access"; then
device_path=/sys/kernel/debug/iio/iio:device1/
else if test -f "/sys/kernel/debug/iio/iio:device2/direct_reg_access"; then
device_path=/sys/kernel/debug/iio/iio:device2/
else if test -f "/sys/kernel/debug/iio/iio:device3/direct_reg_access"; then
device_path=/sys/kernel/debug/iio/iio:device3/
else if test -f "/sys/kernel/debug/iio/iio:device4/direct_reg_access"; then
device_path=/sys/kernel/debug/iio/iio:device4/
else
echo "Check log to make sure ad9361 driver is loaded!"
exit 1
fi
fi
fi
fi
fi
set +x
(bash -c 'echo $PPID' > /tmp/check_calib_inf.pid
while true; do
echo 0x0A7 > ${device_path}direct_reg_access
status=$( cat ${device_path}direct_reg_access )
if [ $status == "0xFF" ]; then
echo "WARNING: Tx Quadrature Calibration failed."
fi
sleep 5
done) &
================================================
FILE: user_space/csi_fuzzer.sh
================================================
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2021 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -lt 4 ]; then
echo "You must enter 4 arguments: c1_rot90_en c1_raw(-64 to 63) c2_rot90_en c2_raw(-64 to 63)"
exit 1
fi
c1_rot90_en=$1
c1_raw=$2
c2_rot90_en=$3
c2_raw=$4
if (($c1_rot90_en != 0)) && (($c1_rot90_en != 1)); then
echo "c1_rot90_en must be 0 or 1!"
exit 1
fi
if (($c1_raw < -64)) || (($c1_raw > 63)); then
echo "c1_raw must be -64 to 63!"
exit 1
fi
if (($c2_rot90_en != 0)) && (($c2_rot90_en != 1)); then
echo "c2_rot90_en must be 0 or 1!"
exit 1
fi
if (($c2_raw < -64)) || (($c2_raw > 63)); then
echo "c2_raw must be -64 to 63!"
exit 1
fi
if (($c1_raw < 0)); then
unsigned_c1=$(expr 128 + $c1_raw)
# echo $unsigned_c1
else
unsigned_c1=$c1_raw
fi
if (($c2_raw < 0)); then
unsigned_c2=$(expr 128 + $c2_raw)
# echo $unsigned_c2
else
unsigned_c2=$c2_raw
fi
# echo $c1_rot90_en
# echo $unsigned_c1
# echo $c2_rot90_en
# echo $unsigned_c2
unsigned_dec_combined=$(($unsigned_c1 + 512 * $c1_rot90_en + 1024 * $unsigned_c2 + 524288 * $c2_rot90_en))
# echo $unsigned_dec_combined
echo "./sdrctl dev sdr0 set reg tx_intf 5 $unsigned_dec_combined"
./sdrctl dev sdr0 set reg tx_intf 5 $unsigned_dec_combined
================================================
FILE: user_space/csi_fuzzer_scan.sh
================================================
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2021 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -lt 1 ]; then
echo "You must enter 1 arguments: 1, 2, 3 or 4. For scan c1, c2, c2&c1 or c1&c2,"
exit 1
fi
SCAN_OPTION=$1
if (($SCAN_OPTION == 1)); then
echo "Scan tap1:"
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 $i 0 0
sleep 0.01
done
for i in {-64..63};
do
./csi_fuzzer.sh 1 $i 0 0
sleep 0.01
done
done
exit 1
fi
if (($SCAN_OPTION == 2)); then
echo "Scan tap2:"
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 0 0 $i
sleep 0.01
done
for i in {-64..63};
do
./csi_fuzzer.sh 0 0 1 $i
sleep 0.01
done
done
exit 1
fi
if (($SCAN_OPTION == 3)); then
echo "Scan tap1 after tap2:"
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 $j 0 $i
# sleep 0.1
done
for i in {-64..63};
do
./csi_fuzzer.sh 0 $j 1 $i
# sleep 0.1
done
done
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 1 $j 0 $i
# sleep 0.1
done
for i in {-64..63};
do
./csi_fuzzer.sh 1 $j 1 $i
# sleep 0.1
done
done
exit 1
fi
if (($SCAN_OPTION == 4)); then
echo "Scan tap2 after tap1:"
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 $i 0 $j
# sleep 0.1
done
for i in {-64..63};
do
./csi_fuzzer.sh 1 $i 0 $j
# sleep 0.1
done
done
for j in {-64..63};
do
for i in {-64..63};
do
./csi_fuzzer.sh 0 $i 1 $j
# sleep 0.1
done
for i in {-64..63};
do
./csi_fuzzer.sh 1 $i 1 $j
# sleep 0.1
done
done
exit 1
fi
================================================
FILE: user_space/cw_disable.sh
================================================
#!/bin/bash
home_dir=$(pwd)
if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then
cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr
else
cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr
fi
set -x
#set
if [[ -n $1 ]]; then
echo "3$1" > csma_cfg0
fi
# show
cat csma_cfg0
set +x
cd $home_dir
================================================
FILE: user_space/cw_max_min_cfg.sh
================================================
#!/bin/bash
home_dir=$(pwd)
if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then
cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr
else
cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr
fi
set -x
#set
if [[ -n $1 ]]; then
echo "$1" > cw_max_min_cfg
fi
# show
cat cw_max_min_cfg
set +x
cd $home_dir
================================================
FILE: user_space/dhcpd.conf
================================================
#
# Sample configuration file for ISC dhcpd for Debian
#
# Attention: If /etc/ltsp/dhcpd.conf exists, that will be used as
# configuration file instead of this file.
#
#
# The ddns-updates-style parameter controls whether or not the server will
# attempt to do a DNS update when a lease is confirmed. We default to the
# behavior of the version 2 packages ('none', since DHCP v2 didn't
# have support for DDNS.)
ddns-update-style none;
# option definitions common to all supported networks...
# option domain-name "orca-project.eu";
#option domain-name-servers ns1.example.org, ns2.example.org;
default-lease-time 600;
max-lease-time 7200;
# If this DHCP server is the official DHCP server for the local
# network, the authoritative directive should be uncommented.
#authoritative;
# Use this to send dhcp log messages to a different log file (you also
# have to hack syslog.conf to complete the redirection).
log-facility local7;
# No service will be given on this subnet, but declaring it helps the
# DHCP server to understand the network topology.
option subnet-mask 255.255.255.0;
option broadcast-address 192.168.13.255;
option routers 192.168.13.1;
option domain-name-servers 8.8.8.8, 4.4.4.4;
option domain-name "mydomain.example";
subnet 192.168.13.0 netmask 255.255.255.0 {
# default-lease-time 6000;
# max-lease-time 7200;
option routers 192.168.13.1;
range 192.168.13.2 192.168.13.254;
}
#subnet 10.152.187.0 netmask 255.255.255.0 {
#}
# This is a very basic subnet declaration.
#subnet 10.254.239.0 netmask 255.255.255.224 {
# range 10.254.239.10 10.254.239.20;
# option routers rtr-239-0-1.example.org, rtr-239-0-2.example.org;
#}
# This declaration allows BOOTP clients to get dynamic addresses,
# which we don't really recommend.
#subnet 10.254.239.32 netmask 255.255.255.224 {
# range dynamic-bootp 10.254.239.40 10.254.239.60;
# option broadcast-address 10.254.239.31;
# option routers rtr-239-32-1.example.org;
#}
# A slightly different configuration for an internal subnet.
#subnet 10.5.5.0 netmask 255.255.255.224 {
# range 10.5.5.26 10.5.5.30;
# option domain-name-servers ns1.internal.example.org;
# option domain-name "internal.example.org";
# option routers 10.5.5.1;
# option broadcast-address 10.5.5.31;
# default-lease-time 600;
# max-lease-time 7200;
#}
# Hosts which require special configuration options can be listed in
# host statements. If no address is specified, the address will be
# allocated dynamically (if possible), but the host-specific information
# will still come from the host declaration.
#host passacaglia {
# hardware ethernet 0:0:c0:5d:bd:95;
# filename "vmunix.passacaglia";
# server-name "toccata.fugue.com";
#}
# Fixed IP addresses can also be specified for hosts. These addresses
# should not also be listed as being available for dynamic assignment.
# Hosts for which fixed IP addresses have been specified can boot using
# BOOTP or DHCP. Hosts for which no fixed address is specified can only
# be booted with DHCP, unless there is an address range on the subnet
# to which a BOOTP client is connected which has the dynamic-bootp flag
# set.
#host fantasia {
# hardware ethernet 08:00:07:26:c0:a5;
# fixed-address fantasia.fugue.com;
#}
# You can declare a class of clients and then do address allocation
# based on that. The example below shows a case where all clients
# in a certain class get addresses on the 10.17.224/24 subnet, and all
# other clients get addresses on the 10.0.29/24 subnet.
#class "foo" {
# match if substring (option vendor-class-identifier, 0, 4) = "SUNW";
#}
#shared-network 224-29 {
# subnet 10.17.224.0 netmask 255.255.255.0 {
# option routers rtr-224.example.org;
# }
# subnet 10.0.29.0 netmask 255.255.255.0 {
# option routers rtr-29.example.org;
# }
# pool {
# allow members of "foo";
# range 10.17.224.10 10.17.224.250;
# }
# pool {
# deny members of "foo";
# range 10.0.29.10 10.0.29.230;
# }
#}
================================================
FILE: user_space/difs_disable.sh
================================================
#!/bin/bash
home_dir=$(pwd)
if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then
cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr
else
cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr
fi
set -x
#set
if [[ -n $1 ]]; then
echo "1$1" > csma_cfg0
fi
# show
cat csma_cfg0
set +x
cd $home_dir
================================================
FILE: user_space/driver_nl80211.patch
================================================
--- wpa_supplicant-2.1/src/drivers/driver_nl80211.c 2014-02-04 12:23:35.000000000 +0100
+++ driver_nl80211.c 2020-01-09 09:11:35.943884000 +0100
@@ -5903,6 +5903,8 @@
wpa_driver_nl80211_set_mode(bss, nlmode) < 0)
return -1;
+ nl80211_disable_11b_rates(drv, drv->ifindex, 1);
+
retry:
msg = nlmsg_alloc();
if (!msg)
@@ -8625,6 +8627,7 @@
}
nl80211_mark_disconnected(drv);
+ nl80211_disable_11b_rates(drv, drv->ifindex, 1);
msg = nlmsg_alloc();
if (!msg)
================================================
FILE: user_space/drv_and_fpga_package_gen.sh
================================================
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2022 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
if [ "$#" -lt 3 ]; then
echo "You have input $# arguments."
echo "You must enter at least the first three 3 arguments: \$OPENWIFI_HW_IMG_DIR \$XILINX_DIR \$BOARD_NAME file_postfix"
exit 1
fi
OPENWIFI_HW_IMG_DIR=$1
XILINX_DIR=$2
BOARD_NAME=$3
XILINX_ENV_FILE=$XILINX_DIR/Vitis/2022.2/settings64.sh
echo "Expect env file $XILINX_ENV_FILE"
if [ -f "$XILINX_ENV_FILE" ]; then
echo "$XILINX_ENV_FILE is found!"
else
echo "$XILINX_ENV_FILE is not correct. Please check!"
exit 1
fi
if [ "$BOARD_NAME" != "neptunesdr" ] && [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "e310v2" ] && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
echo "$BOARD_NAME is not correct. Please check!"
exit 1
else
echo "$BOARD_NAME is found!"
fi
if [ -d "$OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME" ]; then
echo "$OPENWIFI_HW_IMG_DIR is found!"
else
echo "$OPENWIFI_HW_IMG_DIR is not correct. Please check!"
exit 1
fi
# uncompress the system.hdf and system_top.bit for use
mkdir -p hdf_and_bit
rm hdf_and_bit/* -rf
unzip $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top.xsa -d ./hdf_and_bit
# cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf
# cp ./hdf_and_bit/system_top.bit $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf
# BIT_FILENAME=$OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit
BIT_FILENAME=./hdf_and_bit/system_top.bit
if [ -f "$BIT_FILENAME" ]; then
echo "$BIT_FILENAME is found!"
else
echo "$BIT_FILENAME does NOT exist. Please check!"
exit 1
fi
if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then
ARCH="zynqmp"
ARCH_BIT=64
else
ARCH="zynq"
ARCH_BIT=32
fi
# FINAL_BIT_FILENAME=$BOARD_NAME\_system_top_reload.bit.bin
set -x
source $XILINX_ENV_FILE
cp $BIT_FILENAME ./
bootgen -image system_top.bif -arch $ARCH -process_bitstream bin -w
# cp system_top_reload.bit.bin ./$FINAL_BIT_FILENAME
cd ../driver
make clean
./make_all.sh $XILINX_DIR $ARCH_BIT
cd ../user_space
mkdir -p drv_and_fpga
rm -rf drv_and_fpga/*
cp system_top.bit.bin ../driver/side_ch/side_ch.ko ../driver/tx_intf/tx_intf.ko ../driver/rx_intf/rx_intf.ko ../driver/openofdm_tx/openofdm_tx.ko ../driver/openofdm_rx/openofdm_rx.ko ../driver/xpu/xpu.ko ../driver/sdr.ko ./drv_and_fpga -f
cp $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/git_info.txt ./drv_and_fpga -f
# Add driver git info
echo " " >> ./drv_and_fpga//git_info.txt
echo "openwifi-git-branch" >> ./drv_and_fpga//git_info.txt
git branch >> ./drv_and_fpga//git_info.txt
echo " " >> ./drv_and_fpga//git_info.txt
echo "openwifi-git-commit" >> ./drv_and_fpga//git_info.txt
git log -3 >> ./drv_and_fpga//git_info.txt
echo " " >> ./drv_and_fpga//git_info.txt
tar -cvf ./drv_and_fpga/driver.tar $(git ls-files ../driver/)
# dir_save=$(pwd)
# cd $OPENWIFI_HW_DIR/ip/
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-root.tar $(git ls-files ./ | grep -v -E "/|openofdm_rx")
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-xpu.tar $(git ls-files ./xpu)
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-tx_intf.tar $(git ls-files ./tx_intf)
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-rx_intf.tar $(git ls-files ./rx_intf)
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-openofdm_tx.tar $(git ls-files ./openofdm_tx)
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-side_ch.tar $(git ls-files ./side_ch)
# cd ../boards
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-root.tar $(git ls-files ./ | grep -v "/")
# cd ./$BOARD_NAME
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-root.tar $(git ls-files ./ | grep -v "/")
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-src.tar $(git ls-files ./src)
# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-ip_repo.tar ip_repo
# cd $dir_save
# # tar -cvf drv_and_fpga.tar system_top.bit.bin tx_intf.ko rx_intf.ko openofdm_tx.ko openofdm_rx.ko xpu.ko sdr.ko git_info.txt
if [ "$#" == 4 ]; then
POSTFIX="_${4}"
else
POSTFIX=""
fi
tar -zcvf drv_and_fpga$POSTFIX.tar.gz drv_and_fpga
set +x
================================================
FILE: user_space/eifs_by_last_rx_fail_disable.sh
================================================
#!/bin/bash
home_dir=$(pwd)
if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then
cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr
else
cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr
fi
set -x
#set
if [[ -n $1 ]]; then
echo "4$1" > csma_cfg0
fi
# show
cat csma_cfg0
set +x
cd $home_dir
================================================
FILE: user_space/eifs_by_last_tx_fail_disable.sh
================================================
#!/bin/bash
home_dir=$(pwd)
if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then
cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr
else
cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr
fi
set -x
#set
if [[ -n $1 ]]; then
echo "5$1" > csma_cfg0
fi
# show
cat csma_cfg0
set +x
cd $home_dir
================================================
FILE: user_space/eifs_disable.sh
================================================
#!/bin/bash
home_dir=$(pwd)
if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then
cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr
else
cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr
fi
set -x
#set
if [[ -n $1 ]]; then
echo "2$1" > csma_cfg0
fi
# show
cat csma_cfg0
set +x
cd $home_dir
================================================
FILE: user_space/fast_reg_log/fast_reg_log.c
================================================
// Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com)
// SPDX-FileCopyrightText: 2023 UGent
// SPDX-License-Identifier: AGPL-3.0-or-later
// Use this example together with fast_reg_log_analyzer.m (notter release)
#include
#include
#include
#include
#include
#include
#include
int main()
{
unsigned int bram_size = 0x10000; // 64KB, aligned with openwifi hw .bd and devicetree
off_t bram_pbase = 0x83c40000; // physical base address, aligned with openwifi hw .bd and devicetree (this example: xpu @ 32bit boards)
uint32_t *bram32_vptr;
int fd, i, j;
uint32_t tsf_reg[524288*2];
FILE *fp;
// Map the BRAM physical address into user space getting a virtual address for it
if ((fd = open("/dev/mem", O_RDONLY | O_SYNC)) != -1) {
bram32_vptr = (uint32_t *)mmap(NULL, bram_size, PROT_READ, MAP_SHARED, fd, bram_pbase);
fp = fopen ("fast_reg_log.bin", "wb");
if (fp == NULL) {
printf("fopen fast_reg_log.bin failed! %d\n", (int)fp);
close(fd);
return(0);
}
for (j=0; j<10; j++) {
for (i=0; i<(524288*2); i=i+2) {
tsf_reg[i+0] = (*(bram32_vptr+57)); // read xpu register 57: rssi trx agc cca status
tsf_reg[i+1] = (*(bram32_vptr+58)); // read xpu register 58: low 32bit of tsf
}
// for (i=0; i<1024; i++) {
// printf("%d %x\n", tsf[i], reg[i]);
// }
// memcpy(buf, bram64_vptr, bram_size);
fwrite(tsf_reg, sizeof(uint32_t), 524288*2, fp);
}
fclose(fp);
// printf("%016llx\n", buf[65532]);
// printf("%016llx\n", buf[65533]);
// printf("%016llx\n", buf[65534]);
// printf("%016llx\n", buf[65535]);
// //for(i=0; i<32; i++) {
// // printf("0x%02x\n", buf[i]);
// //}
close(fd);
}
return(0);
}
================================================
FILE: user_space/fast_reg_log/fast_reg_log_analyzer.m
================================================
% Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com)
% SPDX-FileCopyrightText: 2023 UGent
% SPDX-License-Identifier: AGPL-3.0-or-later
function fast_reg_log_analyzer(filename_bin, start_idx, end_idx)
close all;
% if exist('start_idx', 'var')==0 || isempty(start_idx)
% start_idx = 1;
% end
%
% if exist('end_idx', 'var')==0 || isempty(end_idx)
% end_idx = 65536;
% end
filename_csv = [filename_bin(1:(end-3)) 'csv'];
disp(['Human readable fast reg log will be in ' filename_csv]);
fid = fopen(filename_bin);
if fid == -1
disp('fopen failed!');
return;
end
a = fread(fid, inf, 'uint32');
fclose(fid);
% a = bitand(uint32(a), uint32(268435455));
% plot(a(1:2:end)); hold on;
% plot(a(2:2:end));
% legend('1', '2');
a = uint32(a);
tsf = a(2:2:end);
% plot(tsf);
state = a(1:2:end);
% find out overflow idx
overflow_idx = find(diff([0; double(tsf)])<0, 1, 'first');
% overflow_idx
if ~isempty(overflow_idx)
tsf(overflow_idx:end) = tsf(overflow_idx:end) + (2^32);
disp(num2str(overflow_idx));
end
rssi_correction = 145;
rssi_half_db = double(bitand(bitshift(state, 0), uint32((2^11)-1)));
agc_lock = 1 - double(bitand(bitshift(state, -11), uint32(1)));
demod_is_ongoing = double(bitand(bitshift(state, -12), uint32(1)));
tx_is_ongoing = double(bitand(bitshift(state, -13), uint32(1)));
ch_idle = 1 - double(bitand(bitshift(state, -14), uint32(1)));
iq_rssi_half_db = double(bitand(bitshift(state, -16), uint32((2^9)-1)));
agc_gain = double(bitand(bitshift(state, -25), uint32((2^7)-1)));
rssi_dbm = (rssi_half_db./2) - rssi_correction;
figure;
subplot(2,1,1);
plot(tsf, -rssi_dbm, 'r+-'); hold on;
plot(tsf, iq_rssi_half_db, 'bo-');
plot(tsf, agc_gain, 'ks-');
legend('rssi dbm', 'iq rssi half db', 'agc gain');
subplot(2,1,2);
plot(tsf, agc_lock+0); hold on;
plot(tsf, demod_is_ongoing+2);
plot(tsf, tx_is_ongoing+4);
plot(tsf, ch_idle+6);
legend('agc lock', 'demod is ongoing', 'tx is ongoing', 'ch idle');
a=table(tsf, rssi_half_db, rssi_dbm, iq_rssi_half_db, agc_gain, agc_lock, demod_is_ongoing, tx_is_ongoing, ch_idle);
writetable(a, filename_csv);
================================================
FILE: user_space/fosdem-11ag.sh
================================================
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
# test_mode=$1
# if [ -z $test_mode ]
# then
# test_mode=0
# fi
# echo test_mode $test_mode
killall hostapd
killall webfsd
cd ~/openwifi
# service network-manager stop
# ./wgd.sh $test_mode
ifconfig sdr0 192.168.13.1
rm /var/run/dhcpd.pid
sleep 1
service isc-dhcp-server restart
hostapd hostapd-openwifi-11ag.conf &
sleep 5
cd webserver
webfsd -F -p 80 -f index.html &
route add default gw 192.168.10.1
cd ~/openwifi
./agc_settings.sh 1
================================================
FILE: user_space/fosdem.sh
================================================
#!/bin/bash
# Author: Xianjun Jiao
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
# test_mode=$1
# if [ -z $test_mode ]
# then
# test_mode=0
# fi
# echo test_mode $test_mode
killall hostapd
killall webfsd
cd ~/openwifi
# service network-manager stop
# ./wgd.sh $test_mode
ifconfig sdr0 192.168.13.1
rm /var/run/dhcpd.pid
sleep 1
service isc-dhcp-server restart
hostapd hostapd-openwifi.conf &
sleep 5
cd webserver
webfsd -F -p 80 -f index.html &
route add default gw 192.168.10.1
cd ~/openwifi
./agc_settings.sh 1
================================================
FILE: user_space/hostapd-openwifi-11ag.conf
================================================
interface=sdr0
driver=nl80211
country_code=BE
ssid=openwifi
hw_mode=a
channel=36
supported_rates=60 90 120 180 240 360 480 540
basic_rates=60 90 120 180
#ieee80211n=1
#ht_capab=[SHORT-GI-20]
#require_ht=1
#ieee80211d=1
#ieee80211h=1
#wpa=1
#wpa_passphrase=openwifi
#wpa_key_mgmt=WPA-PSK
#wpa_pairwise=TKIP CCMP
#wpa_ptk_rekey=600
================================================
FILE: user_space/hostapd-openwifi.conf
================================================
interface=sdr0
driver=nl80211
country_code=BE
ssid=openwifi
hw_mode=a
channel=36
supported_rates=60 90 120 180 240 360 480 540
basic_rates=60 90 120 180
ieee80211n=1
#ht_capab=[SHORT-GI-20]
require_ht=1
#ieee80211d=1
#ieee80211h=1
#wpa=1
#wpa_passphrase=openwifi
#wpa_key_mgmt=WPA-PSK
#wpa_pairwise=TKIP CCMP
#wpa_ptk_rekey=600
================================================
FILE: user_space/inject_80211/Makefile
================================================
all: inject_80211 analyze_80211
inject_80211: inject_80211.c
# gcc -Wall -Werror inject_80211.c -o inject_80211 -lpcap
gcc -Wall inject_80211.c -o inject_80211 -lpcap
analyze_80211: analyze_80211.c
# gcc -Wall -Werror radiotap.c analyze_80211.c -o analyze_80211 -lpcap
gcc -Wall radiotap.c analyze_80211.c -o analyze_80211 -lpcap
clean:
rm -f inject_80211 analyze_80211
================================================
FILE: user_space/inject_80211/analyze_80211.c
================================================
// Author: Michael Mehari
// SPDX-FileCopyrightText: 2020 UGent
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include "inject_80211.h"
#include "radiotap.h"
#include "uthash.h"
#define HEADERLEN_80211 24
struct RECORD_t
{
char id[16]; // hw_mode-rate-sgi_flag-packet_size
uint16_t pkt_cnt; // number of packets received
uint64_t ts_begin; // beginning timestamp
uint64_t ts_end; // ending timestamp
UT_hash_handle hh; // hash function handler
};
/* 802.11n bitrates x 2 */
static const uint8_t rates_11n[] = {13, 26, 39, 52, 78, 104, 117, 130};
int main(int argc, char **argv)
{
struct pcap_pkthdr pcap_hdr;
const u_char *packet;
char hw_mode, id[16];
int rate, sgi_flag, packet_size;
int n, hdr_len;
struct ieee80211_radiotap_iterator rti;
struct RECORD_t *RECORD_ptr, *tmp_ptr, *hash_ptr = NULL;
if (argc < 2)
{
fprintf(stderr, "Usage: %s \n", argv[0]);
exit(1);
}
pcap_t *handle;
char errbuf[PCAP_ERRBUF_SIZE];
handle = pcap_open_offline(argv[1], errbuf);
if (handle == NULL)
{
fprintf(stderr,"Couldn't open pcap file %s: %s\n", argv[1], errbuf);
return(2);
}
while ((packet = pcap_next(handle, &pcap_hdr)))
{
hdr_len = (packet[2] + (packet[3] << 8));
if (pcap_hdr.len < (hdr_len + HEADERLEN_80211))
continue;
packet_size = pcap_hdr.len - (hdr_len + HEADERLEN_80211);
if (packet_size < 0)
continue;
if (ieee80211_radiotap_iterator_init(&rti, (struct ieee80211_radiotap_header *)packet, packet_size, NULL) < 0)
continue;
while ((n = ieee80211_radiotap_iterator_next(&rti)) == 0)
{
switch (rti.this_arg_index)
{
case IEEE80211_RADIOTAP_RATE:
rate = (rti.this_arg)[0];
sgi_flag = 0;
hw_mode = 'a';
break;
case IEEE80211_RADIOTAP_MCS:
rate = rates_11n[((rti.this_arg)[2])];
sgi_flag = (rti.this_arg)[1] & 0x40;
hw_mode = 'n';
break;
}
}
// create hash table index
sprintf(id, "%c-%d-%d-%d", hw_mode, rate, sgi_flag, packet_size);
// Hash table implementation for c : https://github.com/troydhanson/uthash
HASH_FIND_STR(hash_ptr, id, RECORD_ptr);
if(RECORD_ptr == NULL)
{
RECORD_ptr = (struct RECORD_t*)malloc(sizeof(struct RECORD_t));
if(RECORD_ptr == NULL)
{
fprintf(stderr, "Unable to create record!\n");
return 1;
}
strcpy(RECORD_ptr->id, id);
RECORD_ptr->pkt_cnt = 1;
RECORD_ptr->ts_begin = 1e6*pcap_hdr.ts.tv_sec + pcap_hdr.ts.tv_usec;
// Add the new record to the hash table
HASH_ADD_STR(hash_ptr, id, RECORD_ptr);
}
else
{
RECORD_ptr->pkt_cnt++;
RECORD_ptr->ts_end = 1e6*pcap_hdr.ts.tv_sec + pcap_hdr.ts.tv_usec;
}
}
pcap_close(handle);
// Iterate through the hash table
printf("HW MODE\tRATE(Mbps)\tSGI\tSIZE(bytes)\tCOUNT\tDELAY(sec)\n");
printf("=======\t==========\t===\t===========\t=====\t=========\n");
HASH_ITER(hh, hash_ptr, RECORD_ptr, tmp_ptr)
{
sscanf(RECORD_ptr->id, "%c-%d-%d-%d", &hw_mode, &rate, &sgi_flag, &packet_size);
printf("802.11%c\t%.1f\t\t%s\t%d\t\t%d\t%.5f\n", hw_mode, rate/2.0, (sgi_flag == 0 ? "OFF" : "ON"), packet_size, RECORD_ptr->pkt_cnt, 1e-6*(RECORD_ptr->ts_end - RECORD_ptr->ts_begin));
}
fflush(stdout);
return 0;
}
================================================
FILE: user_space/inject_80211/ieee80211_radiotap.h
================================================
/*
* Copyright (c) 2017 Intel Deutschland GmbH
* Copyright (c) 2018-2019 Intel Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __RADIOTAP_H
#define __RADIOTAP_H
#include
// #include
/**
* struct ieee82011_radiotap_header - base radiotap header
*/
struct ieee80211_radiotap_header {
/**
* @it_version: radiotap version, always 0
*/
uint8_t it_version;
/**
* @it_pad: padding (or alignment)
*/
uint8_t it_pad;
/**
* @it_len: overall radiotap header length
*/
__le16 it_len;
/**
* @it_present: (first) present word
*/
__le32 it_present;
} __attribute__((packed));
/* version is always 0 */
#define PKTHDR_RADIOTAP_VERSION 0
/* see the radiotap website for the descriptions */
enum ieee80211_radiotap_presence {
IEEE80211_RADIOTAP_TSFT = 0,
IEEE80211_RADIOTAP_FLAGS = 1,
IEEE80211_RADIOTAP_RATE = 2,
IEEE80211_RADIOTAP_CHANNEL = 3,
IEEE80211_RADIOTAP_FHSS = 4,
IEEE80211_RADIOTAP_DBM_ANTSIGNAL = 5,
IEEE80211_RADIOTAP_DBM_ANTNOISE = 6,
IEEE80211_RADIOTAP_LOCK_QUALITY = 7,
IEEE80211_RADIOTAP_TX_ATTENUATION = 8,
IEEE80211_RADIOTAP_DB_TX_ATTENUATION = 9,
IEEE80211_RADIOTAP_DBM_TX_POWER = 10,
IEEE80211_RADIOTAP_ANTENNA = 11,
IEEE80211_RADIOTAP_DB_ANTSIGNAL = 12,
IEEE80211_RADIOTAP_DB_ANTNOISE = 13,
IEEE80211_RADIOTAP_RX_FLAGS = 14,
IEEE80211_RADIOTAP_TX_FLAGS = 15,
IEEE80211_RADIOTAP_RTS_RETRIES = 16,
IEEE80211_RADIOTAP_DATA_RETRIES = 17,
/* 18 is XChannel, but it's not defined yet */
IEEE80211_RADIOTAP_MCS = 19,
IEEE80211_RADIOTAP_AMPDU_STATUS = 20,
IEEE80211_RADIOTAP_VHT = 21,
IEEE80211_RADIOTAP_TIMESTAMP = 22,
IEEE80211_RADIOTAP_HE = 23,
IEEE80211_RADIOTAP_HE_MU = 24,
IEEE80211_RADIOTAP_ZERO_LEN_PSDU = 26,
IEEE80211_RADIOTAP_LSIG = 27,
/* valid in every it_present bitmap, even vendor namespaces */
IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE = 29,
IEEE80211_RADIOTAP_VENDOR_NAMESPACE = 30,
IEEE80211_RADIOTAP_EXT = 31
};
/* for IEEE80211_RADIOTAP_FLAGS */
enum ieee80211_radiotap_flags {
IEEE80211_RADIOTAP_F_CFP = 0x01,
IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
IEEE80211_RADIOTAP_F_WEP = 0x04,
IEEE80211_RADIOTAP_F_FRAG = 0x08,
IEEE80211_RADIOTAP_F_FCS = 0x10,
IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
IEEE80211_RADIOTAP_F_BADFCS = 0x40,
};
/* for IEEE80211_RADIOTAP_CHANNEL */
enum ieee80211_radiotap_channel_flags {
IEEE80211_CHAN_CCK = 0x0020,
IEEE80211_CHAN_OFDM = 0x0040,
IEEE80211_CHAN_2GHZ = 0x0080,
IEEE80211_CHAN_5GHZ = 0x0100,
IEEE80211_CHAN_DYN = 0x0400,
IEEE80211_CHAN_HALF = 0x4000,
IEEE80211_CHAN_QUARTER = 0x8000,
};
/* for IEEE80211_RADIOTAP_RX_FLAGS */
enum ieee80211_radiotap_rx_flags {
IEEE80211_RADIOTAP_F_RX_BADPLCP = 0x0002,
};
/* for IEEE80211_RADIOTAP_TX_FLAGS */
enum ieee80211_radiotap_tx_flags {
IEEE80211_RADIOTAP_F_TX_FAIL = 0x0001,
IEEE80211_RADIOTAP_F_TX_CTS = 0x0002,
IEEE80211_RADIOTAP_F_TX_RTS = 0x0004,
IEEE80211_RADIOTAP_F_TX_NOACK = 0x0008,
IEEE80211_RADIOTAP_F_TX_NOSEQNO = 0x0010,
};
/* for IEEE80211_RADIOTAP_MCS "have" flags */
enum ieee80211_radiotap_mcs_have {
IEEE80211_RADIOTAP_MCS_HAVE_BW = 0x01,
IEEE80211_RADIOTAP_MCS_HAVE_MCS = 0x02,
IEEE80211_RADIOTAP_MCS_HAVE_GI = 0x04,
IEEE80211_RADIOTAP_MCS_HAVE_FMT = 0x08,
IEEE80211_RADIOTAP_MCS_HAVE_FEC = 0x10,
IEEE80211_RADIOTAP_MCS_HAVE_STBC = 0x20,
};
enum ieee80211_radiotap_mcs_flags {
IEEE80211_RADIOTAP_MCS_BW_MASK = 0x03,
IEEE80211_RADIOTAP_MCS_BW_20 = 0,
IEEE80211_RADIOTAP_MCS_BW_40 = 1,
IEEE80211_RADIOTAP_MCS_BW_20L = 2,
IEEE80211_RADIOTAP_MCS_BW_20U = 3,
IEEE80211_RADIOTAP_MCS_SGI = 0x04,
IEEE80211_RADIOTAP_MCS_FMT_GF = 0x08,
IEEE80211_RADIOTAP_MCS_FEC_LDPC = 0x10,
IEEE80211_RADIOTAP_MCS_STBC_MASK = 0x60,
IEEE80211_RADIOTAP_MCS_STBC_1 = 1,
IEEE80211_RADIOTAP_MCS_STBC_2 = 2,
IEEE80211_RADIOTAP_MCS_STBC_3 = 3,
IEEE80211_RADIOTAP_MCS_STBC_SHIFT = 5,
};
/* for IEEE80211_RADIOTAP_AMPDU_STATUS */
enum ieee80211_radiotap_ampdu_flags {
IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN = 0x0001,
IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN = 0x0002,
IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN = 0x0004,
IEEE80211_RADIOTAP_AMPDU_IS_LAST = 0x0008,
IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR = 0x0010,
IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN = 0x0020,
IEEE80211_RADIOTAP_AMPDU_EOF = 0x0040,
IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN = 0x0080,
};
/* for IEEE80211_RADIOTAP_VHT */
enum ieee80211_radiotap_vht_known {
IEEE80211_RADIOTAP_VHT_KNOWN_STBC = 0x0001,
IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA = 0x0002,
IEEE80211_RADIOTAP_VHT_KNOWN_GI = 0x0004,
IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS = 0x0008,
IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM = 0x0010,
IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED = 0x0020,
IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH = 0x0040,
IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID = 0x0080,
IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID = 0x0100,
};
enum ieee80211_radiotap_vht_flags {
IEEE80211_RADIOTAP_VHT_FLAG_STBC = 0x01,
IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA = 0x02,
IEEE80211_RADIOTAP_VHT_FLAG_SGI = 0x04,
IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9 = 0x08,
IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM = 0x10,
IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED = 0x20,
};
enum ieee80211_radiotap_vht_coding {
IEEE80211_RADIOTAP_CODING_LDPC_USER0 = 0x01,
IEEE80211_RADIOTAP_CODING_LDPC_USER1 = 0x02,
IEEE80211_RADIOTAP_CODING_LDPC_USER2 = 0x04,
IEEE80211_RADIOTAP_CODING_LDPC_USER3 = 0x08,
};
/* for IEEE80211_RADIOTAP_TIMESTAMP */
enum ieee80211_radiotap_timestamp_unit_spos {
IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MASK = 0x000F,
IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MS = 0x0000,
IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US = 0x0001,
IEEE80211_RADIOTAP_TIMESTAMP_UNIT_NS = 0x0003,
IEEE80211_RADIOTAP_TIMESTAMP_SPOS_MASK = 0x00F0,
IEEE80211_RADIOTAP_TIMESTAMP_SPOS_BEGIN_MDPU = 0x0000,
IEEE80211_RADIOTAP_TIMESTAMP_SPOS_PLCP_SIG_ACQ = 0x0010,
IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_PPDU = 0x0020,
IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_MPDU = 0x0030,
IEEE80211_RADIOTAP_TIMESTAMP_SPOS_UNKNOWN = 0x00F0,
};
enum ieee80211_radiotap_timestamp_flags {
IEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT = 0x00,
IEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT = 0x01,
IEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY = 0x02,
};
struct ieee80211_radiotap_he {
__le16 data1, data2, data3, data4, data5, data6;
};
enum ieee80211_radiotap_he_bits {
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK = 3,
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU = 0,
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU = 1,
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU = 2,
IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG = 3,
IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN = 0x0004,
IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN = 0x0008,
IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN = 0x0010,
IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN = 0x0020,
IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN = 0x0040,
IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN = 0x0080,
IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN = 0x0100,
IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN = 0x0200,
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN = 0x0400,
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN = 0x0800,
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN = 0x1000,
IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN = 0x2000,
IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN = 0x4000,
IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN = 0x8000,
IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN = 0x0001,
IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN = 0x0002,
IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN = 0x0004,
IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN = 0x0008,
IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN = 0x0010,
IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN = 0x0020,
IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN = 0x0040,
IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN = 0x0080,
IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET = 0x3f00,
IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN = 0x4000,
IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC = 0x8000,
IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR = 0x003f,
IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE = 0x0040,
IEEE80211_RADIOTAP_HE_DATA3_UL_DL = 0x0080,
IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS = 0x0f00,
IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM = 0x1000,
IEEE80211_RADIOTAP_HE_DATA3_CODING = 0x2000,
IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG = 0x4000,
IEEE80211_RADIOTAP_HE_DATA3_STBC = 0x8000,
IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE = 0x000f,
IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID = 0x7ff0,
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1 = 0x000f,
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2 = 0x00f0,
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3 = 0x0f00,
IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4 = 0xf000,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC = 0x000f,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ = 0,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ = 1,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ = 2,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ = 3,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T = 4,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T = 5,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T = 6,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T = 7,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T = 8,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T = 9,
IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T = 10,
IEEE80211_RADIOTAP_HE_DATA5_GI = 0x0030,
IEEE80211_RADIOTAP_HE_DATA5_GI_0_8 = 0,
IEEE80211_RADIOTAP_HE_DATA5_GI_1_6 = 1,
IEEE80211_RADIOTAP_HE_DATA5_GI_3_2 = 2,
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE = 0x00c0,
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN = 0,
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X = 1,
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X = 2,
IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X = 3,
IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS = 0x0700,
IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD = 0x3000,
IEEE80211_RADIOTAP_HE_DATA5_TXBF = 0x4000,
IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG = 0x8000,
IEEE80211_RADIOTAP_HE_DATA6_NSTS = 0x000f,
IEEE80211_RADIOTAP_HE_DATA6_DOPPLER = 0x0010,
IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_KNOWN = 0x0020,
IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW = 0x00c0,
IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_20MHZ = 0,
IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_40MHZ = 1,
IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_80MHZ = 2,
IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_160MHZ = 3,
IEEE80211_RADIOTAP_HE_DATA6_TXOP = 0x7f00,
IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY = 0x8000,
};
struct ieee80211_radiotap_he_mu {
__le16 flags1, flags2;
u8 ru_ch1[4];
u8 ru_ch2[4];
};
enum ieee80211_radiotap_he_mu_bits {
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS = 0x000f,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN = 0x0010,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM = 0x0020,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN = 0x0040,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_CTR_26T_RU_KNOWN = 0x0080,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN = 0x0100,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_RU_KNOWN = 0x0200,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN = 0x1000,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU = 0x2000,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN = 0x4000,
IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN = 0x8000,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW = 0x0003,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_20MHZ = 0x0000,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_40MHZ = 0x0001,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_80MHZ = 0x0002,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_160MHZ = 0x0003,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN = 0x0004,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP = 0x0008,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS = 0x00f0,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW = 0x0300,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN= 0x0400,
IEEE80211_RADIOTAP_HE_MU_FLAGS2_CH2_CTR_26T_RU = 0x0800,
};
enum ieee80211_radiotap_lsig_data1 {
IEEE80211_RADIOTAP_LSIG_DATA1_RATE_KNOWN = 0x0001,
IEEE80211_RADIOTAP_LSIG_DATA1_LENGTH_KNOWN = 0x0002,
};
enum ieee80211_radiotap_lsig_data2 {
IEEE80211_RADIOTAP_LSIG_DATA2_RATE = 0x000f,
IEEE80211_RADIOTAP_LSIG_DATA2_LENGTH = 0xfff0,
};
struct ieee80211_radiotap_lsig {
__le16 data1, data2;
};
enum ieee80211_radiotap_zero_len_psdu_type {
IEEE80211_RADIOTAP_ZERO_LEN_PSDU_SOUNDING = 0,
IEEE80211_RADIOTAP_ZERO_LEN_PSDU_NOT_CAPTURED = 1,
IEEE80211_RADIOTAP_ZERO_LEN_PSDU_VENDOR = 0xff,
};
// /**
// * ieee80211_get_radiotap_len - get radiotap header length
// */
// static inline u16 ieee80211_get_radiotap_len(const char *data)
// {
// struct ieee80211_radiotap_header *hdr = (void *)data;
// return get_unaligned_le16(&hdr->it_len);
// }
#endif /* __RADIOTAP_H */
================================================
FILE: user_space/inject_80211/inject_80211.c
================================================
// Modified by: Michael Mehari
// SPDX-FileCopyrightText: 2020 UGent
// SPDX-FileCopyrightText: 2007 Andy Green
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
// Thanks for contributions:
// 2007-03-15 fixes to getopt_long code by Matteo Croce rootkit85@yahoo.it
#include "inject_80211.h"
#include "ieee80211_radiotap.h"
#define BUF_SIZE_MAX (1536)
#define BUF_SIZE_TOTAL (BUF_SIZE_MAX+1) // +1 in case the sprintf insert the last 0
/* wifi bitrate to use in 500kHz units */
static const u8 u8aRatesToUse[] = {
6*2,
9*2,
12*2,
18*2,
24*2,
36*2,
48*2,
54*2
};
/* this is the template radiotap header we send packets out with */
static const u8 u8aRadiotapHeader[] =
{
0x00, 0x00, // <-- radiotap version
0x1c, 0x00, // <- radiotap header length
0x6f, 0x08, 0x08, 0x00, // <-- bitmap
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // <-- timestamp
0x00, // <-- flags (Offset +0x10)
0x6c, // <-- rate (0ffset +0x11)
0x71, 0x09, 0xc0, 0x00, // <-- channel
0xde, // <-- antsignal
0x00, // <-- antnoise
0x01, // <-- antenna
0x02, 0x00, 0x0f, // <-- MCS
};
#define OFFSET_RATE 0x11
#define MCS_OFFSET 0x19
#define GI_OFFSET 0x1a
#define MCS_RATE_OFFSET 0x1b
/* IEEE80211 header */
static u8 ieee_hdr_data[] =
{
0x08, 0x02, 0x00, 0x00, // FC 0x0802. 0--subtype; 8--type&version; 02--toDS0 fromDS1 (data packet from DS to STA)
0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // BSSID/MAC of AP
0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // Transmitter address
0x66, 0x55, 0x44, 0x33, 0x22, 0x33, // Source address
0x10, 0x86, // 0--fragment number; 0x861=2145--sequence number
};
static u8 ieee_hdr_mgmt[] =
{
0x00, 0x00, 0x00, 0x00, // FC 0x0000. 0--subtype; 0--type&version;
0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // BSSID/MAC of AP
0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // Transmitter address
0x66, 0x55, 0x44, 0x33, 0x22, 0x33, // Source address
0x10, 0x86, // 0--fragment number; 0x861=2145--sequence number
};
static u8 ieee_hdr_ack_cts[] =
{
0xd4, 0x00, 0x00, 0x00, // FC 0xd400. d--subtype; 4--type&version;
0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // mac addr of the peer
};
static u8 ieee_hdr_rts[] =
{
0xb4, 0x00, 0x00, 0x00, // FC 0xb400. b--subtype; 4--type&version;
0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // mac addr of the peer
0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // mac addr of the peer
};
// Generate random string
void gen_rand_str(int size, char *rand_char)
{
int i, randNum = 0;
// Seed the random number generator with packet size
srand(size);
for (i = 0; i < size; i++)
{
// First, pick a number between 0 and 25.
randNum = 255 * (rand() / (RAND_MAX + 1.0));
if(randNum == 0)
{
i--;
continue;
}
// Type cast to character
rand_char[i] = (char) randNum;
}
rand_char[i] = '\0';
}
// Put input mac address by strtol to ieee header
void assign_mac_addr(u64 a, u8 *hdr)
{
hdr[0] = ((a>>40)&0xFF);
hdr[1] = ((a>>32)&0xFF);
hdr[2] = ((a>>24)&0xFF);
hdr[3] = ((a>>16)&0xFF);
hdr[4] = ((a>>8 )&0xFF);
hdr[5] = ((a>>0 )&0xFF);
}
int flagHelp = 0;
void usage(void)
{
printf(
"(c)2006-2007 Andy Green Licensed under GPL2\n"
"(r)2020 Michael Tetemke Mehari \n"
"(r)2022 Xianjun Jiao "
"\n"
"Usage: inject_80211 [options] \n\nOptions\n"
"-m/--hw_mode (a,g,n)\n"
"-r/--rate_index (0,1,2,3,4,5,6,7)\n"
"-t/--packet_type (m/c/d/r for management/control/data/reserved)\n"
"-e/--sub_type (hex value. example:\n"
" 8/A/B/C for Beacon/Disassociation/Authentication/Deauth, when packet_type m\n"
" A/B/C/D for PS-Poll/RTS/CTS/ACK, when packet_type c\n"
" 0/1/2/8 for Data/Data+CF-Ack/Data+CF-Poll/QoS-Data, when packet_type d)\n"
"-a/--addr1 \n"
"-b/--addr2 \n"
"-i/--sgi_flag (0,1)\n"
"-n/--num_packets \n"
"-s/--payload_size \n"
"-d/--delay \n"
"-h this menu\n\n"
"Example:\n"
" iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up\n"
" inject_80211 mon0\n"
"\n");
exit(1);
}
int main(int argc, char *argv[])
{
u8 buffer[BUF_SIZE_TOTAL], sub_type=1, *ieee_hdr;
u64 addr1=1, addr2=2;
char szErrbuf[PCAP_ERRBUF_SIZE], rand_char[1484], hw_mode = 'n', packet_type = 'd';
int i, nLinkEncap = 0, r, rate_index = 0, sgi_flag = 0, num_packets = 10, payload_size = 64, packet_size, nDelay = 100000;
int ieee_hdr_len, payload_len;
pcap_t *ppcap = NULL;
while (1)
{
int nOptionIndex;
static const struct option optiona[] =
{
{ "hw_mode", required_argument, NULL, 'm' },
{ "rate_index", required_argument, NULL, 'r' },
{ "packet_type", required_argument, NULL, 't' },
{ "sub_type", required_argument, NULL, 'e' },
{ "addr1", required_argument, NULL, 'a' },
{ "addr2", required_argument, NULL, 'b' },
{ "sgi_flag", no_argument, NULL, 'i' },
{ "num_packets", required_argument, NULL, 'n' },
{ "payload_size", required_argument, NULL, 's' },
{ "delay", required_argument, NULL, 'd' },
{ "help", no_argument, &flagHelp, 1 },
{ 0, 0, 0, 0 }
};
int c = getopt_long(argc, argv, "m:r:t:e:a:b:i:n:s:d:h", optiona, &nOptionIndex);
if (c == -1)
break;
switch (c)
{
case 0: // long option
break;
case 'h':
usage();
break;
case 'm':
hw_mode = optarg[0];
break;
case 'r':
rate_index = atoi(optarg);
break;
case 't':
packet_type = optarg[0];
break;
case 'e':
sub_type = strtol(optarg, NULL, 16);
break;
case 'a':
addr1 = strtoll(optarg, NULL, 16);
break;
case 'b':
addr2 = strtoll(optarg, NULL, 16);
break;
case 'i':
sgi_flag = atoi(optarg);
break;
case 'n':
num_packets = atoi(optarg);
break;
case 's':
payload_size = atoi(optarg);
break;
case 'd':
nDelay = atoi(optarg);
break;
default:
printf("unknown switch %c\n", c);
usage();
break;
}
}
if (optind >= argc)
usage();
// open the interface in pcap
szErrbuf[0] = '\0';
ppcap = pcap_open_live(argv[optind], 800, 1, 20, szErrbuf);
if (ppcap == NULL)
{
printf("Unable to open interface %s in pcap: %s\n", argv[optind], szErrbuf);
return (1);
}
nLinkEncap = pcap_datalink(ppcap);
switch (nLinkEncap)
{
case DLT_PRISM_HEADER:
printf("DLT_PRISM_HEADER Encap\n");
break;
case DLT_IEEE802_11_RADIO:
printf("DLT_IEEE802_11_RADIO Encap\n");
break;
default:
printf("!!! unknown encapsulation on %s !\n", argv[1]);
return (1);
}
pcap_setnonblock(ppcap, 1, szErrbuf);
// Fill the IEEE hdr
if (packet_type == 'd') // data packet
{
ieee_hdr_data[0] = ( ieee_hdr_data[0]|(sub_type<<4) );
// ieee_hdr_data[9] = addr1;
assign_mac_addr(addr1, ieee_hdr_data+4);
// ieee_hdr_data[15] = addr2;
assign_mac_addr(addr2, ieee_hdr_data+10);
// ieee_hdr_data[21] = addr1;
assign_mac_addr(addr2, ieee_hdr_data+16);
ieee_hdr_len = sizeof(ieee_hdr_data);
ieee_hdr = ieee_hdr_data;
}
else if (packet_type == 'm') // managment packet
{
ieee_hdr_mgmt[0] = ( ieee_hdr_mgmt[0]|(sub_type<<4) );
// ieee_hdr_mgmt[9] = addr1;
assign_mac_addr(addr1, ieee_hdr_mgmt+4);
// ieee_hdr_mgmt[15] = addr2;
assign_mac_addr(addr2, ieee_hdr_mgmt+10);
// ieee_hdr_mgmt[21] = addr1;
assign_mac_addr(addr2, ieee_hdr_mgmt+16);
ieee_hdr_len = sizeof(ieee_hdr_mgmt);
ieee_hdr = ieee_hdr_mgmt;
}
else if (packet_type == 'c')
{
payload_size = 0;
if (sub_type == 0xC || sub_type == 0xD)
{
ieee_hdr_ack_cts[0] = ( ieee_hdr_ack_cts[0]|(sub_type<<4) );
// ieee_hdr_ack_cts[9] = addr1;
assign_mac_addr(addr1, ieee_hdr_ack_cts+4);
ieee_hdr_len = sizeof(ieee_hdr_ack_cts);
ieee_hdr = ieee_hdr_ack_cts;
}
else if (sub_type == 0xA || sub_type == 0xB)
{
ieee_hdr_rts[0] = ( ieee_hdr_rts[0]|(sub_type<<4) );
// ieee_hdr_rts[9] = addr1;
assign_mac_addr(addr1, ieee_hdr_rts+4);
// ieee_hdr_rts[15] = addr2;
assign_mac_addr(addr2, ieee_hdr_rts+10);
ieee_hdr_len = sizeof(ieee_hdr_rts);
ieee_hdr = ieee_hdr_rts;
}
else
{
printf("!!! sub_type %x is not supported yet!\n", sub_type);
return (1);
}
}
else
{
printf("!!! packet_type %c is not supported yet!\n", packet_type);
return (1);
}
// Generate random string
gen_rand_str(payload_size+4, rand_char); //4 for space reserved for crc
payload_len = strlen(rand_char);
packet_size = sizeof(u8aRadiotapHeader) + ieee_hdr_len + payload_len;
printf("mode = 802.11%c, rate index = %d, SHORT GI = %d, number of packets = %d and packet size = %d bytes, delay = %d usec\n", hw_mode, rate_index, sgi_flag, num_packets, packet_size, nDelay);
printf("packet_type %c sub_type %x payload_len %d ieee_hdr_len %d addr1 %016llx addr2 %016llx\n", packet_type, sub_type, payload_len, ieee_hdr_len, addr1, addr2);
if (packet_size > BUF_SIZE_MAX) {
printf("packet_size %d > %d! Quite\n", packet_size, BUF_SIZE_MAX);
return(1);
}
// Clear storage buffer
memset(buffer, 0, sizeof (buffer));
// Insert default radiotap header
memcpy(buffer, u8aRadiotapHeader, sizeof (u8aRadiotapHeader));
// Update radiotap header (i.e. hw_mode, rate, GI)
if(hw_mode == 'g' || hw_mode == 'a')
{
buffer[OFFSET_RATE] = u8aRatesToUse[rate_index];
buffer[MCS_OFFSET] = 0x00;
}
else
{
buffer[MCS_OFFSET] = 0x07;
if(sgi_flag)
buffer[GI_OFFSET] = IEEE80211_RADIOTAP_MCS_SGI;
buffer[MCS_RATE_OFFSET] = rate_index;
}
// Insert IEEE DATA header
memcpy(buffer + sizeof(u8aRadiotapHeader), ieee_hdr, ieee_hdr_len);
// Insert IEEE DATA payload
sprintf((char *)(buffer + sizeof(u8aRadiotapHeader) + ieee_hdr_len), "%s", rand_char);
// Inject packets
for(i = 1; i <= num_packets; i++)
{
r = pcap_inject(ppcap, buffer, packet_size);
if (r != packet_size) {
perror("Trouble injecting packet");
return (1);
}
printf("number of packets sent = %d\r", i);
fflush(stdout);
if (nDelay)
usleep(nDelay);
}
printf("\n");
return (0);
}
================================================
FILE: user_space/inject_80211/inject_80211.h
================================================
/*
* Author: Michael Mehari
* SPDX-FileCopyrightText: 2019 UGent
* SPDX-License-Identifier: AGPL-3.0-or-later
*/
#include
#include
#include
#include
#include
#include
#include
typedef unsigned long long int u64;
typedef unsigned int u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef u32 __le32;
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define le16_to_cpu(x) (x)
#define le32_to_cpu(x) (x)
#else
#define le16_to_cpu(x) ((((x)&0xff)<<8)|(((x)&0xff00)>>8))
#define le32_to_cpu(x) \
((((x)&0xff)<<24)|(((x)&0xff00)<<8)|(((x)&0xff0000)>>8)|(((x)&0xff000000)>>24))
#endif
#define unlikely(x) (x)
================================================
FILE: user_space/inject_80211/inject_80211.sh
================================================
#!/bin/bash
# Author: Michael Mehari
# SPDX-FileCopyrightText: 2019 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
HW_MODE='n'
COUNT=100
DELAY=1000
RATE=( 0 1 2 3 4 5 6 7 )
SIZE=( $(seq -s' ' 50 100 1450) )
IF="mon0"
for (( i = 0 ; i < ${#SIZE[@]} ; i++ )) do
for (( j = 0 ; j < ${#RATE[@]} ; j++ )) do
inject_80211 -m $HW_MODE -n $COUNT -d $DELAY -r ${RATE[$j]} -s ${SIZE[$i]} $IF
sleep 1
done
done
================================================
FILE: user_space/inject_80211/radiotap.c
================================================
/*
* Radiotap parser
*
* Copyright 2007 Andy Green
* Copyright 2009 Johannes Berg
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Alternatively, this software may be distributed under the terms of BSD
* license.
*
* See COPYING for more details.
*/
#include
// #include
// #include
// #include